cpu/samd21: added cpu clock configuration
- choosable between PLL and internal 8MHz osciallator - configurable to a wide range of frequencies
This commit is contained in:
Hauke Petersen
parent
acb06d8fe8
commit
164721657d
@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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@ -14,22 +14,80 @@
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* @brief Implementation of the CPU initialization
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @}
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*/
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#include "cpu.h"
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void clk_init(void);
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#include "periph_conf.h"
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/**
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* @brief Initialize the CPU, set IRQ priorities
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* @brief Configure clock sources and the cpu frequency
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*/
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static void clk_init(void)
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{
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/* enable clocks for the power, sysctrl and gclk modules */
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PM->APBAMASK.reg = (PM_APBAMASK_PM | PM_APBAMASK_SYSCTRL |
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PM_APBAMASK_GCLK);
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/* adjust NVM wait states, see table 42.30 (p. 1070) in the datasheet */
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#if (CLOCK_CORECLOCK > 24000000)
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PM->APBAMASK.reg |= PM_AHBMASK_NVMCTRL;
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NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(1);
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PM->APBAMASK.reg &= ~PM_AHBMASK_NVMCTRL;
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#endif
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/* configure internal 8MHz oscillator to run without prescaler */
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SYSCTRL->OSC8M.bit.PRESC = 0;
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SYSCTRL->OSC8M.bit.ONDEMAND = 0;
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SYSCTRL->OSC8M.bit.RUNSTDBY = 0;
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SYSCTRL->OSC8M.bit.ENABLE = 1;
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while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY));
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#if CLOCK_USE_PLL
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/* reset the GCLK module so it is in a known state */
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GCLK->CTRL.reg = GCLK_CTRL_SWRST;
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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/* setup generic clock 1 to feed DPLL with 1MHz */
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GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(8) |
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GCLK_GENDIV_ID(1));
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_OSC8M |
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GCLK_GENCTRL_ID(1));
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_GEN(1) |
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GCLK_CLKCTRL_ID(1) |
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GCLK_CLKCTRL_CLKEN);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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/* enable PLL */
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SYSCTRL->DPLLRATIO.reg = (SYSCTRL_DPLLRATIO_LDR(CLOCK_PLL_MUL));
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SYSCTRL->DPLLCTRLB.reg = (SYSCTRL_DPLLCTRLB_REFCLK_GCLK);
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SYSCTRL->DPLLCTRLA.reg = (SYSCTRL_DPLLCTRLA_ENABLE);
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while(!(SYSCTRL->DPLLSTATUS.reg &
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(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) ==
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(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK));
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/* select the PLL as source for clock generator 0 (CPU core clock) */
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GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(CLOCK_PLL_DIV) |
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GCLK_GENDIV_ID(0));
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_FDPLL96M |
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GCLK_GENCTRL_ID(0));
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#else /* do not use PLL, use internal 8MHz oscillator directly */
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GCLK->GENDIV.reg = (GCLK_GENDIV_DIV(CLOCK_DIV) |
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GCLK_GENDIV_ID(0));
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN |
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GCLK_GENCTRL_SRC_OSC8M |
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GCLK_GENCTRL_ID(0));
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#endif
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/* make sure we synchronize clock generator 0 before we go on */
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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}
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void cpu_init(void)
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{
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/* pm clk enable */
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PM->APBAMASK.reg = PM_APBAMASK_PM;
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/* port clk enable */
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PM->APBBMASK.reg |= PM_APBBMASK_PORT;
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/* disable the watchdog timer */
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WDT->CTRL.bit.ENABLE = 0;
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/* initialize the Cortex-M core */
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@ -37,28 +95,3 @@ void cpu_init(void)
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/* Initialise clock sources and generic clocks */
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clk_init();
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}
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/**
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* @brief Initialise clock sources and generic clocks
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*/
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void clk_init(void)
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{
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PM->APBAMASK.reg |= PM_APBAMASK_SYSCTRL;
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PM->APBAMASK.reg |= PM_APBAMASK_GCLK;
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SYSCTRL->OSC8M.bit.PRESC = 0;
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SYSCTRL->OSC8M.bit.ONDEMAND = 1;
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SYSCTRL->OSC8M.bit.RUNSTDBY = 0;
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SYSCTRL->OSC8M.bit.ENABLE = 1;
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/* Software reset the module to ensure it is re-initialized correctly */
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GCLK->CTRL.reg = GCLK_CTRL_SWRST;
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while (GCLK->CTRL.reg & GCLK_CTRL_SWRST);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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/* Select the correct generator */
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*((uint8_t*)&GCLK->GENDIV.reg) = 0;
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC8M | GCLK_CLKCTRL_GEN_GCLK0);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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}
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@ -176,6 +176,7 @@ typedef union {
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#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5u /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
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#define GCLK_GENCTRL_SRC_OSC8M_Val 0x6u /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
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#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7u /**< \brief (GCLK_GENCTRL) DFLL48M output */
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#define GCLK_GENCTRL_SRC_FDPLL96M_Val 0x8u /**< \brief (GCLK_GENCTRL) FDPLL96M output */
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#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
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@ -184,6 +185,7 @@ typedef union {
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#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_FDPLL96M (GCLK_GENCTRL_SRC_FDPLL96M_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
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#define GCLK_GENCTRL_GENEN (0x1u << GCLK_GENCTRL_GENEN_Pos)
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#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
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@ -82,7 +82,7 @@ int i2c_init_master(i2c_t dev, i2c_speed_t speed)
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pin_scl = I2C_SDA;
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pin_sda = I2C_SCL;
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i2c_pins = I2C_0_PINS;
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clock_source_speed = I2C_0_REF_F;
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clock_source_speed = CLOCK_CORECLOCK;
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sercom_core = SERCOM3_GCLK_ID_CORE;
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sercom_gclk_id_slow = SERCOM3_GCLK_ID_SLOW ;
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break;
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@ -66,9 +66,19 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
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f_baud = 1000000;
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break;
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case SPI_SPEED_5MHZ:
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#if CLOCK_CORECLOCK >= 5000000
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f_baud = 5000000;
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break;
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#else
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return -1;
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#endif
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case SPI_SPEED_10MHZ:
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#if CLOCK_CORECLOCK >= 10000000
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f_baud = 10000000;
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break;
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#else
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return -1;
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#endif
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}
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switch(conf)
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{
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@ -172,7 +182,9 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
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spi_dev->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE_SPI_MASTER;
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while (spi_dev->SYNCBUSY.reg);
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spi_dev->BAUD.bit.BAUD = (uint8_t) (((uint32_t) SPI_0_F_REF) / (2 * f_baud) - 1); /* Syncronous mode*/
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spi_dev->BAUD.bit.BAUD = (uint8_t) (((uint32_t)CLOCK_CORECLOCK) / (2 * f_baud) - 1); /* Syncronous mode*/
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spi_dev->CTRLA.reg |= (SERCOM_SPI_CTRLA_DOPO(dopo))
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| (SERCOM_SPI_CTRLA_DIPO(dipo))
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| (cpha << SERCOM_SPI_CTRLA_CPHA_Pos)
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@ -48,13 +48,27 @@ timer_conf_t config[TIMER_NUMOF];
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*/
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int timer_init(tim_t dev, unsigned int us_per_ticks, void (*callback)(int))
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{
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/* configure GCLK0 to feed TC3, TC4 and TC5 */;
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GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | (TC3_GCLK_ID << GCLK_CLKCTRL_ID_Pos)));
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/* at the moment, the timer can only run at 1MHz */
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if (us_per_ticks != 1) {
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return -1;
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}
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/* select the clock generator depending on the main clock source:
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* GCLK0 (1MHz) if we use the internal 8MHz oscillator
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* GCLK1 (8MHz) if we use the PLL */
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#if CLOCK_USE_PLL
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/* configure GCLK1 (configured to 1MHz) to feed TC3, TC4 and TC5 */;
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GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK1 | (TC3_GCLK_ID << GCLK_CLKCTRL_ID_Pos)));
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while (GCLK->STATUS.bit.SYNCBUSY);
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/* TC4 and TC5 share the same channel */
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GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK1 | (TC4_GCLK_ID << GCLK_CLKCTRL_ID_Pos)));
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#else
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/* configure GCLK0 to feed TC3, TC4 and TC5 */;
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GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | (TC3_GCLK_ID << GCLK_CLKCTRL_ID_Pos)));
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/* TC4 and TC5 share the same channel */
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GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | (TC4_GCLK_ID << GCLK_CLKCTRL_ID_Pos)));
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#endif
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while (GCLK->STATUS.bit.SYNCBUSY);
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/* select the timer and enable the timer specific peripheral clocks */
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switch (dev) {
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#if TIMER_0_EN
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@ -68,8 +82,13 @@ int timer_init(tim_t dev, unsigned int us_per_ticks, void (*callback)(int))
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while (TIMER_0_DEV.CTRLA.bit.SWRST);
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/* choosing 16 bit mode */
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TIMER_0_DEV.CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT16_Val;
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/* sourced by 8MHz with Presc 64 results in 125kHz clk */
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TIMER_0_DEV.CTRLA.bit.PRESCALER = TC_CTRLA_PRESCALER_DIV64_Val;
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#if CLOCK_USE_PLL
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/* sourced by 1MHz with prescaler 1 results in... you know it :-) */
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TIMER_0_DEV.CTRLA.bit.PRESCALER = TC_CTRLA_PRESCALER_DIV1_Val;
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#else
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/* sourced by 8MHz with Presc 8 results in 1MHz clk */
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TIMER_0_DEV.CTRLA.bit.PRESCALER = TC_CTRLA_PRESCALER_DIV8_Val;
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#endif
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/* choose normal frequency operation */
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TIMER_0_DEV.CTRLA.bit.WAVEGEN = TC_CTRLA_WAVEGEN_NFRQ_Val;
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break;
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@ -87,8 +106,13 @@ int timer_init(tim_t dev, unsigned int us_per_ticks, void (*callback)(int))
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TIMER_1_DEV.CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT32_Val;
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#if CLOCK_USE_PLL
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/* sourced by 1MHz and prescaler 1 to reach 1MHz */
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TIMER_1_DEV.CTRLA.bit.PRESCALER = TC_CTRLA_PRESCALER_DIV1_Val;
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#else
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/* sourced by 8MHz with Presc 8 results in 1Mhz clk */
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TIMER_1_DEV.CTRLA.bit.PRESCALER = TC_CTRLA_PRESCALER_DIV8_Val;
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#endif
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/* choose normal frequency operation */
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TIMER_1_DEV.CTRLA.bit.WAVEGEN = TC_CTRLA_WAVEGEN_NFRQ_Val;
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break;
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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@ -15,6 +15,7 @@
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Troels Hoffmeyer <troels.d.hoffmeyer@gmail.com>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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@ -53,8 +54,6 @@ static inline void irq_handler(uart_t uartnum, SercomUsart *uart);
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*/
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static uart_conf_t uart_config[UART_NUMOF];
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static uint64_t _long_division(uint64_t n, uint64_t d);
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg)
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{
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/* initialize basic functionality */
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@ -81,11 +80,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t t
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int uart_init_blocking(uart_t uart, uint32_t baudrate)
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{
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/* Calculate the BAUD value */
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uint64_t temp1 = ((16 * ((uint64_t)baudrate)) << 32);
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uint64_t ratio = _long_division(temp1 , UART_0_REF_F);
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uint64_t scale = ((uint64_t)1 << 32) - ratio;
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uint64_t baud_calculated = (65536 * scale) >> 32;
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uint32_t baud = ((((uint32_t)CLOCK_CORECLOCK * 10) / baudrate) / 16);
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switch (uart) {
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#if UART_0_EN
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@ -97,9 +92,6 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
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GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | (SERCOM0_GCLK_ID_CORE << GCLK_CLKCTRL_ID_Pos)));
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while (GCLK->STATUS.bit.SYNCBUSY);
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GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | (SERCOM0_GCLK_ID_SLOW << GCLK_CLKCTRL_ID_Pos)));
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while (GCLK->STATUS.bit.SYNCBUSY);
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/* configure PINS to input/output*/
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UART_0_PORT.DIRSET.reg = (1 << UART_0_TX_PIN); /* tx's direction is output */
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UART_0_PORT.PINCFG[UART_0_RX_PIN % 32].bit.INEN = true; /* buffer rx pin's value */
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@ -117,20 +109,17 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
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/* set to LSB, asynchronous mode without parity, PAD0 Tx, PAD1 Rx,
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* 16x over-sampling, internal clk */
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UART_0_DEV.CTRLA.reg = SERCOM_USART_CTRLA_DORD \
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| SERCOM_USART_CTRLA_FORM(0x0) \
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| SERCOM_USART_CTRLA_SAMPA(0x0) \
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| SERCOM_USART_CTRLA_TXPO(0x0) \
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| SERCOM_USART_CTRLA_RXPO(0x1) \
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| SERCOM_USART_CTRLA_SAMPR(0x0) \
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| SERCOM_USART_CTRLA_SAMPR(0x1) \
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| SERCOM_USART_CTRLA_MODE_USART_INT_CLK;
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/* Set baud rate */
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UART_0_DEV.BAUD.bit.BAUD = baud_calculated;
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UART_0_DEV.BAUD.FRAC.FP = (baud % 10);
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UART_0_DEV.BAUD.FRAC.BAUD = (baud / 10);
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/* enable receiver and transmitter, one stop bit*/
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UART_0_DEV.CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
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while(UART_0_DEV.SYNCBUSY.bit.CTRLB);
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break;
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#endif
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}
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@ -226,29 +215,4 @@ static inline void irq_handler(uint8_t uartnum, SercomUsart *dev)
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}
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}
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static uint64_t _long_division(uint64_t n, uint64_t d)
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{
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int32_t i;
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uint64_t q = 0, r = 0, bit_shift;
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for (i = 63; i >= 0; i--) {
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bit_shift = (uint64_t)1 << i;
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r = r << 1;
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if (n & bit_shift) {
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r |= 0x01;
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}
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if (r >= d) {
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r = r - d;
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q |= bit_shift;
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}
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}
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return q;
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}
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#endif /* UART_NUMOF */
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