From 1659a71ed0f236449f77e9cf7fc5aa0a14af7610 Mon Sep 17 00:00:00 2001 From: Anton Gerasimov Date: Sun, 10 Jun 2018 23:29:03 +0200 Subject: [PATCH] cpu/cc13x2: Add support for cc13x2 MCUs Signed-off-by: Anton Gerasimov --- cpu/cc13x2/Makefile | 7 + cpu/cc13x2/Makefile.features | 1 + cpu/cc13x2/Makefile.include | 7 + cpu/cc13x2/cpu.c | 41 ++++ cpu/cc13x2/doc.txt | 17 ++ cpu/cc13x2/include/cc13x2_aux.h | 346 +++++++++++++++++++++++++++++++ cpu/cc13x2/include/cc13x2_fcfg.h | 147 +++++++++++++ cpu/cc13x2/include/cc13x2_prcm.h | 237 +++++++++++++++++++++ cpu/cc13x2/include/cpu_conf.h | 40 ++++ cpu/cc13x2/include/periph_cpu.h | 35 ++++ cpu/cc13x2/ldscripts/cc1352r1.ld | 19 ++ cpu/cc13x2/periph/Makefile | 1 + cpu/cc13x2/pm.c | 32 +++ 13 files changed, 930 insertions(+) create mode 100644 cpu/cc13x2/Makefile create mode 100644 cpu/cc13x2/Makefile.features create mode 100644 cpu/cc13x2/Makefile.include create mode 100644 cpu/cc13x2/cpu.c create mode 100644 cpu/cc13x2/doc.txt create mode 100644 cpu/cc13x2/include/cc13x2_aux.h create mode 100644 cpu/cc13x2/include/cc13x2_fcfg.h create mode 100644 cpu/cc13x2/include/cc13x2_prcm.h create mode 100644 cpu/cc13x2/include/cpu_conf.h create mode 100644 cpu/cc13x2/include/periph_cpu.h create mode 100644 cpu/cc13x2/ldscripts/cc1352r1.ld create mode 100644 cpu/cc13x2/periph/Makefile create mode 100644 cpu/cc13x2/pm.c diff --git a/cpu/cc13x2/Makefile b/cpu/cc13x2/Makefile new file mode 100644 index 0000000000..f02c58d576 --- /dev/null +++ b/cpu/cc13x2/Makefile @@ -0,0 +1,7 @@ +# Define the module that is built: +MODULE = cpu + +# Add a list of subdirectories, that should also be built: +DIRS = periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/cc26xx_cc13xx + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/cc13x2/Makefile.features b/cpu/cc13x2/Makefile.features new file mode 100644 index 0000000000..34f3697b8d --- /dev/null +++ b/cpu/cc13x2/Makefile.features @@ -0,0 +1 @@ +-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features diff --git a/cpu/cc13x2/Makefile.include b/cpu/cc13x2/Makefile.include new file mode 100644 index 0000000000..c0379f895a --- /dev/null +++ b/cpu/cc13x2/Makefile.include @@ -0,0 +1,7 @@ +CPU_ARCH = cortex-m4f +CPU_VARIANT = x2 + +VECTORS_O = $(BINDIR)/cc26xx_cc13xx/vectors.o + +include ${RIOTCPU}/cc26xx_cc13xx/Makefile.include +include $(RIOTMAKE)/arch/cortexm.inc.mk diff --git a/cpu/cc13x2/cpu.c b/cpu/cc13x2/cpu.c new file mode 100644 index 0000000000..6a29a35bb1 --- /dev/null +++ b/cpu/cc13x2/cpu.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 Leon George + * Copyright (C) 2018 Anton Gerasimov + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_cc13x2 + * @{ + * + * @file + * @brief implementation of the CPU initialization + * + * @author Leon M. George , Anton Gerasimov + * @} + */ + +#include "cpu.h" +#include "periph_conf.h" +#include "periph/init.h" +#include "stdio_base.h" + +#include "cc13x2_prcm.h" + +/** + * @brief Initialize the CPU, set IRQ priorities + */ +void cpu_init(void) +{ + /* initialize the Cortex-M core */ + cortexm_init(); + + /* initialize stdio prior to periph_init() to allow use of DEBUG() there */ + stdio_init(); + + /* trigger static peripheral initialization */ + periph_init(); +} diff --git a/cpu/cc13x2/doc.txt b/cpu/cc13x2/doc.txt new file mode 100644 index 0000000000..a6cf885893 --- /dev/null +++ b/cpu/cc13x2/doc.txt @@ -0,0 +1,17 @@ +/** + * @defgroup cpu_cc13x2 TI CC13x2 + * @ingroup cpu + * @brief Texas Instruments CC13x2 Cortex-M4F MCU specific code + */ + +/** + * @defgroup cpu_cc13x2_peripheral_memory_map TI CC13x2 peripheral memory map + * @ingroup cpu + * @brief Texas Instruments CC13x2 memory mappings for peripherals + */ + +/** + * @defgroup cpu_cc13x2_definitions TI CC13x2 definitions + * @ingroup cpu_cc13x2 + * @brief Texas Instruments CC13x2 specific defines + */ diff --git a/cpu/cc13x2/include/cc13x2_aux.h b/cpu/cc13x2/include/cc13x2_aux.h new file mode 100644 index 0000000000..c02adaf0e2 --- /dev/null +++ b/cpu/cc13x2/include/cc13x2_aux.h @@ -0,0 +1,346 @@ +/* + * Copyright (C) 2016 Leon George + * Copyright (C) 2018 Anton Gerasimov + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ +/** + * @ingroup cpu_cc13x2_definitions + * @{ + * + * @file + * @brief CC13x2 AUX register definitions + */ + +#ifndef CC13X2_AUX_H +#define CC13X2_AUX_H + +#include + +#include "cc26xx_cc13xx.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * AUX_AIODIO registers + */ +typedef struct { + reg32_t IOMODE; /**< input output mode */ + reg32_t GPIODIE; /**< gpio data input enable */ + reg32_t IOPOE; /**< io peripheral output enable */ + reg32_t GPIODOUT; /**< gpio data output */ + reg32_t GPIODIN; /**< gpio data input */ + reg32_t GPIODOUTSET; /**< gpio data out set */ + reg32_t GPIODOUTCLR; /**< gpio data out clear */ + reg32_t GPIODOUTTGL; /**< gpio data out toggle */ + reg32_t IO0PSEL; /**< i/o 0 peripheral select */ + reg32_t IO1PSEL; /**< i/o 1 peripheral select */ + reg32_t IO2PSEL; /**< i/o 2 peripheral select */ + reg32_t IO3PSEL; /**< i/o 3 peripheral select */ + reg32_t IO4PSEL; /**< i/o 4 peripheral select */ + reg32_t IO5PSEL; /**< i/o 5 peripheral select */ + reg32_t IO6PSEL; /**< i/o 6 peripheral select */ + reg32_t IO7PSEL; /**< i/o 7 peripheral select */ + reg32_t IOMODEH; /**< input output mode high */ + reg32_t IOMODEL; /**< input output mode low */ +} aux_aiodio_regs_t; + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define AUX_AIODIO0_BASE 0x400CC000 /**< AUX_AIODIO0 base address */ +#define AUX_AIODIO1_BASE 0x400CD000 /**< AUX_AIODIO1 base address */ +#define AUX_AIODIO2_BASE 0x400CE000 /**< AUX_AIODIO2 base address */ +#define AUX_AIODIO3_BASE 0x400CF000 /**< AUX_AIODIO3 base address */ +/** @} */ + +#define AUX_AIODIO0 ((aux_aiodio_regs_t *) (AUX_AIODIO0_BASE)) /**< AUX_AIODIO0 register bank */ +#define AUX_AIODIO1 ((aux_aiodio_regs_t *) (AUX_AIODIO1_BASE)) /**< AUX_AIODIO1 register bank */ +#define AUX_AIODIO2 ((aux_aiodio_regs_t *) (AUX_AIODIO2_BASE)) /**< AUX_AIODIO2 register bank */ +#define AUX_AIODIO3 ((aux_aiodio_regs_t *) (AUX_AIODIO3_BASE)) /**< AUX_AIODIO3 register bank */ + + +/** + * AUX_TDC registers + */ +typedef struct { + reg32_t CTL; /**< control */ + reg32_t STAT; /**< status */ + reg32_t RESULT; /**< result */ + reg32_t SATCFG; /**< saturaion configuration */ + reg32_t TRIGSRC; /**< trigger source */ + reg32_t TRIGCNT; /**< trigger counter */ + reg32_t TRIGCNTLOAD; /**< trigger counter load */ + reg32_t TRIGCNTCFG; /**< trigger counter config */ + reg32_t PRECTL; /**< prescaler control */ + reg32_t PRECNT; /**< prescaler counter */ +} aux_tdc_regs_t; + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define AUX_TDC_BASE 0x400C4000 /**< AUX_TDC base address */ +/** @} */ + +#define AUX_TDC ((aux_tdc_regs_t *) (AUX_TDC_BASE)) /**< AUX_TDC register bank */ + + +/** + * AUX_EVCTL registers + */ +typedef struct { + reg32_t EVSTAT0; /**< event status 0 */ + reg32_t EVSTAT1; /**< event status 1 */ + reg32_t EVSTAT2; /**< event status 2 */ + reg32_t EVSTAT3; /**< event status 3 */ + reg32_t SCEWEVSEL0; /**< sensor controller engine wait event configuration 0 */ + reg32_t SCEWEVSEL1; /**< sensor controller engine wait event configuration 1 */ + reg32_t DMACTL; /**< direct memoty access control */ + reg32_t __reserved; /**< meh */ + reg32_t SWEVSET; /**< software event set */ + reg32_t EVTOAONFLAGS; /**< events to AON domain flags */ + reg32_t EVTOAONPOL; /**< events to AON domain polarity */ + reg32_t EVTOAONFLAGSCLR; /**< events to AON domain clear */ + reg32_t EVTOMCUFLAGS; /**< event to MCU domain flags */ + reg32_t EVTOMCUPOL; /**< event to MCU domain polarity */ + reg32_t EVTOMCUFLAGSCLR; /**< events to MCU domain flags clear */ + reg32_t COMBEVTOMCUMASK; /**< combined event to MCU domain mask */ + reg32_t PROGDLY; /**< programmable delay */ + reg32_t MANUAL; /**< manual */ + reg32_t EVSTAT0L; /**< event status 0 low */ + reg32_t EVSTAT0H; /**< event status 0 high */ + reg32_t EVSTAT1L; /**< event status 1 low */ + reg32_t EVSTAT1H; /**< event status 1 high */ + reg32_t EVSTAT2L; /**< event status 2 low */ + reg32_t EVSTAT2H; /**< event status 2 high */ + reg32_t EVSTAT3L; /**< event status 3 low */ + reg32_t EVSTAT3H; /**< event status 3 high */ + +} aux_evtcl_regs_t; + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define AUX_EVCTL_BASE 0x400C5000 /**< AUX_EVCTL base address */ +/** @} */ + +#define AUX_EVCTL ((aux_evctl_regs_t *) (AUX_EVCTL_BASE)) /**< AUX_EVCTL register bank */ + + +/** + * AUX_SYSIF registers + */ +typedef struct { + reg32_t OPMODEREQ; /**< operational mode request */ + reg32_t OPMODEACK; /**< operational mode acknowledgement */ + reg32_t PROGWU0CFG; /**< programmanble wakeup 0 configuration */ + reg32_t PROGWU1CFG; /**< programmanble wakeup 0 configuration */ + reg32_t PROGWU2CFG; /**< programmanble wakeup 0 configuration */ + reg32_t PROGWU3CFG; /**< programmanble wakeup 0 configuration */ + reg32_t SWUTRIG; /**< software wakeup triggers */ + reg32_t WUFLAGS; /**< wakeup flags */ + reg32_t WUFLAGSCLR; /**< wakeup flags clear */ + reg32_t WUGATE; /**< wakeup gate */ + reg32_t VECCFG0; /**< vector configuration 0 */ + reg32_t VECCFG1; /**< vector configuration 1 */ + reg32_t VECCFG2; /**< vector configuration 2 */ + reg32_t VECCFG3; /**< vector configuration 3 */ + reg32_t VECCFG4; /**< vector configuration 4 */ + reg32_t VECCFG5; /**< vector configuration 5 */ + reg32_t VECCFG6; /**< vector configuration 6 */ + reg32_t VECCFG7; /**< vector configuration 7 */ + reg32_t EVSYNCRATE; /**< event synchronization rate */ + reg32_t PEROPRATE; /**< peripheral operational rate */ + reg32_t ADCCLKCTL; /**< ADC clock control */ + reg32_t TDCCLKCTL; /**< TDC clock control */ + reg32_t TDCREFCLKCTL; /**< TDC reference clock control */ + reg32_t TIMER2CLKCTL; /**< AUX_TIMER2 clock control */ + reg32_t TIMER2CLKSTAT; /**< AUX_TIMER2 clock status */ + reg32_t TIMER2CLKSWITCH; /**< AUX_TIMER2 clock switch */ + reg32_t TIMER2DBGCTL; /**< AUX_TIMER2 debug control */ + reg32_t __reserved1; /**< meh */ + reg32_t CLKSHIFTDET; /**< clock shift detection */ + reg32_t RECHARGETRIG; /**< recharge trigger */ + reg32_t RECHARGEDET; /**< recharge detector */ + reg32_t RTCSUBSECINC0; /**< RTC sub-second increment 0 */ + reg32_t RTCSUBSECINC1; /**< RTC sub-second increment 1 */ + reg32_t RTCSUBSECINCCTL; /**< RTC sub-second increment control */ + reg32_t RTCSEC; /**< RTC second */ + reg32_t RTCSUBSEC; /**< RTC sub-second */ + reg32_t RTCEVCLR; /**< RTC event clear */ + reg32_t BATMONBAT; /**< battery voltage */ + reg32_t __reserved2; /**< meh */ + reg32_t BATMONTEMP; /**< batmon temperature */ + reg32_t TIMERHALT; /**< timer halt */ + reg32_t __reserved3[3]; /**< meh */ + reg32_t TIMER2BRIDGE; /**< timer2 bridge */ + reg32_t SWPWRPROF; /**< software power profiler */ +} aux_sysif_regs_t; + +/** @} */ + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define AUX_SYSIF_BASE 0x400C6000 /**< AUX_SYSIF base address */ +/** @} */ + +#define AUX_SYSIF ((aux_wuc_regs_t *) (AUX_SYSIF_BASE)) /**< AUX_SYSIF register bank */ + + +/** + * AUX_TIMER registers + */ +typedef struct { + reg32_t T0CFG; /**< timer 0 config */ + reg32_t T0CTL; /**< timer 0 control */ + reg32_t T0TARGET; /**< timer 0 target */ + reg32_t T0CNTR; /**< timer 0 counter */ + reg32_t T1CFG; /**< timer 1 config */ + reg32_t T1TARGET; /**< timer 1 target */ + reg32_t T1CTL; /**< timer 1 control */ + reg32_t T1CNTR; /**< timer 0 counter */ +} aux_timer01_regs_t; + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define AUX_TIMER01_BASE 0x400C7000 /**< AUX_WUC base address */ +/** @} */ + +#define AUX_TIMER01 ((aux_timer01_regs_t *) (AUX_TIMER01_BASE)) /**< AUX_TIMER01 register bank */ + + +/** + * AUX_TIMER2 registers + */ +typedef struct { + reg32_t CTL; /**< timer 2 control */ + reg32_t TARGET; /**< timer 2 target */ + reg32_t SHDWTARGET; /**< timer 2 shadow target */ + reg32_t CNTR; /**< timer 2 counter */ + reg32_t PRECFG; /**< timer 2 prescaler config */ + reg32_t EVCTL; /**< timer 2 event control */ + reg32_t PULSETRIG; /**< timer 2 pulse trigger */ + reg32_t __reserved[25]; /**< meh */ + reg32_t CH0EVCFG; /**< timer 2 channel 0 event configuration */ + reg32_t CH0CCFG; /**< timer 2 channel 0 capture configuration */ + reg32_t CH0PCC; /**< timer 2 channel 0 pipeline capture compare */ + reg32_t CH0CC; /**< timer 2 channel 0 capture compare */ + reg32_t CH1EVCFG; /**< timer 2 channel 1 event configuration */ + reg32_t CH1CCFG; /**< timer 2 channel 1 capture configuration */ + reg32_t CH1PCC; /**< timer 2 channel 1 pipeline capture compare */ + reg32_t CH1CC; /**< timer 2 channel 1 capture compare */ + reg32_t CH2EVCFG; /**< timer 2 channel 2 event configuration */ + reg32_t CH2CCFG; /**< timer 2 channel 2 capture configuration */ + reg32_t CH2PCC; /**< timer 2 channel 2 pipeline capture compare */ + reg32_t CH2CC; /**< timer 2 channel 2 capture compare */ + reg32_t CH3EVCFG; /**< timer 2 channel 3 event configuration */ + reg32_t CH3CCFG; /**< timer 2 channel 3 capture configuration */ + reg32_t CH3PCC; /**< timer 2 channel 3 pipeline capture compare */ + reg32_t CH3CC; /**< timer 2 channel 3 capture compare */ +} aux_timer2_regs_t; + + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define AUX_TIMER2_BASE 0x400C3000 /**< AUX_WUC base address */ +/** @} */ +#define AUX_TIMER2 ((aux_timer2_regs_t *) (AUX_TIMER2_BASE)) /**< AUX_TIMER2 register bank */ + + + +/** + * AUX_SMPH registers + */ +typedef struct { + reg32_t SMPH0; /**< semaphore 0 */ + reg32_t SMPH1; /**< semaphore 1 */ + reg32_t SMPH2; /**< semaphore 2 */ + reg32_t SMPH3; /**< semaphore 3 */ + reg32_t SMPH4; /**< semaphore 4 */ + reg32_t SMPH5; /**< semaphore 5 */ + reg32_t SMPH6; /**< semaphore 6 */ + reg32_t SMPH7; /**< semaphore 7 */ + reg32_t AUTOTAKE; /**< sticky request for single semaphore */ +} aux_smph_regs_t; + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define AUX_SMPH_BASE 0x400C8000 /**< AUX_WUC base address */ +/* @} */ + +#define AUX_SMPH ((aux_smph_regs_t *) (AUX_SMPH_BASE)) /**< AUX_SMPH register bank */ + + +/** + * AUX_ANAIF registers + */ +typedef struct { + reg32_t __reserved1[4]; /**< meh */ + reg32_t ADCCTL; /**< ADC control */ + reg32_t ADCFIFOSTAT; /**< ADC fifo status */ + reg32_t ADCFIFO; /**< ADC fifo */ + reg32_t ADCTRIG; /**< ADC trigger */ + reg32_t ISRCCTL; /**< current source control */ + reg32_t __reserved2[3]; /**< meh */ + reg32_t DACCTL; /**< DAC control */ + reg32_t LPMBIASCTL; /**< low-power mode bias control */ + reg32_t DACSMPLCTL; /**< DAC sample control */ + reg32_t DACSMPLCFG0; /**< DAC sample configuration 0 */ + reg32_t DACSMPLCFG1; /**< DAC sample configuration 1 */ + reg32_t DACVALUE; /**< DAC value */ + reg32_t DACSTAT; /**< DAC status */ +} aux_anaif_regs_t; + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define AUX_ANAIF_BASE 0x400C9000 /**< AUX_WUC base address */ +/** @} */ + +#define AUX_ANAIF ((aux_anaif_regs_t *) (AUX_ANAIF_BASE)) /**< AUX_ANAIF register bank */ + + +/** + * ADI_4_AUX registers + */ +typedef struct { + reg8_t MUX0; /**< multiplexer 0 */ + reg8_t MUX1; /**< multiplexer 1 */ + reg8_t MUX2; /**< multiplexer 2 */ + reg8_t MUX3; /**< multiplexer 3 */ + reg8_t ISRC; /**< current source */ + reg8_t COMP; /**< comparator */ + reg8_t MUX4; /**< multiplexer 4 */ + reg8_t ADC0; /**< ADC control 0 */ + reg8_t ADC1; /**< ADC control 1 */ + reg8_t ADCREF0; /**< ADC reference 0 */ + reg8_t ADCREF1; /**< ADC reference 1 */ +} adi_4_aux_regs_t; + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define ADI_4_AUX_BASE 0x400CB000 /**< AUX_WUC base address */ +/** @} */ + +#define ADI_4_AUX ((adi_4_aux_regs_t *) (ADI_4_AUX_BASE)) /**< ADI_4_AUX register bank */ + + +#define ADDI_SEM AUX_SMPH->SMPH0 /**< the semamphore used for ADDI */ + +#ifdef __cplusplus +} /* end extern "C" */ +#endif + +#endif /* CC13X2_AUX_H */ + +/** @}*/ diff --git a/cpu/cc13x2/include/cc13x2_fcfg.h b/cpu/cc13x2/include/cc13x2_fcfg.h new file mode 100644 index 0000000000..6f5c87eb16 --- /dev/null +++ b/cpu/cc13x2/include/cc13x2_fcfg.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2016 Leon George + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ +/** + * @ingroup cpu_cc13x2_definitions + * @{ + * + * @file + * @brief CC13x2 FCFG register definitions + */ + +#ifndef CC13X2_FCFG_H +#define CC13X2_FCFG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define FCFG_BASE 0x50001000 /**< base address of FCFG memory */ +/*@}*/ + +/** + * FCFG registers + */ +typedef struct { + uint8_t __reserved1[0xA0]; /**< meh */ + /* TODO does it pad here? */ + reg32_t MISC_CONF_1; /**< misc config */ + reg32_t MISC_CONF_2; /**< misc config */ + reg32_t __reserved2[7]; /**< meh */ + reg32_t CONFIG_FE_CC26; /**< internal */ + reg32_t CONFIG_FE_CC13; /**< internal */ + reg32_t CONFIG_RF_COMMON; /**< internal */ + reg32_t CONFIG_SYNTH_DIV2_CC26_2G4; /**< config of synthesizer in divide-by-2-mode */ + reg32_t CONFIG_SYNTH_DIV2_CC13_2G4; /**< config of synthesizer in divide-by-2-mode */ + reg32_t CONFIG_SYNTH_DIV2_CC26_1G; /**< config of synthesizer in divide-by-2-mode */ + reg32_t CONFIG_SYNTH_DIV2_CC13_1G; /**< config of synthesizer in divide-by-2-mode */ + reg32_t CONFIG_SYNTH_DIV4_CC26; /**< config of synthesizer in divide-by-4-mode */ + reg32_t CONFIG_SYNTH_DIV4_CC13; /**< config of synthesizer in divide-by-4-mode */ + reg32_t CONFIG_SYNTH_DIV5; /**< config of synthesizer in divide-by-5-mode */ + reg32_t CONFIG_SYNTH_DIV6_CC26; /**< config of synthesizer in divide-by-5-mode */ + reg32_t CONFIG_SYNTH_DIV6_CC13; /**< config of synthesizer in divide-by-5-mode */ + reg32_t CONFIG_SYNTH_DIV10; /**< config of synthesizer in divide-by-10-mode */ + reg32_t CONFIG_SYNTH_DIV12_CC26; /**< config of synthesizer in divide-by-12-mode */ + reg32_t CONFIG_SYNTH_DIV12_CC13; /**< config of synthesizer in divide-by-12-mode */ + reg32_t CONFIG_SYNTH_DIV15; /**< config of synthesizer in divide-by-15-mode */ + reg32_t CONFIG_SYNTH_DIV30; /**< config of synthesizer in divide-by-30-mode */ + reg32_t __reserved3[23]; /**< meh */ + reg32_t FLASH_NUMBER; /**< manufacturing lot number */ + reg32_t __reserved4; /**< meh */ + reg32_t FLASH_COORDINATE; /**< chip coordinates on a wafer */ + reg32_t FLASH_E_P; /**< internal */ + reg32_t FLASH_C_E_P_R; /**< internal */ + reg32_t FLASH_P_R_PV; /**< internal */ + reg32_t FLASH_EH_SEQ; /**< internal */ + reg32_t FLASH_VHV_E; /**< internal */ + reg32_t FLASH_PP; /**< internal */ + reg32_t FLASH_PROG_EP; /**< internal */ + reg32_t FLASH_ERA_PW; /**< internal */ + reg32_t FLASH_VHV; /**< internal */ + reg32_t FLASH_VHV_PV; /**< internal */ + reg32_t FLASH_V; /**< internal */ + reg32_t __reserved5[38]; /**< meh */ + reg32_t USER_ID; /* user identification */ + reg32_t __reserved6[6]; /**< meh */ + reg32_t FLASH_OTP_DATA3; /**< internal */ + reg32_t ANA2_TRIM; /**< internal */ + reg32_t LDO_TRIM; /**< internal */ + reg32_t __reserved7[11]; /**< meh */ + reg32_t MAC_BLE_0; /**< MAC BLE address 0 */ + reg32_t MAC_BLE_1; /**< MAC BLE address 1 */ + reg32_t MAC_15_4_0; /**< MAC IEEE 802.15.4 address 0 */ + reg32_t MAC_15_4_1; /**< MAC IEEE 802.15.4 address 1 */ + reg32_t __reserved8[4]; /**< meh */ + reg32_t FLASH_OTP_DATA4; /**< Internal */ + reg32_t MISC_TRIM; /**< Miscelaneous trim parameters */ + reg32_t RCOSC_HF_TEMPCOMP; /**< Internal */ + reg32_t __reserved9; /**< meh */ + reg32_t ICEPICK_DEVICE_ID; /**< IcePick Device Identification */ + reg32_t FCFG1_REVISION; /**< Factory configuration revision */ + reg32_t MISC_OTP_DATA; /**< Miscelanous OTP data */ + reg32_t __reserved10[8]; /**< meh */ + reg32_t IOCONF; /**< I/O Configuration */ + reg32_t __reserved11; /**< meh */ + reg32_t CONFIG_IF_ADC; /**< Internal */ + reg32_t CONFIG_OSC_TOP; /**< Internal */ + reg32_t __reserved12[2]; /**< meh */ + reg32_t SOC_ADC_ABS_GAIN; /**< AUX_ADC gain in absolute reference mode */ + reg32_t SOC_ADC_REL_GAIN; /**< AUX_ADC gain in relative reference mode */ + reg32_t __reserved13; /**< meh */ + reg32_t SOC_ADC_OFFSET_INT; /**< AUX_ADC temperature offsets in absolute reference mode */ + reg32_t SOC_ADC_REF_TRIM_AND_OFFSET_EXT; /**< Internal */ + reg32_t AMPCOMP_TH1; /**< Internal */ + reg32_t AMPCOMP_TH2; /**< Internal */ + reg32_t AMPCOMP_CTRL1; /**< Internal */ + reg32_t ANABYPASS_VALUE2; /**< Internal */ + reg32_t __reserved14[2]; /**< meh */ + reg32_t VOLT_TRIM; /**< Internal */ + reg32_t OSC_CONF; /**< OSC configuration */ + reg32_t FREQ_OFFSET; /**< Internal */ + reg32_t __reserved15; /**< meh */ + reg32_t MISC_OTP_DATA_1; /**< Internal */ + reg32_t PWD_CURR_20C; /**< power down current control 20C */ + reg32_t PWD_CURR_35C; /**< power down current control 35C */ + reg32_t PWD_CURR_50C; /**< power down current control 50C */ + reg32_t PWD_CURR_65C; /**< power down current control 65C */ + reg32_t PWD_CURR_80C; /**< power down current control 80C */ + reg32_t PWD_CURR_95C; /**< power down current control 95C */ + reg32_t PWD_CURR_110C; /**< power down current control 110C */ + reg32_t PWD_CURR_125C; /**< power down current control 125C */ + reg32_t __reserved16[5]; /**< meh */ + reg32_t SHDW_DIE_ID_0; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_0.* */ + reg32_t SHDW_DIE_ID_1; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_1.* */ + reg32_t SHDW_DIE_ID_2; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_2.* */ + reg32_t SHDW_DIE_ID_3; /**< shadow of JTAG_TAP::EFUSE::DIE_ID_3.* */ + reg32_t __reserved17[2]; /**< meh */ + reg32_t SHDW_OSC_BIAS_LDO_TRIM; /**< Internal */ + reg32_t SHDW_ANA_TRIM; /**< Internal */ + reg32_t __reserved18[3]; /**< meh */ + reg32_t DAC_BIAS_CNF; /**< Internal */ + reg32_t __reserved19[2]; /**< meh */ + reg32_t TFW_PROBE; /**< Internal */ + reg32_t TFW_FT; /**< Internal */ + reg32_t DAC_CAL0; /**< Internal */ + reg32_t DAC_CAL1; /**< Internal */ + reg32_t DAC_CAL2; /**< Internal */ + reg32_t DAC_CAL3; /**< Internal */ +} fcfg_regs_t; + +#define FCFG ((fcfg_regs_t *) (FCFG_BASE)) /**< FCFG register bank */ + +#ifdef __cplusplus +} /* end extern "C" */ +#endif + +#endif /* CC13X2_FCFG_H */ + +/*@}*/ diff --git a/cpu/cc13x2/include/cc13x2_prcm.h b/cpu/cc13x2/include/cc13x2_prcm.h new file mode 100644 index 0000000000..dc67483bbe --- /dev/null +++ b/cpu/cc13x2/include/cc13x2_prcm.h @@ -0,0 +1,237 @@ +/* + * Copyright (C) 2016 Leon George + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_cc13x2_definitions + * @{ + * + * @file + * @brief CC13x2 PRCM register definitions + */ + +#ifndef CC13X2_PRCM_H +#define CC13X2_PRCM_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * DDI_0_OSC registers + */ +typedef struct { + reg32_t CTL0; /**< control 0 */ + reg32_t CTL1; /**< control 1 */ + reg32_t RADCEXTCFG; /**< RADC external config */ + reg32_t AMPCOMPCTL; /**< amplitude compensation control */ + reg32_t AMPCOMPTH1; /**< amplitude compensation threshold 1 */ + reg32_t AMPCOMPTH2; /**< amplitude compensation threshold 2 */ + reg32_t ANABYPASSVAL1; /**< analog bypass values 1 */ + reg32_t ANABYPASSVAL2; /**< analog bypass values 2 */ + reg32_t ATESTCTL; /**< analog test control */ + reg32_t ADCDOUBLERNANOAMPCTL; /**< ADC doubler nanoamp control */ + reg32_t XOSCHFCTL; /**< XOSCHF control */ + reg32_t LFOSCCTL; /**< low frequency oscillator control */ + reg32_t RCOSCHFCTL; /**< RCOSCHF control */ + reg32_t RCOSCHMCTL; /**< RCOSCHM control */ + reg32_t STAT0; /**< status 0 */ + reg32_t STAT1; /**< status 1 */ + reg32_t STAT2; /**< status 2 */ +} ddi0_osc_regs_t; + +/** + * @brief DDI_0_OSC register values + * @{ + */ +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL 0x0000000C +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL 0x00000180 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 /* enable clock loss detection */ +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 /* bypass XOSC_LF and use digital input clock from AON foor xosx_lf (precuations in datasheet) */ +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 +#define DDI_0_OSC_CTL0_DCDC_SRC_SEL 0x01000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION 0x0C000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 +/** @} */ + +/** @ingroup cpu_cc13x2_peripheral_memory_map + * @{ + */ +#define DDI0_OSC_BASE 0x400CA000 /**< DDI0_OSC base address */ +/*@}*/ + +#define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE)) /**< DDI_0_OSC register bank */ + +/** +* AON_PMCTL registers +*/ +typedef struct { + reg32_t __reserved1; /**< meh */ + reg32_t AUXSCECLK; /**< AUX SCE management */ + reg32_t RAMCFG; /**< RAM configuration */ + reg32_t __reserved2; /**< meh */ + reg32_t PWRCTL; /**< Power management control */ + reg32_t PWRSTAT; /**< Power status */ + reg32_t SHUTDOWN; /**< Shutdown control */ + reg32_t RECHARGECFG; /**< Recharge controller configuration */ + reg32_t RECHARGESTAT; /**< Recharge controller status */ + reg32_t OSCCFG; /**< Oscillator configuration */ + reg32_t RESETCTL; /**< Reset control */ + reg32_t SLEEPCTL; /**< Reset control */ + reg32_t __reserved3; /**< meh */ + reg32_t JTAGCFG; /**< JTAG configuration */ + reg32_t JTAGUSERCODE; /**< JTAG USERCODE */ +} aon_pmctl_regs_t; + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define AON_PMCTL_BASE 0x40090000 /**< AON_PMCTL base address */ +/*@}*/ + +#define AON_PMCTL ((aon_pmctl_regs_t *) (AON_PMCTL_BASE)) /**< AON_PMCTL register bank */ + +/** + * PRCM registers + */ +typedef struct { + reg32_t INFRCLKDIVR; /**< infrastructure clock division factor for run mode */ + reg32_t INFRCLKDIVS; /**< infrastructure clock division factor for sleep mode */ + reg32_t INFRCLKDIVDS; /**< infrastructure clock division factor for deep sleep mode */ + reg32_t VDCTL; /**< MCU voltage domain control */ + reg32_t __reserved1[6]; /**< meh */ + reg32_t CLKLOADCTL; /**< clock load control */ + reg32_t RFCCLKG; /**< RFC clock gate */ + reg32_t VIMSCLKG; /**< VIMS clock gate */ + reg32_t __reserved2[2]; /**< meh */ + reg32_t SECDMACLKGR; /**< TRNG, CRYPTO, and UDMA clock gate for run mode */ + reg32_t SECDMACLKGS; /**< TRNG, CRYPTO, and UDMA clock gate for sleep mode */ + reg32_t SECDMACLKGDS; /**< TRNG, CRYPTO, and UDMA clock gate for deep sleep mode */ + reg32_t GPIOCLKGR; /**< GPIO clock gate for run mode */ + reg32_t GPIOCLKGS; /**< GPIO clock gate for sleep mode */ + reg32_t GPIOCLKGDS; /**< GPIO clock gate for deep sleep mode */ + reg32_t GPTCLKGR; /**< GPT clock gate for run mode */ + reg32_t GPTCLKGS; /**< GPT clock gate for sleep mode */ + reg32_t GPTCLKGDS; /**< GPT clock gate for deep sleep mode */ + reg32_t I2CCLKGR; /**< I2C clock gate for run mode */ + reg32_t I2CCLKGS; /**< I2C clock gate for sleep mode */ + reg32_t I2CCLKGDS; /**< I2C clock gate for deep sleep mode */ + reg32_t UARTCLKGR; /**< UART clock gate for run mode */ + reg32_t UARTCLKGS; /**< UART clock gate for sleep mode */ + reg32_t UARTCLKGDS; /**< UART clock gate for deep sleep mode */ + reg32_t SSICLKGR; /**< SSI clock gate for run mode */ + reg32_t SSICLKGS; /**< SSI clock gate for sleep mode */ + reg32_t SSICLKGDS; /**< SSI clock gate for deep sleep mode */ + reg32_t I2SCLKGR; /**< I2S clock gate for run mode */ + reg32_t I2SCLKGS; /**< I2S clock gate for sleep mode */ + reg32_t I2SCLKGDS; /**< I2S clock gate for deep sleep mode */ + reg32_t __reserved3[9]; /**< meh */ + reg32_t SYSBUSCLKDIV; /**< System bus clock division factor */ + reg32_t CPUCLKDIV; /**< CPU clock division factor */ + reg32_t PERBUSCPUCLKDIV; /**< Peripheral bus division factor */ + reg32_t __reserved4; /**< meh */ + reg32_t PERDMACLKDIV; /**< DMA clock division factor */ + reg32_t I2SBCLKSEL; /**< I2S clock select */ + reg32_t GPTCLKDIV; /**< GPT scalar */ + reg32_t I2SCLKCTL; /**< I2S clock control */ + reg32_t I2SMCLKDIV; /**< MCLK division ratio */ + reg32_t I2SBCLKDIV; /**< BCLK division ratio */ + reg32_t I2SWCLKDIV; /**< WCLK division ratio */ + reg32_t __reserved5[4]; /**< meh */ + reg32_t RESETSECDMA; /**< Reset SEC and UDMA */ + reg32_t RESETGPIO; /**< Reset GPIO */ + reg32_t RESETGPT; /**< Reset GPTs */ + reg32_t RESETI2C; /**< Reset I2C */ + reg32_t RESETUART; /**< Reset UART */ + reg32_t RESETSSI; /**< Reset SSI */ + reg32_t RESETI2S; /**< Reset I2S */ + reg32_t __reserved6[8]; /**< meh */ + reg32_t PDCTL0; /**< power domain control */ + reg32_t PDCTL0RFC; /**< RFC power domain control */ + reg32_t PDCTL0SERIAL; /**< SERIAL power domain control */ + reg32_t PDCTL0PERIPH; /**< PERIPH power domain control */ + reg32_t __reserved7; /**< meh */ + reg32_t PDSTAT0; /**< power domain status */ + reg32_t PDSTAT0RFC; /**< RFC power domain status */ + reg32_t PDSTAT0SERIAL; /**< SERIAL power domain status */ + reg32_t PDSTAT0PERIPH; /**< PERIPH power domain status */ + reg32_t __reserved8[11]; /**< meh */ + reg32_t PDCTL1; /**< power domain control */ + reg32_t __reserved9; /**< power domain control */ + reg32_t PDCTL1CPU; /**< CPU power domain control */ + reg32_t PDCTL1RFC; /**< RFC power domain control */ + reg32_t PDCTL1VIMS; /**< VIMS power domain control */ + reg32_t __reserved10; /**< meh */ + reg32_t PDSTAT1; /**< power domain status */ + reg32_t PDSTAT1BUS; /**< BUS power domain status */ + reg32_t PDSTAT1RFC; /**< RFC power domain status */ + reg32_t PDSTAT1CPU; /**< CPU power domain status */ + reg32_t PDSTAT1VIMS; /**< VIMS power domain status */ + reg32_t __reserved11[9]; /**< meh */ + reg32_t RFCBITS; /**< Control to RFC */ + reg32_t RFCMODESEL; /**< selected RFC mode */ + reg32_t RFCMODEHWOPT; /**< allowed RFC modes */ + reg32_t __reserved12[2]; /**< meh */ + reg32_t PWRPROFSTAT; /**< power profiler register */ + reg32_t __reserved13[14]; /**< meh */ + reg32_t MCUSRAMCFG; /**< MCU SRAM configuration */ + reg32_t __reserved14; /**< meh */ + reg32_t RAMRETEN; /**< memory retention control */ + reg32_t __reserved15[27]; /**< meh */ + reg32_t OSCIMSC; /**< oscillator interrupt mask */ + reg32_t OSCRIS; /**< oscillator raw interrupt status */ + reg32_t OSCICR; /**< oscillator raw interrupt clear */ +} prcm_regs_t; + +/** + * @brief PRCM register values + * @{ + */ +#define CLKLOADCTL_LOAD 0x1 +#define CLKLOADCTL_LOADDONE 0x2 + +#define PDCTL0_RFC_ON 0x1 +#define PDCTL0_SERIAL_ON 0x2 +#define PDCTL0_PERIPH_ON 0x4 + +#define PDSTAT0_RFC_ON 0x1 +#define PDSTAT0_SERIAL_ON 0x2 +#define PDSTAT0_PERIPH_ON 0x4 + +#define PDCTL1_CPU_ON 0x2 +#define PDCTL1_RFC_ON 0x4 +#define PDCTL1_VIMS_ON 0x8 + +#define PDSTAT1_CPU_ON 0x2 +#define PDSTAT1_RFC_ON 0x4 +#define PDSTAT1_VIMS_ON 0x8 +/** @} */ + +/** @ingroup cpu_specific_peripheral_memory_map + * @{ + */ +#define PRCM_BASE 0x40082000 /**< PRCM base address */ +/*@}*/ + +#define PRCM ((prcm_regs_t *) (PRCM_BASE)) /**< PRCM register bank */ + +#ifdef __cplusplus +} /* end extern "C" */ +#endif + +#endif /* CC13X2_PRCM_H */ + +/*@}*/ diff --git a/cpu/cc13x2/include/cpu_conf.h b/cpu/cc13x2/include/cpu_conf.h new file mode 100644 index 0000000000..f064013a43 --- /dev/null +++ b/cpu/cc13x2/include/cpu_conf.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016 Leon George + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @addtogroup cpu_cc13x2 + * @{ + * + * @file + * @brief Implementation specific CPU configuration options + * + * @author Leon M. George + * @author Anton Gerasimov + * + */ + +#ifndef CPU_CONF_H +#define CPU_CONF_H + +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#include "cpu_conf_cc26xx_cc13xx.h" + +#include "cc13x2_aux.h" +#include "cc13x2_fcfg.h" +#include "cc13x2_prcm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* CPU_CONF_H */ +/** @} */ diff --git a/cpu/cc13x2/include/periph_cpu.h b/cpu/cc13x2/include/periph_cpu.h new file mode 100644 index 0000000000..319f805e61 --- /dev/null +++ b/cpu/cc13x2/include/periph_cpu.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2016 Leon George + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_cc13x2 + * @{ + * + * @file + * @brief CPU specific definitions for internal peripheral handling + * + * @author Leon M. George + */ + +#ifndef PERIPH_CPU_H +#define PERIPH_CPU_H + +#include "periph_cpu_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Empty, but makes linter happy + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CPU_H */ +/** @} */ diff --git a/cpu/cc13x2/ldscripts/cc1352r1.ld b/cpu/cc13x2/ldscripts/cc1352r1.ld new file mode 100644 index 0000000000..7cdad64b71 --- /dev/null +++ b/cpu/cc13x2/ldscripts/cc1352r1.ld @@ -0,0 +1,19 @@ +/** + * @addtogroup cpu_cc13x2 + * @{ + * + * @file + * @brief linker script for cc13x2 MCUs + * + * @} + */ + +/* Memory Space Definitions: */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x58000 + gpram : ORIGIN = 0x11000000, LENGTH = 8K /* configurable as cache. 20K here, 8K there, and 2K in the ld-script of cc13x2ware */ + ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 20K /* sram */ +} + +INCLUDE cortexm_base.ld diff --git a/cpu/cc13x2/periph/Makefile b/cpu/cc13x2/periph/Makefile new file mode 100644 index 0000000000..a36df249ac --- /dev/null +++ b/cpu/cc13x2/periph/Makefile @@ -0,0 +1 @@ +include $(RIOTMAKE)/periph.mk diff --git a/cpu/cc13x2/pm.c b/cpu/cc13x2/pm.c new file mode 100644 index 0000000000..19c0d5fa4e --- /dev/null +++ b/cpu/cc13x2/pm.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Kaspar Schleiser + * @author Hauke Petersen + * + * @} + */ + +#include "cpu.h" +#include "periph/pm.h" + +#ifdef PROVIDES_PM_SET_LOWEST_CORTEXM +void pm_set_lowest(void) +{ + /* don't do anything here */ +} +#endif