Merge pull request #14502 from benpicco/cpu/sam0_common/flashpage_cleanup
cpu/sam0_common: flashpage: clean up implementation
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Francisco
GitHub
commit
16f47fc893
@ -21,6 +21,7 @@
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* use in RIOT is actually the row size as specified in the datasheet.
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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*
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* @}
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*/
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@ -30,10 +31,10 @@
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#include "cpu.h"
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#include "periph/flashpage.h"
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#define NVMCTRL_PAC_BIT (0x00000002)
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#define FLASH_MAIN 0
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#define FLASH_RWWEE 1
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#define MIN(x, y) (((x) < (y)) ? (x) : (y))
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/**
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* @brief NVMCTRL selection macros
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@ -44,10 +45,9 @@
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#define _NVMCTRL NVMCTRL
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#endif
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static inline void wait_nvm_is_ready(void) __attribute__((always_inline));
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static inline void wait_nvm_is_ready(void)
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{
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#if defined(CPU_SAML1X) || defined(CPU_SAMD5X)
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#ifdef NVMCTRL_STATUS_READY
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while (!_NVMCTRL->STATUS.bit.READY) {}
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#else
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while (!_NVMCTRL->INTFLAG.bit.READY) {}
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@ -60,29 +60,133 @@ static void _unlock(void)
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#ifdef REG_PAC_WRCTRL
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PAC->WRCTRL.reg = (PAC_WRCTRL_KEY_CLR | ID_NVMCTRL);
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#else
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if (PAC1->WPSET.reg & NVMCTRL_PAC_BIT) {
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PAC1->WPCLR.reg = NVMCTRL_PAC_BIT;
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}
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PAC1->WPCLR.reg = PAC1_WPROT_DEFAULT_VAL;
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#endif
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}
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static void _lock(void)
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{
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wait_nvm_is_ready();
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/* put peripheral access lock for the NVMCTRL peripheral */
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#ifdef REG_PAC_WRCTRL
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PAC->WRCTRL.reg = (PAC_WRCTRL_KEY_SET | ID_NVMCTRL);
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#else
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if (PAC1->WPCLR.reg & NVMCTRL_PAC_BIT) {
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PAC1->WPSET.reg = NVMCTRL_PAC_BIT;
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}
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PAC1->WPSET.reg = PAC1_WPROT_DEFAULT_VAL;
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#endif
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}
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#ifdef FLASHPAGE_RWWEE_NUMOF
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void flashpage_write_raw_internal(void *target_addr, const void *data, size_t len, int flash_type)
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static void _cmd_clear_page_buffer(void)
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{
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wait_nvm_is_ready();
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#ifdef NVMCTRL_CTRLB_CMDEX_KEY
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_NVMCTRL->CTRLB.reg = (NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_PBC);
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#else
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void flashpage_write_raw(void *target_addr, const void *data, size_t len)
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_PBC);
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#endif
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}
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static void _cmd_erase_row(void)
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{
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wait_nvm_is_ready();
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/* send Row/Block erase command */
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#ifdef NVMCTRL_CTRLB_CMDEX_KEY
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_NVMCTRL->CTRLB.reg = (NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_EB);
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#else
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER);
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#endif
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}
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static void _cmd_write_page(void)
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{
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wait_nvm_is_ready();
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/* write page */
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#ifdef NVMCTRL_CTRLB_CMDEX_KEY
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_NVMCTRL->CTRLB.reg = (NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_WP);
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#else
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP);
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#endif
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}
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static void _write_page(void* dst, const void *data, size_t len, void (*cmd_write)(void))
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{
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uint32_t *dst32 = dst;
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_unlock();
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_cmd_clear_page_buffer();
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/* copy whole words */
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const uint32_t *data32 = data;
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while (len) {
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*dst32++ = *data32++;
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len -= sizeof(uint32_t);
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}
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cmd_write();
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_lock();
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}
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static void _erase_page(void* page, void (*cmd_erase)(void))
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{
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uintptr_t page_addr = (uintptr_t)page;
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/* erase given page (the ADDR register uses 16-bit addresses) */
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_unlock();
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/* ADDR drives the hardware (16-bit) address to the NVM when a command is executed using CMDEX.
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* 8-bit addresses must be shifted one bit to the right before writing to this register.
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*/
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#if defined(CPU_SAMD21) || defined(CPU_SAML21)
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page_addr >>= 1;
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#endif
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/* set Row/Block start address */
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_NVMCTRL->ADDR.reg = page_addr;
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cmd_erase();
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_lock();
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}
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/* dst must be row-aligned */
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static void _write_row(uint8_t *dst, const void *_data, size_t len, size_t chunk_size,
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void (*cmd_write)(void))
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{
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const uint8_t *data = _data;
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/* One RIOT page is FLASHPAGE_PAGES_PER_ROW SAM0 flash pages (a row) as
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* defined in the file cpu/sam0_common/include/cpu_conf.h, therefore we
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* have to split the write into FLASHPAGE_PAGES_PER_ROW raw calls
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* underneath, each writing a physical page in chunks of 4 bytes (see
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* flashpage_write_raw)
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* The erasing is done once as a full row is always erased.
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*/
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while (len) {
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size_t chunk = MIN(len, chunk_size);
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_write_page(dst, data, chunk, cmd_write);
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data += chunk;
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dst += chunk;
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len -= chunk;
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}
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}
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void flashpage_write(int page, const void *data)
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{
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assert((unsigned)page < FLASHPAGE_NUMOF);
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_erase_page(flashpage_addr(page), _cmd_erase_row);
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if (data == NULL) {
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return;
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}
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_write_row(flashpage_addr(page), data, FLASHPAGE_SIZE, NVMCTRL_PAGE_SIZE,
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_cmd_write_page);
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}
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void flashpage_write_raw(void *target_addr, const void *data, size_t len)
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{
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/* The actual minimal block size for writing is 16B, thus we
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* assert we write on multiples and no less of that length.
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@ -94,155 +198,69 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
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((unsigned)data % FLASHPAGE_RAW_ALIGNMENT)));
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/* ensure the length doesn't exceed the actual flash size */
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#ifdef FLASHPAGE_RWWEE_NUMOF
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if (flash_type == FLASH_RWWEE) {
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assert(((unsigned)target_addr + len) <=
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(CPU_FLASH_RWWEE_BASE + (FLASHPAGE_SIZE * FLASHPAGE_RWWEE_NUMOF)));
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} else {
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#endif
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assert(((unsigned)target_addr + len) <=
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(CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)));
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#ifdef FLASHPAGE_RWWEE_NUMOF
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}
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#endif
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assert(((unsigned)target_addr + len) <=
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(CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)));
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uint32_t *dst = (uint32_t *)target_addr;
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const uint32_t *data_addr = data;
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_write_page(target_addr, data, len, _cmd_write_page);
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/* write 4 bytes in one go */
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len /= 4;
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_unlock();
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#ifdef NVMCTRL_CTRLB_CMDEX_KEY
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_NVMCTRL->CTRLB.reg = (NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_PBC);
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#else
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_PBC);
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#endif
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wait_nvm_is_ready();
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for (unsigned i = 0; i < len; i++) {
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*dst++ = *data_addr++;
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}
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#ifdef FLASHPAGE_RWWEE_NUMOF
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if (flash_type == FLASH_RWWEE) {
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#ifdef CPU_SAML1X
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/* SAML1X use the same Write Page command for both flash memories */
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP);
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#else
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_RWWEEWP);
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#endif
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} else {
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#endif
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#ifdef NVMCTRL_CTRLB_CMDEX_KEY
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_NVMCTRL->CTRLB.reg = (NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_WP);
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#else
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP);
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#endif
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#ifdef FLASHPAGE_RWWEE_NUMOF
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}
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#endif
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wait_nvm_is_ready();
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_lock();
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}
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#ifdef FLASHPAGE_RWWEE_NUMOF
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void flashpage_write_internal(int page, const void *data, int flash_type)
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#else
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void flashpage_write(int page, const void *data)
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#endif
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static void _cmd_erase_row_rwwee(void)
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{
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uint32_t *page_addr;
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#ifdef FLASHPAGE_RWWEE_NUMOF
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if (flash_type == FLASH_RWWEE) {
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page_addr = (uint32_t *)flashpage_rwwee_addr(page);
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} else {
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#endif
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page_addr = (uint32_t *)flashpage_addr(page);
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#ifdef FLASHPAGE_RWWEE_NUMOF
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}
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#endif
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/* erase given page (the ADDR register uses 16-bit addresses) */
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_unlock();
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#if defined(CPU_SAML1X) || defined(CPU_SAMD5X)
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/* Ensure address alignment */
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_NVMCTRL->ADDR.reg = (((uint32_t)page_addr) & 0xfffffffe);
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#else
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_NVMCTRL->ADDR.reg = (((uint32_t)page_addr) >> 1);
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#endif
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#ifdef FLASHPAGE_RWWEE_NUMOF
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if (flash_type == FLASH_RWWEE) {
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#ifdef CPU_SAML1X
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/* SAML1X use the same Erase command for both flash memories */
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER);
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#else
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_RWWEEER);
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#endif
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} else {
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#endif
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#ifdef NVMCTRL_CTRLB_CMDEX_KEY
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_NVMCTRL->CTRLB.reg = (NVMCTRL_CTRLB_CMDEX_KEY | NVMCTRL_CTRLB_CMD_EB);
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#else
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER);
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#endif
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#ifdef FLASHPAGE_RWWEE_NUMOF
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}
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#endif
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wait_nvm_is_ready();
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_lock();
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/* write data to page */
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if (data != NULL) {
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/* One RIOT page is FLASHPAGE_PAGES_PER_ROW SAM0 flash pages (a row) as
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* defined in the file cpu/sam0_common/include/cpu_conf.h, therefore we
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* have to split the write into FLASHPAGE_PAGES_PER_ROW raw calls
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* underneath, each writing a physical page in chunks of 4 bytes (see
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* flashpage_write_raw)
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* The erasing is done once as a full row is always reased.
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*/
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for (unsigned curpage = 0; curpage < FLASHPAGE_PAGES_PER_ROW; curpage++) {
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#ifdef FLASHPAGE_RWWEE_NUMOF
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flashpage_write_raw_internal(page_addr + (curpage * NVMCTRL_PAGE_SIZE / 4),
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(void *) ((uint32_t *) data + (curpage * NVMCTRL_PAGE_SIZE / 4)),
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NVMCTRL_PAGE_SIZE, flash_type);
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/* send erase row command */
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#ifdef NVMCTRL_CTRLA_CMD_RWWEEER
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_RWWEEER);
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#else
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flashpage_write_raw(page_addr + (curpage * NVMCTRL_PAGE_SIZE / 4),
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(void *) ((uint32_t *) data + (curpage * NVMCTRL_PAGE_SIZE / 4)),
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NVMCTRL_PAGE_SIZE);
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/* SAML1X use the same Erase command for both flash memories */
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_ER);
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#endif
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}
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}
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}
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#ifdef FLASHPAGE_RWWEE_NUMOF
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/*
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* If RWWEE flash is present then we create an additional layer for the write functions
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* so we can specify the type (either MAIN or RWWEE) we want to access, keeping the
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* standard API unchanged and code for systems without RWWEE at a minimum at the cost
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* of some more #defines in the code
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*/
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void flashpage_write_raw(void *target_addr, const void *data, size_t len)
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static void _cmd_write_page_rwwee(void)
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{
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flashpage_write_raw_internal(target_addr, data, len, FLASH_MAIN);
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}
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wait_nvm_is_ready();
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void flashpage_write(int page, const void *data)
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{
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assert((uint32_t)page < FLASHPAGE_NUMOF);
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flashpage_write_internal(page, data, FLASH_MAIN);
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/* write page */
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#ifdef NVMCTRL_CTRLA_CMD_RWWEEWP
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_RWWEEWP);
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#else
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/* SAML1X use the same Write Page command for both flash memories */
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_NVMCTRL->CTRLA.reg = (NVMCTRL_CTRLA_CMDEX_KEY | NVMCTRL_CTRLA_CMD_WP);
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#endif
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}
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void flashpage_rwwee_write_raw(void *target_addr, const void *data, size_t len)
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{
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flashpage_write_raw_internal(target_addr, data, len, FLASH_RWWEE);
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/* The actual minimal block size for writing is 16B, thus we
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* assert we write on multiples and no less of that length.
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*/
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assert(!(len % FLASHPAGE_RAW_BLOCKSIZE));
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/* ensure 4 byte aligned writes */
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assert(!(((unsigned)target_addr % FLASHPAGE_RAW_ALIGNMENT) ||
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((unsigned)data % FLASHPAGE_RAW_ALIGNMENT)));
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assert(((unsigned)target_addr + len) <=
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(CPU_FLASH_RWWEE_BASE + (FLASHPAGE_SIZE * FLASHPAGE_RWWEE_NUMOF)));
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_write_page(target_addr, data, len, _cmd_write_page_rwwee);
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}
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void flashpage_rwwee_write(int page, const void *data)
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{
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assert((uint32_t)page < FLASHPAGE_RWWEE_NUMOF);
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assert((unsigned)page < FLASHPAGE_RWWEE_NUMOF);
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flashpage_write_internal(page, data, FLASH_RWWEE);
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_erase_page(flashpage_rwwee_addr(page), _cmd_erase_row_rwwee);
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if (data == NULL) {
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return;
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}
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_write_row(flashpage_rwwee_addr(page), data, FLASHPAGE_SIZE, NVMCTRL_PAGE_SIZE,
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_cmd_write_page_rwwee);
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}
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#endif
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#endif /* FLASHPAGE_RWWEE_NUMOF */
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