From 17b322494dcfe41e61cae035adcac22c124cfe2f Mon Sep 17 00:00:00 2001 From: PeterKietzmann Date: Mon, 10 Oct 2016 11:19:08 +0200 Subject: [PATCH] cpu/msp430: remove non-effective code for msp430f2xxx --- cpu/msp430fxyz/periph/spi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cpu/msp430fxyz/periph/spi.c b/cpu/msp430fxyz/periph/spi.c index a5d8254ad1..d5440121ea 100644 --- a/cpu/msp430fxyz/periph/spi.c +++ b/cpu/msp430fxyz/periph/spi.c @@ -53,16 +53,16 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed) /* set polarity and phase */ switch (conf) { case SPI_CONF_FIRST_RISING: - SPI_DEV->TCTL |= (USART_TCTL_CKPH & ~(USART_TCTL_CKPL)); + SPI_DEV->TCTL |= USART_TCTL_CKPH; break; case SPI_CONF_SECOND_RISING: - SPI_DEV->TCTL |= (~(USART_TCTL_CKPH) & ~(USART_TCTL_CKPL)); + /* nothing to be done here */ break; case SPI_CONF_FIRST_FALLING: SPI_DEV->TCTL |= (USART_TCTL_CKPH & USART_TCTL_CKPL); break; case SPI_CONF_SECOND_FALLING: - SPI_DEV->TCTL |= (~(USART_TCTL_CKPH) & USART_TCTL_CKPL); + SPI_DEV->TCTL |= USART_TCTL_CKPL; break; default: /* invalid clock setting */ @@ -128,7 +128,7 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed) SPI_DEV->CTL0 |= USCI_SPI_CTL0_CKPH; break; case SPI_CONF_SECOND_RISING: - /* nothong to be done here */ + /* nothing to be done here */ break; case SPI_CONF_FIRST_FALLING: SPI_DEV->CTL0 |= (USCI_SPI_CTL0_CKPH & USCI_SPI_CTL0_CKPL);