cpu/atmega_common: Cleanup state flags
- Use one byte of RAM to track both IRQ and UART TX state - Fix incorrect use of volatile
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@ -59,16 +59,88 @@ extern "C"
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/** @} */
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/**
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* @brief global in-ISR state variable
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* @name Flags for the current state of the ATmega MCU
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* @{
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*/
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extern volatile uint8_t atmega_in_isr;
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#define ATMEGA_STATE_FLAG_ISR (0x80U) /**< In ISR */
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#define ATMEGA_STATE_FLAG_UART0_TX (0x01U) /**< TX pending for UART 0 */
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#define ATMEGA_STATE_FLAG_UART1_TX (0x02U) /**< TX pending for UART 1 */
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#define ATMEGA_STATE_FLAG_UART_TX(x) (0x01U << x) /**< TX pending for UART x */
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/** @} */
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/**
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* @brief Run this code on entering interrupt routines
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* @brief Global variable containing the current state of the MCU
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*
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* @note This variable is updated from IRQ context; access to it should
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* be wrapped into @ref irq_disable and @ref irq_restore or
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* @ref atmega_get_state should be used.
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*
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* Contents:
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* 7 6 5 4 3 2 1 0
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* +---+---+---+---+---+---+---+---+
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* |IRQ| unused |TX1|TX0|
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* +---+---+---+---+---+---+---+---+
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* | Label | Description |
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* |:-------|:--------------------------------------------------------------|
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* | IRQ | This bit is set when in IRQ context |
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* | unused | This bits are currently not used |
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* | TX1 | This bit is set when on UART1 TX is pending |
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* | TX0 | This bit is set when on UART0 TX is pending |
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*/
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extern uint8_t atmega_state;
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/**
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* @brief Atomically read the state (@ref atmega_state)
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*
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* This function guarantees that the read is not optimized out, not reordered
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* and done atomically. This does not mean that by the time return value is
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* processed that it still reflects the value currently stored in
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* @ref atmega_state.
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*
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* Using ASM rather than C11 atomics has less overhead, as not every access to
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* the state has to be performed atomically: Those done from ISR will not be
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* interrupted (no support for nested interrupts) and barriers at the begin and
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* end of the ISRs make sure the access takes place before IRQ context is left.
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*/
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static inline uint8_t atmega_get_state(void)
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{
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uint8_t state;
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__asm__ volatile(
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"lds %[state], atmega_state \n\t"
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: [state] "=r" (state)
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:
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: "memory"
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);
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return state;
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}
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/**
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* @brief Run this code on entering interrupt routines
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*/
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static inline void atmega_enter_isr(void)
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{
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atmega_in_isr = 1;
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/* This flag is only called from IRQ context, and nested IRQs are not
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* supported as of now. The flag will be unset before the IRQ context is
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* left, so no need to use memory barriers or atomics here
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*/
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atmega_state |= ATMEGA_STATE_FLAG_ISR;
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}
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/**
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* @brief Check if TX on any present UART device is still pending
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*
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* @retval !=0 At least on UART device is still sending data out
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* @retval 0 No UART is currently sending data
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*/
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static inline int atmega_is_uart_tx_pending(void)
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{
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uint8_t state = atmega_get_state();
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return (state & (ATMEGA_STATE_FLAG_UART0_TX | ATMEGA_STATE_FLAG_UART1_TX));
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}
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/**
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@ -23,6 +23,7 @@
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#include <stdint.h>
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#include <stdio.h>
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#include <stdint.h>
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#include "irq.h"
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#include "cpu.h"
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@ -32,7 +33,7 @@
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static uint8_t atmega_get_interrupt_state(void);
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static void atmega_set_interrupt_state(uint8_t state);
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volatile uint8_t atmega_in_isr = 0;
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uint8_t atmega_state = 0;
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__attribute__((always_inline)) static inline uint8_t atmega_get_interrupt_state(void)
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{
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@ -88,7 +89,6 @@ void irq_restore(unsigned int state)
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*/
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int irq_is_in(void)
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{
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int result = atmega_in_isr;
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__asm__ volatile("" ::: "memory");
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return result;
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uint8_t state = atmega_get_state();
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return (state & ATMEGA_STATE_FLAG_ISR);
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}
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@ -80,12 +80,6 @@ static mega_uart_t *dev[] = {
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*/
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static uart_isr_ctx_t isr_ctx[UART_NUMOF];
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/**
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* @brief Allocate variable to hold transmission status, set when there
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* is data in UDRn or in the Transmit Shift Register
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*/
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static volatile uint8_t _tx_pending = 0;
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static void _update_brr(uart_t uart, uint16_t brr, bool double_speed)
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{
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dev[uart]->BRR = brr;
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@ -126,8 +120,8 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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return UART_NODEV;
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}
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uint16_t count = 0xffff;
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while (_tx_pending && count--) {}
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uint16_t count = UINT16_MAX;
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while (atmega_is_uart_tx_pending() && count--) {}
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/* register interrupt context */
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isr_ctx[uart].rx_cb = rx_cb;
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@ -178,8 +172,9 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
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#endif
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/* start of TX won't finish until no data in UDRn and transmit shift
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register is empty */
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_tx_pending |= (1 << uart);
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unsigned long state = irq_disable();
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atmega_state |= ATMEGA_STATE_FLAG_UART_TX(uart);
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irq_restore(state);
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dev[uart]->DR = data[i];
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}
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}
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@ -211,7 +206,7 @@ static inline void _tx_isr_handler(int num)
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/* entire frame in the Transmit Shift Register has been shifted out and
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there are no new data currently present in the transmit buffer */
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_tx_pending &= ~(1 << num);
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atmega_state &= ~ATMEGA_STATE_FLAG_UART_TX(num);
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atmega_exit_isr();
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}
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@ -247,7 +247,9 @@ void thread_yield_higher(void)
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void atmega_exit_isr(void)
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{
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atmega_in_isr = 0;
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atmega_state &= ~ATMEGA_STATE_FLAG_ISR;
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/* Force access to atmega_state to take place */
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__asm__ volatile ("" : : : "memory");
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if (sched_context_switch_request) {
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atmega_context_save();
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sched_run();
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