cpu/stm32l4: implement MCO configuration

cpu/stm32/stmclk/stmclk_l4wb.c

@@ -26,6 +26,7 @@
 #include "cpu.h"
 #include "stmclk.h"
 #include "periph_conf.h"
+#include "periph/gpio.h"
 
 /* map CMSIS defines not present in stm32wb55xx.h */
 #if defined(CPU_FAM_STM32WB)
@@ -106,6 +107,7 @@
 #endif
 /** @} */
 
+/* Define MSI range bit fields */
 #if CONFIG_CLOCK_MSI == KHZ(100)
 #define CLOCK_MSIRANGE              (RCC_CR_MSIRANGE_0)
 #elif CONFIG_CLOCK_MSI == KHZ(200)
@@ -134,6 +136,142 @@
 #error "Invalid MSI clock"
 #endif
 
+/* Configure MCO */
+#ifndef CONFIG_CLOCK_ENABLE_MCO
+#define CONFIG_CLOCK_ENABLE_MCO     0   /* Don't enable MCO by default */
+#endif
+
+/* Configure the MCO clock source: options are PLLCLK (default), HSE, HSI, LSE, LSI or SYSCLK*/
+#ifndef CONFIG_CLOCK_MCO_USE_PLLCLK
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+    IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || \
+    IS_ACTIVE(CONFIG_CLOCK_MCO_USE_MSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK)
+#define CONFIG_CLOCK_MCO_USE_PLLCLK 0
+#else
+#define CONFIG_CLOCK_MCO_USE_PLLCLK 1   /* Use PLLCLK by default */
+#endif
+#endif /* CONFIG_CLOCK_MCO_USE_PLLCLK */
+
+#ifndef CONFIG_CLOCK_MCO_USE_HSE
+#define CONFIG_CLOCK_MCO_USE_HSE    0
+#endif /* CONFIG_CLOCK_MCO_USE_HSE */
+
+#ifndef CONFIG_CLOCK_MCO_USE_HSI
+#define CONFIG_CLOCK_MCO_USE_HSI    0
+#endif /* CONFIG_CLOCK_MCO_USE_HSI */
+
+#ifndef CONFIG_CLOCK_MCO_USE_LSE
+#define CONFIG_CLOCK_MCO_USE_LSE    0
+#endif /* CONFIG_CLOCK_MCO_USE_LSE */
+
+#ifndef CONFIG_CLOCK_MCO_USE_LSI
+#define CONFIG_CLOCK_MCO_USE_LSI    0
+#endif /* CONFIG_CLOCK_MCO_USE_LSI */
+
+#ifndef CONFIG_CLOCK_MCO_USE_MSI
+#define CONFIG_CLOCK_MCO_USE_MSI    0
+#endif /* CONFIG_CLOCK_MCO_USE_MSI */
+
+#ifndef CONFIG_CLOCK_MCO_USE_SYSCLK
+#define CONFIG_CLOCK_MCO_USE_SYSCLK 0
+#endif /* CONFIG_CLOCK_MCO_USE_SYSCLK */
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_MSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use PLLCLK as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_MSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use HSE as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_MSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use HSI as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_MSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use LSE as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_MSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use LSI as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_MSI) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLL) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK))
+#error "Cannot use MSI as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK) && \
+    (IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI) || \
+     IS_ACTIVE(CONFIG_CLOCK_MCO_USE_MSI) || IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK))
+#error "Cannot use SYSCLK as MCO clock source with other clocks"
+#endif
+
+#if IS_ACTIVE(CONFIG_CLOCK_MCO_USE_SYSCLK)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_0)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_MSI)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_1)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_0)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_2)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_2 | RCC_CFGR_MCOSEL_0)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_2 | RCC_CFGR_MCOSEL_1)
+#elif IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE)
+#define CLOCK_MCO_SRC                           (RCC_CFGR_MCOSEL_2 | RCC_CFGR_MCOSEL_1 | RCC_CFGR_MCOSEL_0)
+#else
+#error "Invalid MCO clock source selection"
+#endif
+
+/* Configure the MCO prescaler: valid values are 1, 2, 4, 8, 16 */
+#ifndef CONFIG_CLOCK_MCO_PRE
+#define CONFIG_CLOCK_MCO_PRE                    (1)
+#endif
+
+#ifdef CPU_FAM_STM32WB
+/* Define bitfields for MCO prescaler for compatibility with L4*/
+#define RCC_CFGR_MCOPRE_DIV1                    (0)
+#define RCC_CFGR_MCOPRE_DIV2                    (RCC_CFGR_MCOPRE_0)
+#define RCC_CFGR_MCOPRE_DIV4                    (RCC_CFGR_MCOPRE_1)
+#define RCC_CFGR_MCOPRE_DIV8                    (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)
+#define RCC_CFGR_MCOPRE_DIV16                   (RCC_CFGR_MCOPRE_2)
+#endif /* CPU_FAM_STM32WB */
+
+#if CONFIG_CLOCK_MCO_PRE == 1
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_DIV1)
+#elif CONFIG_CLOCK_MCO_PRE == 2
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_DIV2)
+#elif CONFIG_CLOCK_MCO_PRE == 4
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_DIV4)
+#elif CONFIG_CLOCK_MCO_PRE == 8
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_DIV8)
+#elif CONFIG_CLOCK_MCO_PRE == 16
+#define CLOCK_MCO_PRE                           (RCC_CFGR_MCOPRE_DIV16)
+#else
+#error "Invalid MCO prescaler"
+#endif
+
+/* Configure main and peripheral bus clock prescalers */
 #if defined(CPU_FAM_STM32WB)
 #define CLOCK_AHB_DIV               (0)
 
@@ -221,9 +359,11 @@
 /* Check if PLL is required
   - When used as system clock
   - When PLLQ is used as 48MHz clock source
+  - When PLLCLK is used as MCO clock source
 */
 #if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || \
-    (IS_ACTIVE(CLOCK_ENABLE_48MHZ) && IS_ACTIVE(CLOCK48MHZ_USE_PLLQ))
+    (IS_ACTIVE(CLOCK_ENABLE_48MHZ) && IS_ACTIVE(CLOCK48MHZ_USE_PLLQ)) || \
+    (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK))
 #define CLOCK_ENABLE_PLL            1
 #else
 #define CLOCK_ENABLE_PLL            0
@@ -234,7 +374,8 @@
   - When used as PLL input clock
 */
 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
-    (IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE))
+    (IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE)) || \
+    (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSE))
 #define CLOCK_ENABLE_HSE            1
 #else
 #define CLOCK_ENABLE_HSE            0
@@ -250,12 +391,27 @@
   - When used as PLL input clock
 */
 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
-    (IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI))
+    (IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI)) || \
+    (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_HSI))
 #define CLOCK_ENABLE_HSI            1
 #else
 #define CLOCK_ENABLE_HSI            0
 #endif
 
+/* Check whether LSE must be enabled */
+#if IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSE)
+#define CLOCK_ENABLE_LSE            1
+#else
+#define CLOCK_ENABLE_LSE            0
+#endif
+
+/* Check whether LSI must be enabled */
+#if IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_LSI)
+#define CLOCK_ENABLE_LSI            1
+#else
+#define CLOCK_ENABLE_LSI            0
+#endif
+
 /* Check if MSI is required
   - When used as system clock
   - When used as PLL input clock
@@ -263,6 +419,7 @@
 */
 #if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
     (IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)) || \
+    (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_MSI)) || \
     (IS_ACTIVE(CLOCK_ENABLE_48MHZ) && IS_ACTIVE(CLOCK48MHZ_USE_MSI))
 #define CLOCK_ENABLE_MSI            1
 #else
@@ -351,8 +508,10 @@ void stmclk_init_sysclk(void)
 
         /* now we can safely configure and start the PLL */
         RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | PLL_Q);
-        if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
+        if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) ||
-            /* Enable PLLCLK if PLL is used as system clock */
+            (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO) && IS_ACTIVE(CONFIG_CLOCK_MCO_USE_PLLCLK))) {
+            /* Enable PLLCLK if PLL is used as system clock or when PLLCLK is
+               used MCO clock source */
             RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN;
         }
 
@@ -425,5 +584,42 @@ void stmclk_init_sysclk(void)
         }
     }
 
+    /* Enable the LSE if required for MCO.
+     * If available on the board, LSE might also be initialized for RTT/RTC
+     * peripherals. For the monent, this initialization is done in the
+     * corresponding peripheral drivers. */
+    if (IS_ACTIVE(CLOCK_ENABLE_LSE)) {
+        stmclk_dbp_unlock();
+        RCC->BDCR |= RCC_BDCR_LSEON;
+        while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {}
+        stmclk_dbp_lock();
+    }
+
+    /* Enable the LSI if required for MCO
+     * If no LSE is available on the board, LSI might also be initialized for
+     * RTT/RTC peripherals. For the monent, this initialization is done in the
+     * corresponding peripheral drivers. */
+    if (IS_ACTIVE(CLOCK_ENABLE_LSI)) {
+#if defined(CPU_FAM_STM32WB)
+        RCC->CSR |= RCC_CSR_LSI1ON;
+        while (!(RCC->CSR & RCC_CSR_LSI1RDY)) {}
+#else
+        RCC->CSR |= RCC_CSR_LSION;
+        while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
+#endif
+    }
+
+    /* Configure MCO */
+    if (IS_ACTIVE(CONFIG_CLOCK_ENABLE_MCO)) {
+        /* As stated in the manual, it is highly recommended to change the MCO
+           prescaler before enabling the MCO */
+        RCC->CFGR |= CLOCK_MCO_PRE;
+        RCC->CFGR |= CLOCK_MCO_SRC;
+
+        /* Configure MCO pin (PA8 with AF0) */
+        gpio_init(GPIO_PIN(PORT_A, 8), GPIO_OUT);
+        gpio_init_af(GPIO_PIN(PORT_A, 8), GPIO_AF0);
+    }
+
     irq_restore(is);
 }