From 4a5d9a30b12e60ad6548f82e8cc0107e2023a672 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 28 Aug 2020 13:59:07 +0200 Subject: [PATCH 1/8] boards/stm32l0*: rename shared clock config header --- boards/b-l072z-lrwan1/include/periph_conf.h | 2 +- .../l0/{cfg_clock_32_16_1.h => cfg_clock_default.h} | 12 +++++++----- boards/i-nucleo-lrwan1/include/periph_conf.h | 2 +- boards/lsn50/include/periph_conf.h | 2 +- boards/nucleo-l031k6/include/periph_conf.h | 2 +- boards/nucleo-l053r8/include/periph_conf.h | 2 +- boards/nucleo-l073rz/include/periph_conf.h | 2 +- boards/stm32l0538-disco/include/periph_conf.h | 1 + 8 files changed, 14 insertions(+), 11 deletions(-) rename boards/common/stm32/include/l0/{cfg_clock_32_16_1.h => cfg_clock_default.h} (87%) diff --git a/boards/b-l072z-lrwan1/include/periph_conf.h b/boards/b-l072z-lrwan1/include/periph_conf.h index b596a664f6..be416da02a 100644 --- a/boards/b-l072z-lrwan1/include/periph_conf.h +++ b/boards/b-l072z-lrwan1/include/periph_conf.h @@ -20,7 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "l0/cfg_clock_32_16_1.h" +#include "l0/cfg_clock_default.h" #include "cfg_rtt_default.h" #include "cfg_i2c1_pb8_pb9.h" #include "cfg_timer_tim2.h" diff --git a/boards/common/stm32/include/l0/cfg_clock_32_16_1.h b/boards/common/stm32/include/l0/cfg_clock_default.h similarity index 87% rename from boards/common/stm32/include/l0/cfg_clock_32_16_1.h rename to boards/common/stm32/include/l0/cfg_clock_default.h index 4274804229..76acb59e89 100644 --- a/boards/common/stm32/include/l0/cfg_clock_32_16_1.h +++ b/boards/common/stm32/include/l0/cfg_clock_default.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2019 Inria + * Copyright (C) 2018-2020 Inria * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level @@ -11,13 +11,13 @@ * @{ * * @file - * @brief Configure STM32L0 clock using 32MHz core clock and LSE (32.768kHz) + * @brief Default STM32L0 clock configuration * * @author Alexandre Abadie */ -#ifndef L0_CFG_CLOCK_32_16_1_H -#define L0_CFG_CLOCK_32_16_1_H +#ifndef L0_CFG_CLOCK_DEFAULT_H +#define L0_CFG_CLOCK_DEFAULT_H #include "periph_cpu.h" @@ -31,7 +31,9 @@ extern "C" { */ #define CLOCK_HSI (16000000U) /* internal oscillator */ #define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ +#ifndef CLOCK_LSE #define CLOCK_LSE (1) /* enable low speed external oscillator */ +#endif /* configuration of PLL prescaler and multiply values */ /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ @@ -54,5 +56,5 @@ extern "C" { } #endif -#endif /* L0_CFG_CLOCK_32_16_1_H */ +#endif /* L0_CFG_CLOCK_DEFAULT_H */ /** @} */ diff --git a/boards/i-nucleo-lrwan1/include/periph_conf.h b/boards/i-nucleo-lrwan1/include/periph_conf.h index 4761e37000..71f71f9816 100644 --- a/boards/i-nucleo-lrwan1/include/periph_conf.h +++ b/boards/i-nucleo-lrwan1/include/periph_conf.h @@ -20,7 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "l0/cfg_clock_32_16_1.h" +#include "l0/cfg_clock_default.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/lsn50/include/periph_conf.h b/boards/lsn50/include/periph_conf.h index 8e3c2c09c2..ede45528d2 100644 --- a/boards/lsn50/include/periph_conf.h +++ b/boards/lsn50/include/periph_conf.h @@ -20,7 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "l0/cfg_clock_32_16_1.h" +#include "l0/cfg_clock_default.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/nucleo-l031k6/include/periph_conf.h b/boards/nucleo-l031k6/include/periph_conf.h index eb8e02035a..dd1b40ce62 100644 --- a/boards/nucleo-l031k6/include/periph_conf.h +++ b/boards/nucleo-l031k6/include/periph_conf.h @@ -22,7 +22,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "l0/cfg_clock_32_16_1.h" +#include "l0/cfg_clock_default.h" #include "cfg_i2c1_pb6_pb7.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/nucleo-l053r8/include/periph_conf.h b/boards/nucleo-l053r8/include/periph_conf.h index bdbe21c66b..5e7491c51a 100644 --- a/boards/nucleo-l053r8/include/periph_conf.h +++ b/boards/nucleo-l053r8/include/periph_conf.h @@ -22,7 +22,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "l0/cfg_clock_32_16_1.h" +#include "l0/cfg_clock_default.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/nucleo-l073rz/include/periph_conf.h b/boards/nucleo-l073rz/include/periph_conf.h index 6bcb2d79a2..358e4d8ca7 100644 --- a/boards/nucleo-l073rz/include/periph_conf.h +++ b/boards/nucleo-l073rz/include/periph_conf.h @@ -22,7 +22,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "l0/cfg_clock_32_16_1.h" +#include "l0/cfg_clock_default.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/stm32l0538-disco/include/periph_conf.h b/boards/stm32l0538-disco/include/periph_conf.h index d74c1ee041..f8563ec440 100644 --- a/boards/stm32l0538-disco/include/periph_conf.h +++ b/boards/stm32l0538-disco/include/periph_conf.h @@ -20,6 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l0/cfg_clock_default.h" #ifdef __cplusplus extern "C" { From 23117a844e95cece3738cc6f60abbf2ecfe279f6 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 28 Aug 2020 18:35:52 +0200 Subject: [PATCH 2/8] boards: cpu: stm32l0: rework clock configuration --- .../stm32/include/l0/cfg_clock_default.h | 131 +++++++++-- .../stm32/include/l1/cfg_clock_default.h | 129 +++++++++-- cpu/stm32/stmclk/stmclk_l0l1.c | 219 +++++++++++++----- 3 files changed, 379 insertions(+), 100 deletions(-) diff --git a/boards/common/stm32/include/l0/cfg_clock_default.h b/boards/common/stm32/include/l0/cfg_clock_default.h index 76acb59e89..50eb7a8ea1 100644 --- a/boards/common/stm32/include/l0/cfg_clock_default.h +++ b/boards/common/stm32/include/l0/cfg_clock_default.h @@ -29,27 +29,122 @@ extern "C" { * @name Clock system configuration * @{ */ -#define CLOCK_HSI (16000000U) /* internal oscillator */ -#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ -#ifndef CLOCK_LSE -#define CLOCK_LSE (1) /* enable low speed external oscillator */ +/* Select the desired system clock source between PLL, HSE or HSI */ +#ifndef CONFIG_USE_CLOCK_PLL +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \ + IS_ACTIVE(CONFIG_USE_CLOCK_MSI) +#define CONFIG_USE_CLOCK_PLL (0) +#else +#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */ +#endif +#endif /* CONFIG_USE_CLOCK_PLL */ + +#ifndef CONFIG_USE_CLOCK_MSI +#define CONFIG_USE_CLOCK_MSI (0) +#endif /* CONFIG_USE_CLOCK_MSI */ + +#ifndef CONFIG_USE_CLOCK_HSE +#define CONFIG_USE_CLOCK_HSE (0) +#endif /* CONFIG_USE_CLOCK_HSE */ + +#ifndef CONFIG_USE_CLOCK_HSI +#define CONFIG_USE_CLOCK_HSI (0) +#endif /* CONFIG_USE_CLOCK_HSI */ + +#if CONFIG_USE_CLOCK_PLL && \ + (CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) +#error "Cannot use PLL as clock source with other clock configurations" #endif -/* configuration of PLL prescaler and multiply values */ -/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ -#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 -#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 -/* configuration of peripheral bus clock prescalers */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ -/* configuration of flash access cycles */ -#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY +#if CONFIG_USE_CLOCK_MSI && \ + (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) +#error "Cannot use MSI as clock source with other clock configurations" +#endif -/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) +#if CONFIG_USE_CLOCK_HSE && \ + (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSI) +#error "Cannot use HSE as clock source with other clock configurations" +#endif + +#if CONFIG_USE_CLOCK_HSI && \ + (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE) +#error "Cannot use HSI as clock source with other clock configurations" +#endif + +#ifndef CONFIG_BOARD_HAS_HSE +#define CONFIG_BOARD_HAS_HSE (0) +#endif + +#ifndef CLOCK_HSE +#define CLOCK_HSE MHZ(24) +#endif +#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24)) +#error "HSE clock frequency must be between 1MHz and 24MHz" +#endif + +#ifndef CONFIG_CLOCK_HSI_USE_DIV4 +#define CONFIG_CLOCK_HSI_USE_DIV4 (0) +#endif + +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (1) +#endif +#if CONFIG_BOARD_HAS_LSE +#define CLOCK_LSE (1) +#else +#define CLOCK_LSE (0) +#endif + +#define CLOCK_HSI MHZ(16) + +#if CONFIG_USE_CLOCK_HSI +#define CLOCK_CORECLOCK (CLOCK_HSI) + +#elif CONFIG_USE_CLOCK_HSE +#if CONFIG_BOARD_HAS_HSE == 0 +#error "The board doesn't provide an HSE oscillator" +#endif +#define CLOCK_CORECLOCK (CLOCK_HSE) + +#elif CONFIG_USE_CLOCK_MSI +#ifndef CONFIG_CLOCK_MSI +#define CONFIG_CLOCK_MSI KHZ(4194) +#endif +#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) + +#elif CONFIG_USE_CLOCK_PLL +/* The following parameters configure a 64MHz system clock with HSI as input clock */ +#ifndef CONFIG_CLOCK_PLL_DIV +#define CONFIG_CLOCK_PLL_DIV (2) +#endif +#ifndef CONFIG_CLOCK_PLL_MUL +#define CONFIG_CLOCK_PLL_MUL (4) +#endif +#if CONFIG_BOARD_HAS_HSE +#if CLOCK_HSE < MHZ(2) +#error "HSE must be greater than 2MHz when used as PLL input clock" +#endif +#define CLOCK_PLL_SRC (CLOCK_HSE) +#else /* CLOCK_HSI */ +#define CLOCK_PLL_SRC (CLOCK_HSI) +#endif +#endif /* CONFIG_BOARD_HAS_HSE */ +#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL) +#if CLOCK_CORECLOCK > MHZ(32) +#error "SYSCLK cannot exceed 32MHz" +#endif +#endif /* CONFIG_USE_CLOCK_PLL */ + +#define CLOCK_AHB CLOCK_CORECLOCK /* max: 32MHz */ + +#ifndef CONFIG_CLOCK_APB1_DIV +#define CONFIG_CLOCK_APB1_DIV (1) +#endif +#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 32MHz */ +#ifndef CONFIG_CLOCK_APB2_DIV +#define CONFIG_CLOCK_APB2_DIV (1) +#endif +#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */ /** @} */ #ifdef __cplusplus diff --git a/boards/common/stm32/include/l1/cfg_clock_default.h b/boards/common/stm32/include/l1/cfg_clock_default.h index 5623deb3ed..9da55a11e1 100644 --- a/boards/common/stm32/include/l1/cfg_clock_default.h +++ b/boards/common/stm32/include/l1/cfg_clock_default.h @@ -29,28 +29,121 @@ extern "C" { * @name Clock system configuration * @{ */ -#define CLOCK_HSI (16000000U) /* internal oscillator */ -#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ +/* Select the desired system clock source between PLL, HSE or HSI */ +#ifndef CONFIG_USE_CLOCK_PLL +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \ + IS_ACTIVE(CONFIG_USE_CLOCK_MSI) +#define CONFIG_USE_CLOCK_PLL (0) +#else +#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */ +#endif +#endif /* CONFIG_USE_CLOCK_PLL */ -#ifndef CLOCK_LSE -#define CLOCK_LSE (0) /* disable low speed external oscillator */ +#ifndef CONFIG_USE_CLOCK_MSI +#define CONFIG_USE_CLOCK_MSI (0) +#endif /* CONFIG_USE_CLOCK_MSI */ + +#ifndef CONFIG_USE_CLOCK_HSE +#define CONFIG_USE_CLOCK_HSE (0) +#endif /* CONFIG_USE_CLOCK_HSE */ + +#ifndef CONFIG_USE_CLOCK_HSI +#define CONFIG_USE_CLOCK_HSI (0) +#endif /* CONFIG_USE_CLOCK_HSI */ + +#if CONFIG_USE_CLOCK_PLL && \ + (CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) +#error "Cannot use PLL as clock source with other clock configurations" #endif -/* configuration of PLL prescaler and multiply values */ -/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ -#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 -#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 -/* configuration of peripheral bus clock prescalers */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ -/* configuration of flash access cycles */ -#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY +#if CONFIG_USE_CLOCK_MSI && \ + (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) +#error "Cannot use MSI as clock source with other clock configurations" +#endif -/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) +#if CONFIG_USE_CLOCK_HSE && \ + (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSI) +#error "Cannot use HSE as clock source with other clock configurations" +#endif + +#if CONFIG_USE_CLOCK_HSI && \ + (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE) +#error "Cannot use HSI as clock source with other clock configurations" +#endif + +#ifndef CONFIG_BOARD_HAS_HSE +#define CONFIG_BOARD_HAS_HSE (0) +#endif + +#ifndef CLOCK_HSE +#define CLOCK_HSE MHZ(24) +#endif +#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24)) +#error "HSE clock frequency must be between 1MHz and 24MHz" +#endif + +#ifndef CONFIG_CLOCK_HSI_USE_DIV4 +#define CONFIG_CLOCK_HSI_USE_DIV4 (0) +#endif + +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (0) +#endif +#if CONFIG_BOARD_HAS_LSE +#define CLOCK_LSE (1) +#else +#define CLOCK_LSE (0) +#endif + +#define CLOCK_HSI MHZ(16) + +#if CONFIG_USE_CLOCK_HSI +#define CLOCK_CORECLOCK (CLOCK_HSI) + +#elif CONFIG_USE_CLOCK_HSE +#if CONFIG_BOARD_HAS_HSE == 0 +#error "The board doesn't provide an HSE oscillator" +#endif +#define CLOCK_CORECLOCK (CLOCK_HSE) + +#elif CONFIG_USE_CLOCK_MSI +#ifndef CONFIG_CLOCK_MSI +#define CONFIG_CLOCK_MSI KHZ(4194) +#endif +#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) + +#elif CONFIG_USE_CLOCK_PLL +/* The following parameters configure a 64MHz system clock with HSI as input clock */ +#ifndef CONFIG_CLOCK_PLL_DIV +#define CONFIG_CLOCK_PLL_DIV (2) +#endif +#ifndef CONFIG_CLOCK_PLL_MUL +#define CONFIG_CLOCK_PLL_MUL (4) +#endif +#if CONFIG_BOARD_HAS_HSE +#if CLOCK_HSE < MHZ(2) +#error "HSE must be greater than 2MHz when used as PLL input clock" +#endif +#define CLOCK_PLL_SRC (CLOCK_HSE) +#else /* CLOCK_HSI */ +#define CLOCK_PLL_SRC (CLOCK_HSI) +#endif /* CONFIG_BOARD_HAS_HSE */ +#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL) +#if CLOCK_CORECLOCK > MHZ(32) +#error "SYSCLK cannot exceed 32MHz" +#endif +#endif /* CONFIG_USE_CLOCK_PLL */ + +#define CLOCK_AHB CLOCK_CORECLOCK /* max: 32MHz */ + +#ifndef CONFIG_CLOCK_APB1_DIV +#define CONFIG_CLOCK_APB1_DIV (1) +#endif +#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 32MHz */ +#ifndef CONFIG_CLOCK_APB2_DIV +#define CONFIG_CLOCK_APB2_DIV (1) +#endif +#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */ /** @} */ #ifdef __cplusplus diff --git a/cpu/stm32/stmclk/stmclk_l0l1.c b/cpu/stm32/stmclk/stmclk_l0l1.c index c353237111..876631d128 100644 --- a/cpu/stm32/stmclk/stmclk_l0l1.c +++ b/cpu/stm32/stmclk/stmclk_l0l1.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2014 Freie Universität Berlin - * 2017 Inria + * 2017-2020 Inria * 2018 Kaspar Schleiser * * This file is subject to the terms and conditions of the GNU Lesser @@ -22,67 +22,127 @@ */ #include "cpu.h" -#include "board.h" +#include "stmclk.h" #include "periph_conf.h" -#include "periph/init.h" + +#if defined(CPU_FAM_STM32L1) +#define REG_CIR (RCC->CIR) +#else /* CPU_FAM_STM32L0 */ +#define REG_CIR (RCC->CICR) +#endif + +/* configuration of flash access cycles */ +#define CLOCK_FLASH_LATENCY (FLASH_ACR_LATENCY) + +/* Configure the prescalers */ +#define CLOCK_AHB_DIV (RCC_CFGR_HPRE_DIV1) /* HCLK = SYSCLK */ + +#if CONFIG_CLOCK_APB1_DIV == 1 +#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1) +#elif CONFIG_CLOCK_APB1_DIV == 2 +#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV2) +#elif CONFIG_CLOCK_APB1_DIV == 4 +#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV4) +#elif CONFIG_CLOCK_APB1_DIV == 8 +#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV8) +#elif CONFIG_CLOCK_APB1_DIV == 16 +#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV16) +#endif + +#if CONFIG_CLOCK_APB2_DIV == 1 +#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1) +#elif CONFIG_CLOCK_APB2_DIV == 2 +#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV2) +#elif CONFIG_CLOCK_APB2_DIV == 4 +#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV4) +#elif CONFIG_CLOCK_APB2_DIV == 8 +#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV8) +#elif CONFIG_CLOCK_APB2_DIV == 16 +#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV16) +#endif /* Check the source to be used for the PLL */ -#if defined(CLOCK_HSI) && defined(CLOCK_HSE) -#error "Only provide one of two CLOCK_HSI/CLOCK_HSE" -#elif CLOCK_HSI -#define CLOCK_CR_SOURCE RCC_CR_HSION -#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY -#define CLOCK_PLL_SOURCE RCC_CFGR_PLLSRC_HSI -#elif CLOCK_HSE -#define CLOCK_CR_SOURCE RCC_CR_HSEON -#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY -#define CLOCK_PLL_SOURCE RCC_CFGR_PLLSRC_HSE +#if CONFIG_BOARD_HAS_HSE +#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSE) +#else /* Use HSI as PLL input */ +#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI) +#endif + +#if CONFIG_CLOCK_PLL_DIV == 2 +#define CLOCK_PLL_DIV (RCC_CFGR_PLLDIV2) +#elif CONFIG_CLOCK_PLL_DIV == 3 +#define CLOCK_PLL_DIV (RCC_CFGR_PLLDIV3) +#elif CONFIG_CLOCK_PLL_DIV == 4 +#define CLOCK_PLL_DIV (RCC_CFGR_PLLDIV4) #else -#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h" +#error "Invalid PLL DIV value, only 2, 3, and 4 values are allowed." +#endif + +#if CONFIG_CLOCK_PLL_MUL == 3 +#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL3) +#elif CONFIG_CLOCK_PLL_MUL == 4 +#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL4) +#elif CONFIG_CLOCK_PLL_MUL == 6 +#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL6) +#elif CONFIG_CLOCK_PLL_MUL == 8 +#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL8) +#elif CONFIG_CLOCK_PLL_MUL == 12 +#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL12) +#elif CONFIG_CLOCK_PLL_MUL == 16 +#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL16) +#elif CONFIG_CLOCK_PLL_MUL == 24 +#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL24) +#elif CONFIG_CLOCK_PLL_MUL == 32 +#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL32) +#elif CONFIG_CLOCK_PLL_MUL == 48 +#define CLOCK_PLL_MUL (RCC_CFGR_PLLMUL48) +#else +#error "Invalid PLL MUL value, only 3, 4, 6, 8, 12, 16, 24, 32 and 48 values are allowed." +#endif + +#if CONFIG_CLOCK_MSI == 65536UL +#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_0) +#elif CONFIG_CLOCK_MSI == 131072UL +#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_1) +#elif CONFIG_CLOCK_MSI == 262144UL +#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_2) +#elif CONFIG_CLOCK_MSI == 524288UL +#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_3) +#elif CONFIG_CLOCK_MSI == KHZ(1048) +#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_4) +#elif CONFIG_CLOCK_MSI == KHZ(2097) +#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_5) +#elif CONFIG_CLOCK_MSI == KHZ(4194) +#define CLOCK_MSIRANGE (RCC_ICSCR_MSIRANGE_6) +#else +#error "Invalid MSI clock value" #endif /** * @brief Configure the controllers clock system * - * The clock initialization make the following assumptions: - * - the external HSE clock from an external oscillator is used as base clock - * - the internal PLL circuit is used for clock refinement - * - * Use the following formulas to calculate the needed values: - * - * SYSCLK = ((HSE_VALUE / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_P - * USB, SDIO and RNG Clock = ((HSE_VALUE / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_Q - * - * The actual used values are specified in the board's `periph_conf.h` file. - * - * NOTE: currently there is not timeout for initialization of PLL and other locks + * NOTE: currently there is no timeout for initialization of PLL and other locks * -> when wrong values are chosen, the initialization could stall */ void stmclk_init_sysclk(void) { - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - /* Reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE bits */ - RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL); - /* Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON); + /* disable any interrupts. Global interrupts could be enabled if this is + * called from some kind of bootloader... */ + unsigned is = irq_disable(); /* Disable all interrupts */ + REG_CIR = 0x0; -#if defined(CPU_FAM_STM32L0) - RCC->CICR = 0x0; -#elif defined(CPU_FAM_STM32L1) - RCC->CIR = 0x0; -#else -#error unexpected MCU -#endif + /* enable HSI clock for the duration of initialization */ + stmclk_enable_hsi(); + + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Reset MSION, HSEON, CSSON and PLLON bits */ + RCC->CR &= ~(RCC_CR_MSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON); + + /* use HSI as system clock while we do any further configuration and + * configure the AHB and APB clock dividers as configured by the board */ + RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV); - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */ - /* Enable high speed clock source */ - RCC->CR |= CLOCK_CR_SOURCE; - /* Wait till the high speed clock source is ready - * NOTE: the MCU will stay here forever if you use an external clock source and it's not connected */ - while (!(RCC->CR & CLOCK_CR_SOURCE_RDY)) {} #if defined(CPU_FAM_STM32L1) FLASH->ACR |= FLASH_ACR_ACC64; #endif @@ -94,22 +154,53 @@ void stmclk_init_sysclk(void) PWR->CR = PWR_CR_VOS_0; /* Wait Until the Voltage Regulator is ready */ while((PWR->CSR & PWR_CSR_VOSF) != 0) {} - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV; - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV; - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV; - /* PLL configuration: PLLCLK = CLOCK_SOURCE / PLL_DIV * PLL_MUL */ - RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL)); - RCC->CFGR |= (uint32_t)(CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | CLOCK_PLL_MUL); - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - /* Wait till PLL is ready */ - while ((RCC->CR & RCC_CR_PLLRDY) == 0) {} - /* Select PLL as system clock source */ - RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} + + if (CONFIG_USE_CLOCK_HSE) { + /* Enable the HSE clock now */ + RCC->CR |= (RCC_CR_HSEON); + while (!(RCC->CR & RCC_CR_HSERDY)) {} + + /* Select HSE as system clock and configure the different prescalers */ + RCC->CFGR &= ~(RCC_CFGR_SW); + RCC->CFGR |= RCC_CFGR_SW_HSE; + } + else if (CONFIG_USE_CLOCK_MSI) { + /* Configure MSI range and enable it */ + RCC->ICSCR |= CLOCK_MSIRANGE; + RCC->CR |= (RCC_CR_MSION); + while (!(RCC->CR & RCC_CR_MSIRDY)) {} + + /* Select MSI as system clock and configure the different prescalers */ + RCC->CFGR &= ~(RCC_CFGR_SW); + RCC->CFGR |= RCC_CFGR_SW_MSI; + } + else if (CONFIG_USE_CLOCK_PLL) { + if (CONFIG_BOARD_HAS_HSE) { + /* if configured, we need to enable the HSE clock now */ + RCC->CR |= (RCC_CR_HSEON); + while (!(RCC->CR & RCC_CR_HSERDY)) {} + } + + /* Configure PLL clock source and configure the different prescalers */ + RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL); + RCC->CFGR |= (CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | CLOCK_PLL_MUL); + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + /* Wait till PLL is ready */ + while (!(RCC->CR & RCC_CR_PLLRDY)) {} + + /* Select PLL as system clock source */ + RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} + } + + if (!IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && IS_ACTIVE(CONFIG_BOARD_HAS_HSE))) { + /* Disable HSI only if not used */ + stmclk_disable_hsi(); + } + + irq_restore(is); } From 67a1c029b4c87cc08946e73ddf73e725507ef0bc Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 28 Aug 2020 20:17:47 +0200 Subject: [PATCH 3/8] boards/stm32l0: set LSE to 0 default, override in boards --- boards/b-l072z-lrwan1/include/periph_conf.h | 5 ++++ .../stm32/include/l0/cfg_clock_default.h | 2 +- boards/i-nucleo-lrwan1/include/periph_conf.h | 5 ++++ boards/lsn50/include/periph_conf.h | 5 ++++ boards/nucleo-l031k6/include/periph_conf.h | 5 ++++ boards/nucleo-l053r8/include/periph_conf.h | 5 ++++ boards/nucleo-l073rz/include/periph_conf.h | 5 ++++ boards/stm32l0538-disco/include/periph_conf.h | 25 ------------------- 8 files changed, 31 insertions(+), 26 deletions(-) diff --git a/boards/b-l072z-lrwan1/include/periph_conf.h b/boards/b-l072z-lrwan1/include/periph_conf.h index be416da02a..4d945c065b 100644 --- a/boards/b-l072z-lrwan1/include/periph_conf.h +++ b/boards/b-l072z-lrwan1/include/periph_conf.h @@ -19,6 +19,11 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* Add specific clock configuration (HSE, LSE) for this board here */ +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (1) +#endif + #include "periph_cpu.h" #include "l0/cfg_clock_default.h" #include "cfg_rtt_default.h" diff --git a/boards/common/stm32/include/l0/cfg_clock_default.h b/boards/common/stm32/include/l0/cfg_clock_default.h index 50eb7a8ea1..5c0a4808e9 100644 --- a/boards/common/stm32/include/l0/cfg_clock_default.h +++ b/boards/common/stm32/include/l0/cfg_clock_default.h @@ -87,7 +87,7 @@ extern "C" { #endif #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE (0) #endif #if CONFIG_BOARD_HAS_LSE #define CLOCK_LSE (1) diff --git a/boards/i-nucleo-lrwan1/include/periph_conf.h b/boards/i-nucleo-lrwan1/include/periph_conf.h index 71f71f9816..82f023c190 100644 --- a/boards/i-nucleo-lrwan1/include/periph_conf.h +++ b/boards/i-nucleo-lrwan1/include/periph_conf.h @@ -19,6 +19,11 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* Add specific clock configuration (HSE, LSE) for this board here */ +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (1) +#endif + #include "periph_cpu.h" #include "l0/cfg_clock_default.h" #include "cfg_rtt_default.h" diff --git a/boards/lsn50/include/periph_conf.h b/boards/lsn50/include/periph_conf.h index ede45528d2..5307c550c2 100644 --- a/boards/lsn50/include/periph_conf.h +++ b/boards/lsn50/include/periph_conf.h @@ -19,6 +19,11 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* Add specific clock configuration (HSE, LSE) for this board here */ +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (1) +#endif + #include "periph_cpu.h" #include "l0/cfg_clock_default.h" #include "cfg_rtt_default.h" diff --git a/boards/nucleo-l031k6/include/periph_conf.h b/boards/nucleo-l031k6/include/periph_conf.h index dd1b40ce62..3efc412ff5 100644 --- a/boards/nucleo-l031k6/include/periph_conf.h +++ b/boards/nucleo-l031k6/include/periph_conf.h @@ -21,6 +21,11 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* Add specific clock configuration (HSE, LSE) for this board here */ +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (1) +#endif + #include "periph_cpu.h" #include "l0/cfg_clock_default.h" #include "cfg_i2c1_pb6_pb7.h" diff --git a/boards/nucleo-l053r8/include/periph_conf.h b/boards/nucleo-l053r8/include/periph_conf.h index 5e7491c51a..3290d90c2d 100644 --- a/boards/nucleo-l053r8/include/periph_conf.h +++ b/boards/nucleo-l053r8/include/periph_conf.h @@ -21,6 +21,11 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* Add specific clock configuration (HSE, LSE) for this board here */ +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (1) +#endif + #include "periph_cpu.h" #include "l0/cfg_clock_default.h" #include "cfg_rtt_default.h" diff --git a/boards/nucleo-l073rz/include/periph_conf.h b/boards/nucleo-l073rz/include/periph_conf.h index 358e4d8ca7..15335b9db3 100644 --- a/boards/nucleo-l073rz/include/periph_conf.h +++ b/boards/nucleo-l073rz/include/periph_conf.h @@ -21,6 +21,11 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* Add specific clock configuration (HSE, LSE) for this board here */ +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (1) +#endif + #include "periph_cpu.h" #include "l0/cfg_clock_default.h" #include "cfg_rtt_default.h" diff --git a/boards/stm32l0538-disco/include/periph_conf.h b/boards/stm32l0538-disco/include/periph_conf.h index f8563ec440..1ee0648a40 100644 --- a/boards/stm32l0538-disco/include/periph_conf.h +++ b/boards/stm32l0538-disco/include/periph_conf.h @@ -26,31 +26,6 @@ extern "C" { #endif -/** - * @name Clock system configuration - * @{ - */ -#define CLOCK_HSI (16000000U) /* internal oscillator */ -#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ -#define CLOCK_LSE (0) /* enable low speed external oscillator */ - -/* configuration of PLL prescaler and multiply values */ -/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ -#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 -#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 -/* configuration of peripheral bus clock prescalers */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ -/* configuration of flash access cycles */ -#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY - -/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) -/** @} */ - /** * @name Timer configuration * @{ From 4bdb3db0f92f8880f6bdff7aca62345495ecf3c9 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 28 Aug 2020 22:09:10 +0200 Subject: [PATCH 4/8] boards/stm32l1: override default LSE in boards where needed --- boards/im880b/include/periph_conf.h | 4 ++-- boards/lobaro-lorabox/include/periph_conf.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/boards/im880b/include/periph_conf.h b/boards/im880b/include/periph_conf.h index 2c330bf3f4..9e9d07af9d 100644 --- a/boards/im880b/include/periph_conf.h +++ b/boards/im880b/include/periph_conf.h @@ -22,8 +22,8 @@ /* * This board provides an LSE, so enable it before including the default clock config */ -#ifndef CLOCK_LSE -#define CLOCK_LSE (1) +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (1) #endif #include "periph_cpu.h" diff --git a/boards/lobaro-lorabox/include/periph_conf.h b/boards/lobaro-lorabox/include/periph_conf.h index 64c8a47003..5176e8611e 100644 --- a/boards/lobaro-lorabox/include/periph_conf.h +++ b/boards/lobaro-lorabox/include/periph_conf.h @@ -27,8 +27,8 @@ /* * This board provides an LSE, so enable it before including the default clock config */ -#ifndef CLOCK_LSE -#define CLOCK_LSE (1) +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (1) #endif #include "periph_cpu.h" From 5e886a76c9a6d8138319aa25459d8fae6d3aad4f Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 28 Aug 2020 21:30:38 +0200 Subject: [PATCH 5/8] boards/stm32l0/l1: merge default clock configuration headers --- boards/b-l072z-lrwan1/include/periph_conf.h | 2 +- .../include/{l0 => l0l1}/cfg_clock_default.h | 27 ++- .../stm32/include/l1/cfg_clock_default.h | 154 ------------------ boards/i-nucleo-lrwan1/include/periph_conf.h | 2 +- boards/im880b/include/periph_conf.h | 2 +- boards/limifrog-v1/include/periph_conf.h | 2 +- boards/lobaro-lorabox/include/periph_conf.h | 2 +- boards/lsn50/include/periph_conf.h | 2 +- boards/nucleo-l031k6/include/periph_conf.h | 2 +- boards/nucleo-l053r8/include/periph_conf.h | 2 +- boards/nucleo-l073rz/include/periph_conf.h | 2 +- boards/nucleo-l152re/include/periph_conf.h | 2 +- boards/nz32-sc151/include/periph_conf.h | 2 +- boards/stm32l0538-disco/include/periph_conf.h | 2 +- 14 files changed, 30 insertions(+), 175 deletions(-) rename boards/common/stm32/include/{l0 => l0l1}/cfg_clock_default.h (86%) delete mode 100644 boards/common/stm32/include/l1/cfg_clock_default.h diff --git a/boards/b-l072z-lrwan1/include/periph_conf.h b/boards/b-l072z-lrwan1/include/periph_conf.h index 4d945c065b..d618bce0b4 100644 --- a/boards/b-l072z-lrwan1/include/periph_conf.h +++ b/boards/b-l072z-lrwan1/include/periph_conf.h @@ -25,7 +25,7 @@ #endif #include "periph_cpu.h" -#include "l0/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #include "cfg_rtt_default.h" #include "cfg_i2c1_pb8_pb9.h" #include "cfg_timer_tim2.h" diff --git a/boards/common/stm32/include/l0/cfg_clock_default.h b/boards/common/stm32/include/l0l1/cfg_clock_default.h similarity index 86% rename from boards/common/stm32/include/l0/cfg_clock_default.h rename to boards/common/stm32/include/l0l1/cfg_clock_default.h index 5c0a4808e9..a50a4e6858 100644 --- a/boards/common/stm32/include/l0/cfg_clock_default.h +++ b/boards/common/stm32/include/l0l1/cfg_clock_default.h @@ -11,13 +11,13 @@ * @{ * * @file - * @brief Default STM32L0 clock configuration + * @brief Default STM32L0/STM32L1 clock configuration * * @author Alexandre Abadie */ -#ifndef L0_CFG_CLOCK_DEFAULT_H -#define L0_CFG_CLOCK_DEFAULT_H +#ifndef L0L1_CFG_CLOCK_DEFAULT_H +#define L0L1_CFG_CLOCK_DEFAULT_H #include "periph_cpu.h" @@ -97,6 +97,10 @@ extern "C" { #define CLOCK_HSI MHZ(16) +#ifndef CONFIG_CLOCK_MSI +#define CONFIG_CLOCK_MSI KHZ(4194) +#endif + #if CONFIG_USE_CLOCK_HSI #define CLOCK_CORECLOCK (CLOCK_HSI) @@ -107,9 +111,6 @@ extern "C" { #define CLOCK_CORECLOCK (CLOCK_HSE) #elif CONFIG_USE_CLOCK_MSI -#ifndef CONFIG_CLOCK_MSI -#define CONFIG_CLOCK_MSI KHZ(4194) -#endif #define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) #elif CONFIG_USE_CLOCK_PLL @@ -127,8 +128,16 @@ extern "C" { #define CLOCK_PLL_SRC (CLOCK_HSE) #else /* CLOCK_HSI */ #define CLOCK_PLL_SRC (CLOCK_HSI) -#endif #endif /* CONFIG_BOARD_HAS_HSE */ +/* PLL configuration: make sure your values are legit! + * + * compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL) + * with: + * PLL_IN: input clock is HSE if available or HSI otherwise + * PLL_DIV : divider, allowed values: 2, 3, 4 + * PLL_MUL: multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48 + * CORECLOCK -> 48MHz MAX! + */ #define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL) #if CLOCK_CORECLOCK > MHZ(32) #error "SYSCLK cannot exceed 32MHz" @@ -144,12 +153,12 @@ extern "C" { #ifndef CONFIG_CLOCK_APB2_DIV #define CONFIG_CLOCK_APB2_DIV (1) #endif -#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */ +#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */ /** @} */ #ifdef __cplusplus } #endif -#endif /* L0_CFG_CLOCK_DEFAULT_H */ +#endif /* L0L1_CFG_CLOCK_DEFAULT_H */ /** @} */ diff --git a/boards/common/stm32/include/l1/cfg_clock_default.h b/boards/common/stm32/include/l1/cfg_clock_default.h deleted file mode 100644 index 9da55a11e1..0000000000 --- a/boards/common/stm32/include/l1/cfg_clock_default.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (C) 2020 Inria - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup boards_common_stm32 - * @{ - * - * @file - * @brief Default clock configuration for the STM32L1 - * - * @author Alexandre Abadie - */ - -#ifndef L1_CFG_CLOCK_DEFAULT_H -#define L1_CFG_CLOCK_DEFAULT_H - -#include "periph_cpu.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @name Clock system configuration - * @{ - */ -/* Select the desired system clock source between PLL, HSE or HSI */ -#ifndef CONFIG_USE_CLOCK_PLL -#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \ - IS_ACTIVE(CONFIG_USE_CLOCK_MSI) -#define CONFIG_USE_CLOCK_PLL (0) -#else -#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */ -#endif -#endif /* CONFIG_USE_CLOCK_PLL */ - -#ifndef CONFIG_USE_CLOCK_MSI -#define CONFIG_USE_CLOCK_MSI (0) -#endif /* CONFIG_USE_CLOCK_MSI */ - -#ifndef CONFIG_USE_CLOCK_HSE -#define CONFIG_USE_CLOCK_HSE (0) -#endif /* CONFIG_USE_CLOCK_HSE */ - -#ifndef CONFIG_USE_CLOCK_HSI -#define CONFIG_USE_CLOCK_HSI (0) -#endif /* CONFIG_USE_CLOCK_HSI */ - -#if CONFIG_USE_CLOCK_PLL && \ - (CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) -#error "Cannot use PLL as clock source with other clock configurations" -#endif - -#if CONFIG_USE_CLOCK_MSI && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) -#error "Cannot use MSI as clock source with other clock configurations" -#endif - -#if CONFIG_USE_CLOCK_HSE && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSI) -#error "Cannot use HSE as clock source with other clock configurations" -#endif - -#if CONFIG_USE_CLOCK_HSI && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE) -#error "Cannot use HSI as clock source with other clock configurations" -#endif - -#ifndef CONFIG_BOARD_HAS_HSE -#define CONFIG_BOARD_HAS_HSE (0) -#endif - -#ifndef CLOCK_HSE -#define CLOCK_HSE MHZ(24) -#endif -#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24)) -#error "HSE clock frequency must be between 1MHz and 24MHz" -#endif - -#ifndef CONFIG_CLOCK_HSI_USE_DIV4 -#define CONFIG_CLOCK_HSI_USE_DIV4 (0) -#endif - -#ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (0) -#endif -#if CONFIG_BOARD_HAS_LSE -#define CLOCK_LSE (1) -#else -#define CLOCK_LSE (0) -#endif - -#define CLOCK_HSI MHZ(16) - -#if CONFIG_USE_CLOCK_HSI -#define CLOCK_CORECLOCK (CLOCK_HSI) - -#elif CONFIG_USE_CLOCK_HSE -#if CONFIG_BOARD_HAS_HSE == 0 -#error "The board doesn't provide an HSE oscillator" -#endif -#define CLOCK_CORECLOCK (CLOCK_HSE) - -#elif CONFIG_USE_CLOCK_MSI -#ifndef CONFIG_CLOCK_MSI -#define CONFIG_CLOCK_MSI KHZ(4194) -#endif -#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) - -#elif CONFIG_USE_CLOCK_PLL -/* The following parameters configure a 64MHz system clock with HSI as input clock */ -#ifndef CONFIG_CLOCK_PLL_DIV -#define CONFIG_CLOCK_PLL_DIV (2) -#endif -#ifndef CONFIG_CLOCK_PLL_MUL -#define CONFIG_CLOCK_PLL_MUL (4) -#endif -#if CONFIG_BOARD_HAS_HSE -#if CLOCK_HSE < MHZ(2) -#error "HSE must be greater than 2MHz when used as PLL input clock" -#endif -#define CLOCK_PLL_SRC (CLOCK_HSE) -#else /* CLOCK_HSI */ -#define CLOCK_PLL_SRC (CLOCK_HSI) -#endif /* CONFIG_BOARD_HAS_HSE */ -#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL) -#if CLOCK_CORECLOCK > MHZ(32) -#error "SYSCLK cannot exceed 32MHz" -#endif -#endif /* CONFIG_USE_CLOCK_PLL */ - -#define CLOCK_AHB CLOCK_CORECLOCK /* max: 32MHz */ - -#ifndef CONFIG_CLOCK_APB1_DIV -#define CONFIG_CLOCK_APB1_DIV (1) -#endif -#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 32MHz */ -#ifndef CONFIG_CLOCK_APB2_DIV -#define CONFIG_CLOCK_APB2_DIV (1) -#endif -#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */ -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* L1_CFG_CLOCK_DEFAULT_H */ -/** @} */ diff --git a/boards/i-nucleo-lrwan1/include/periph_conf.h b/boards/i-nucleo-lrwan1/include/periph_conf.h index 82f023c190..6ee600b59d 100644 --- a/boards/i-nucleo-lrwan1/include/periph_conf.h +++ b/boards/i-nucleo-lrwan1/include/periph_conf.h @@ -25,7 +25,7 @@ #endif #include "periph_cpu.h" -#include "l0/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/im880b/include/periph_conf.h b/boards/im880b/include/periph_conf.h index 9e9d07af9d..28f3f41e7a 100644 --- a/boards/im880b/include/periph_conf.h +++ b/boards/im880b/include/periph_conf.h @@ -27,7 +27,7 @@ #endif #include "periph_cpu.h" -#include "l1/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #ifdef __cplusplus extern "C" { diff --git a/boards/limifrog-v1/include/periph_conf.h b/boards/limifrog-v1/include/periph_conf.h index 62d92ff8ca..e919e4efe6 100644 --- a/boards/limifrog-v1/include/periph_conf.h +++ b/boards/limifrog-v1/include/periph_conf.h @@ -20,7 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "l1/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #ifdef __cplusplus extern "C" { diff --git a/boards/lobaro-lorabox/include/periph_conf.h b/boards/lobaro-lorabox/include/periph_conf.h index 5176e8611e..8451e16f3c 100644 --- a/boards/lobaro-lorabox/include/periph_conf.h +++ b/boards/lobaro-lorabox/include/periph_conf.h @@ -32,7 +32,7 @@ #endif #include "periph_cpu.h" -#include "l1/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus diff --git a/boards/lsn50/include/periph_conf.h b/boards/lsn50/include/periph_conf.h index 5307c550c2..1ff10d0d1a 100644 --- a/boards/lsn50/include/periph_conf.h +++ b/boards/lsn50/include/periph_conf.h @@ -25,7 +25,7 @@ #endif #include "periph_cpu.h" -#include "l0/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/nucleo-l031k6/include/periph_conf.h b/boards/nucleo-l031k6/include/periph_conf.h index 3efc412ff5..f4d270da8a 100644 --- a/boards/nucleo-l031k6/include/periph_conf.h +++ b/boards/nucleo-l031k6/include/periph_conf.h @@ -27,7 +27,7 @@ #endif #include "periph_cpu.h" -#include "l0/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #include "cfg_i2c1_pb6_pb7.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/nucleo-l053r8/include/periph_conf.h b/boards/nucleo-l053r8/include/periph_conf.h index 3290d90c2d..753d3362fc 100644 --- a/boards/nucleo-l053r8/include/periph_conf.h +++ b/boards/nucleo-l053r8/include/periph_conf.h @@ -27,7 +27,7 @@ #endif #include "periph_cpu.h" -#include "l0/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/nucleo-l073rz/include/periph_conf.h b/boards/nucleo-l073rz/include/periph_conf.h index 15335b9db3..a24b128e2c 100644 --- a/boards/nucleo-l073rz/include/periph_conf.h +++ b/boards/nucleo-l073rz/include/periph_conf.h @@ -27,7 +27,7 @@ #endif #include "periph_cpu.h" -#include "l0/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/nucleo-l152re/include/periph_conf.h b/boards/nucleo-l152re/include/periph_conf.h index 1ef9319431..384c1ae989 100644 --- a/boards/nucleo-l152re/include/periph_conf.h +++ b/boards/nucleo-l152re/include/periph_conf.h @@ -21,7 +21,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "l1/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #include "cfg_timer_tim5.h" #ifdef __cplusplus diff --git a/boards/nz32-sc151/include/periph_conf.h b/boards/nz32-sc151/include/periph_conf.h index d26307a3a6..26cc201308 100644 --- a/boards/nz32-sc151/include/periph_conf.h +++ b/boards/nz32-sc151/include/periph_conf.h @@ -20,7 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "l1/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #include "cfg_timer_tim5.h" #ifdef __cplusplus diff --git a/boards/stm32l0538-disco/include/periph_conf.h b/boards/stm32l0538-disco/include/periph_conf.h index 1ee0648a40..0ca3b44a64 100644 --- a/boards/stm32l0538-disco/include/periph_conf.h +++ b/boards/stm32l0538-disco/include/periph_conf.h @@ -20,7 +20,7 @@ #define PERIPH_CONF_H #include "periph_cpu.h" -#include "l0/cfg_clock_default.h" +#include "l0l1/cfg_clock_default.h" #ifdef __cplusplus extern "C" { From 8ac1909ea3baf0cfffcec072d6ebb0994dfa276b Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 4 Sep 2020 09:17:40 +0200 Subject: [PATCH 6/8] cpu: boards: stm32l0l1: use IS_ACTIVE where possible in stmclk --- boards/b-l072z-lrwan1/include/periph_conf.h | 2 +- .../stm32/include/l0l1/cfg_clock_default.h | 79 ++++++++++--------- boards/i-nucleo-lrwan1/include/periph_conf.h | 2 +- boards/im880b/include/periph_conf.h | 2 +- boards/lobaro-lorabox/include/periph_conf.h | 2 +- boards/lsn50/include/periph_conf.h | 2 +- boards/nucleo-l031k6/include/periph_conf.h | 2 +- boards/nucleo-l053r8/include/periph_conf.h | 2 +- boards/nucleo-l073rz/include/periph_conf.h | 2 +- cpu/stm32/stmclk/stmclk_l0l1.c | 23 +++--- 10 files changed, 60 insertions(+), 58 deletions(-) diff --git a/boards/b-l072z-lrwan1/include/periph_conf.h b/boards/b-l072z-lrwan1/include/periph_conf.h index d618bce0b4..3381fb6bd7 100644 --- a/boards/b-l072z-lrwan1/include/periph_conf.h +++ b/boards/b-l072z-lrwan1/include/periph_conf.h @@ -21,7 +21,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/common/stm32/include/l0l1/cfg_clock_default.h b/boards/common/stm32/include/l0l1/cfg_clock_default.h index a50a4e6858..883a70e8f3 100644 --- a/boards/common/stm32/include/l0l1/cfg_clock_default.h +++ b/boards/common/stm32/include/l0l1/cfg_clock_default.h @@ -33,63 +33,63 @@ extern "C" { #ifndef CONFIG_USE_CLOCK_PLL #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \ IS_ACTIVE(CONFIG_USE_CLOCK_MSI) -#define CONFIG_USE_CLOCK_PLL (0) +#define CONFIG_USE_CLOCK_PLL 0 #else -#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */ +#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */ #endif #endif /* CONFIG_USE_CLOCK_PLL */ #ifndef CONFIG_USE_CLOCK_MSI -#define CONFIG_USE_CLOCK_MSI (0) +#define CONFIG_USE_CLOCK_MSI 0 #endif /* CONFIG_USE_CLOCK_MSI */ #ifndef CONFIG_USE_CLOCK_HSE -#define CONFIG_USE_CLOCK_HSE (0) +#define CONFIG_USE_CLOCK_HSE 0 #endif /* CONFIG_USE_CLOCK_HSE */ #ifndef CONFIG_USE_CLOCK_HSI -#define CONFIG_USE_CLOCK_HSI (0) +#define CONFIG_USE_CLOCK_HSI 0 #endif /* CONFIG_USE_CLOCK_HSI */ -#if CONFIG_USE_CLOCK_PLL && \ - (CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) +#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \ + IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) #error "Cannot use PLL as clock source with other clock configurations" #endif -#if CONFIG_USE_CLOCK_MSI && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) +#if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \ + IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) #error "Cannot use MSI as clock source with other clock configurations" #endif -#if CONFIG_USE_CLOCK_HSE && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSI) +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \ + IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) #error "Cannot use HSE as clock source with other clock configurations" #endif -#if CONFIG_USE_CLOCK_HSI && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE) +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \ + IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) #error "Cannot use HSI as clock source with other clock configurations" #endif #ifndef CONFIG_BOARD_HAS_HSE -#define CONFIG_BOARD_HAS_HSE (0) +#define CONFIG_BOARD_HAS_HSE 0 #endif #ifndef CLOCK_HSE #define CLOCK_HSE MHZ(24) #endif -#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24)) #error "HSE clock frequency must be between 1MHz and 24MHz" #endif -#ifndef CONFIG_CLOCK_HSI_USE_DIV4 -#define CONFIG_CLOCK_HSI_USE_DIV4 (0) -#endif - #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (0) +#define CONFIG_BOARD_HAS_LSE 0 #endif -#if CONFIG_BOARD_HAS_LSE +#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE) #define CLOCK_LSE (1) #else #define CLOCK_LSE (0) @@ -101,27 +101,28 @@ extern "C" { #define CONFIG_CLOCK_MSI KHZ(4194) #endif -#if CONFIG_USE_CLOCK_HSI -#define CLOCK_CORECLOCK (CLOCK_HSI) - -#elif CONFIG_USE_CLOCK_HSE -#if CONFIG_BOARD_HAS_HSE == 0 -#error "The board doesn't provide an HSE oscillator" -#endif -#define CLOCK_CORECLOCK (CLOCK_HSE) - -#elif CONFIG_USE_CLOCK_MSI -#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) - -#elif CONFIG_USE_CLOCK_PLL -/* The following parameters configure a 64MHz system clock with HSI as input clock */ +/* The following parameters configure a 32MHz system clock with HSI as input clock */ #ifndef CONFIG_CLOCK_PLL_DIV #define CONFIG_CLOCK_PLL_DIV (2) #endif #ifndef CONFIG_CLOCK_PLL_MUL #define CONFIG_CLOCK_PLL_MUL (4) #endif -#if CONFIG_BOARD_HAS_HSE + +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) +#define CLOCK_CORECLOCK (CLOCK_HSI) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) +#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#error "The board doesn't provide an HSE oscillator" +#endif +#define CLOCK_CORECLOCK (CLOCK_HSE) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #if CLOCK_HSE < MHZ(2) #error "HSE must be greater than 2MHz when used as PLL input clock" #endif @@ -134,9 +135,9 @@ extern "C" { * compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL) * with: * PLL_IN: input clock is HSE if available or HSI otherwise - * PLL_DIV : divider, allowed values: 2, 3, 4 - * PLL_MUL: multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48 - * CORECLOCK -> 48MHz MAX! + * PLL_DIV : divider, allowed values: 2, 3, 4. Default is 2. + * PLL_MUL: multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48. Default is 4. + * CORECLOCK -> 32MHz MAX! */ #define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL) #if CLOCK_CORECLOCK > MHZ(32) diff --git a/boards/i-nucleo-lrwan1/include/periph_conf.h b/boards/i-nucleo-lrwan1/include/periph_conf.h index 6ee600b59d..f97514f0f7 100644 --- a/boards/i-nucleo-lrwan1/include/periph_conf.h +++ b/boards/i-nucleo-lrwan1/include/periph_conf.h @@ -21,7 +21,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/im880b/include/periph_conf.h b/boards/im880b/include/periph_conf.h index 28f3f41e7a..d4e2bfc464 100644 --- a/boards/im880b/include/periph_conf.h +++ b/boards/im880b/include/periph_conf.h @@ -23,7 +23,7 @@ * This board provides an LSE, so enable it before including the default clock config */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/lobaro-lorabox/include/periph_conf.h b/boards/lobaro-lorabox/include/periph_conf.h index 8451e16f3c..37aa291cc7 100644 --- a/boards/lobaro-lorabox/include/periph_conf.h +++ b/boards/lobaro-lorabox/include/periph_conf.h @@ -28,7 +28,7 @@ * This board provides an LSE, so enable it before including the default clock config */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/lsn50/include/periph_conf.h b/boards/lsn50/include/periph_conf.h index 1ff10d0d1a..8caf9b212c 100644 --- a/boards/lsn50/include/periph_conf.h +++ b/boards/lsn50/include/periph_conf.h @@ -21,7 +21,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/nucleo-l031k6/include/periph_conf.h b/boards/nucleo-l031k6/include/periph_conf.h index f4d270da8a..b1acd433c2 100644 --- a/boards/nucleo-l031k6/include/periph_conf.h +++ b/boards/nucleo-l031k6/include/periph_conf.h @@ -23,7 +23,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/nucleo-l053r8/include/periph_conf.h b/boards/nucleo-l053r8/include/periph_conf.h index 753d3362fc..4960222fb9 100644 --- a/boards/nucleo-l053r8/include/periph_conf.h +++ b/boards/nucleo-l053r8/include/periph_conf.h @@ -23,7 +23,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/nucleo-l073rz/include/periph_conf.h b/boards/nucleo-l073rz/include/periph_conf.h index a24b128e2c..9a7a0918b4 100644 --- a/boards/nucleo-l073rz/include/periph_conf.h +++ b/boards/nucleo-l073rz/include/periph_conf.h @@ -23,7 +23,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/cpu/stm32/stmclk/stmclk_l0l1.c b/cpu/stm32/stmclk/stmclk_l0l1.c index 876631d128..c7d028f0bc 100644 --- a/cpu/stm32/stmclk/stmclk_l0l1.c +++ b/cpu/stm32/stmclk/stmclk_l0l1.c @@ -62,7 +62,7 @@ #endif /* Check the source to be used for the PLL */ -#if CONFIG_BOARD_HAS_HSE +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSE) #else /* Use HSI as PLL input */ #define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI) @@ -155,16 +155,23 @@ void stmclk_init_sysclk(void) /* Wait Until the Voltage Regulator is ready */ while((PWR->CSR & PWR_CSR_VOSF) != 0) {} - if (CONFIG_USE_CLOCK_HSE) { - /* Enable the HSE clock now */ + /* Only enable the HSE clock when it's provided by the board and required: + - when HSE is used as system clock + - when PLL is used as system clock (because HSE is used automatically + as PLL input if it's available) + */ + if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && + (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_PLL))) { RCC->CR |= (RCC_CR_HSEON); while (!(RCC->CR & RCC_CR_HSERDY)) {} + } + if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) { /* Select HSE as system clock and configure the different prescalers */ RCC->CFGR &= ~(RCC_CFGR_SW); RCC->CFGR |= RCC_CFGR_SW_HSE; } - else if (CONFIG_USE_CLOCK_MSI) { + else if (IS_ACTIVE(CONFIG_USE_CLOCK_MSI)) { /* Configure MSI range and enable it */ RCC->ICSCR |= CLOCK_MSIRANGE; RCC->CR |= (RCC_CR_MSION); @@ -174,13 +181,7 @@ void stmclk_init_sysclk(void) RCC->CFGR &= ~(RCC_CFGR_SW); RCC->CFGR |= RCC_CFGR_SW_MSI; } - else if (CONFIG_USE_CLOCK_PLL) { - if (CONFIG_BOARD_HAS_HSE) { - /* if configured, we need to enable the HSE clock now */ - RCC->CR |= (RCC_CR_HSEON); - while (!(RCC->CR & RCC_CR_HSERDY)) {} - } - + else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) { /* Configure PLL clock source and configure the different prescalers */ RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL); RCC->CFGR |= (CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | CLOCK_PLL_MUL); From 425a2f69a2826237eaff14742cec48ce92f30438 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 13 Sep 2020 22:04:29 +0200 Subject: [PATCH 7/8] cpu/stm32l0l1: ensure PLL is enabled when required PLL is required for the 48MHz output used by HWRNG and also when it's used as system clock --- cpu/stm32/stmclk/stmclk_l0l1.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/cpu/stm32/stmclk/stmclk_l0l1.c b/cpu/stm32/stmclk/stmclk_l0l1.c index c7d028f0bc..83175c6951 100644 --- a/cpu/stm32/stmclk/stmclk_l0l1.c +++ b/cpu/stm32/stmclk/stmclk_l0l1.c @@ -118,6 +118,13 @@ #error "Invalid MSI clock value" #endif +/* Check whether PLL must be enabled */ +#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_USED(MODULE_PERIPH_HWRNG) +#define CLOCK_ENABLE_PLL 1 +#else +#define CLOCK_ENABLE_PLL 0 +#endif + /** * @brief Configure the controllers clock system * @@ -181,7 +188,8 @@ void stmclk_init_sysclk(void) RCC->CFGR &= ~(RCC_CFGR_SW); RCC->CFGR |= RCC_CFGR_SW_MSI; } - else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) { + + if (IS_ACTIVE(CLOCK_ENABLE_PLL)) { /* Configure PLL clock source and configure the different prescalers */ RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL); RCC->CFGR |= (CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | CLOCK_PLL_MUL); @@ -190,11 +198,13 @@ void stmclk_init_sysclk(void) /* Wait till PLL is ready */ while (!(RCC->CR & RCC_CR_PLLRDY)) {} - /* Select PLL as system clock source */ - RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} + if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) { + /* Select PLL as system clock source */ + RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} + } } if (!IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || From c14d7ec7dbc2238ad251a70904407e503342b82d Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Thu, 17 Sep 2020 15:25:23 +0200 Subject: [PATCH 8/8] cpu/stm32l0l1: refactor clock initialization sequence --- cpu/stm32/stmclk/stmclk_l0l1.c | 95 +++++++++++++++++++++++----------- 1 file changed, 66 insertions(+), 29 deletions(-) diff --git a/cpu/stm32/stmclk/stmclk_l0l1.c b/cpu/stm32/stmclk/stmclk_l0l1.c index 83175c6951..52f8b8d936 100644 --- a/cpu/stm32/stmclk/stmclk_l0l1.c +++ b/cpu/stm32/stmclk/stmclk_l0l1.c @@ -118,13 +118,49 @@ #error "Invalid MSI clock value" #endif -/* Check whether PLL must be enabled */ +/* Check whether PLL must be enabled: + - When PLLCLK is used as SYSCLK + - When HWRNG feature is used (for the 48MHz clock) +*/ #if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_USED(MODULE_PERIPH_HWRNG) #define CLOCK_ENABLE_PLL 1 #else #define CLOCK_ENABLE_PLL 0 #endif +/* Check whether HSE must be enabled: + - When HSE is used as SYSCLK + - When PLL is used as SYSCLK and the board provides HSE (since HSE will be + used as PLL input clock) +*/ +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \ + (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) +#define CLOCK_ENABLE_HSE 1 +#else +#define CLOCK_ENABLE_HSE 0 +#endif + +/* Check whether HSI must be enabled: + - When HSI is used as SYSCLK + - When PLL is used as SYSCLK and the board doesn't provide HSE (since HSI will be + used as PLL input clock) +*/ +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \ + (!IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) +#define CLOCK_ENABLE_HSI 1 +#else +#define CLOCK_ENABLE_HSI 0 +#endif + +/* Check whether MSI must be enabled: + - When MSI is used as SYSCLK +*/ +#if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) +#define CLOCK_ENABLE_MSI 1 +#else +#define CLOCK_ENABLE_MSI 0 +#endif + /** * @brief Configure the controllers clock system * @@ -162,33 +198,21 @@ void stmclk_init_sysclk(void) /* Wait Until the Voltage Regulator is ready */ while((PWR->CSR & PWR_CSR_VOSF) != 0) {} - /* Only enable the HSE clock when it's provided by the board and required: - - when HSE is used as system clock - - when PLL is used as system clock (because HSE is used automatically - as PLL input if it's available) - */ - if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && - (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_PLL))) { + /* Enable HSE if needed */ + if (IS_ACTIVE(CLOCK_ENABLE_HSE)) { RCC->CR |= (RCC_CR_HSEON); while (!(RCC->CR & RCC_CR_HSERDY)) {} } - if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) { - /* Select HSE as system clock and configure the different prescalers */ - RCC->CFGR &= ~(RCC_CFGR_SW); - RCC->CFGR |= RCC_CFGR_SW_HSE; - } - else if (IS_ACTIVE(CONFIG_USE_CLOCK_MSI)) { + /* Enable MSI if needed */ + if (IS_ACTIVE(CLOCK_ENABLE_MSI)) { /* Configure MSI range and enable it */ RCC->ICSCR |= CLOCK_MSIRANGE; RCC->CR |= (RCC_CR_MSION); while (!(RCC->CR & RCC_CR_MSIRDY)) {} - - /* Select MSI as system clock and configure the different prescalers */ - RCC->CFGR &= ~(RCC_CFGR_SW); - RCC->CFGR |= RCC_CFGR_SW_MSI; } + /* Enable PLL if needed */ if (IS_ACTIVE(CLOCK_ENABLE_PLL)) { /* Configure PLL clock source and configure the different prescalers */ RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL); @@ -197,19 +221,32 @@ void stmclk_init_sysclk(void) RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while (!(RCC->CR & RCC_CR_PLLRDY)) {} - - if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) { - /* Select PLL as system clock source */ - RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} - } } - if (!IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || - (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && IS_ACTIVE(CONFIG_BOARD_HAS_HSE))) { - /* Disable HSI only if not used */ + /* Disable HSI if it's unused */ + if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) { + RCC->CFGR &= ~(RCC_CFGR_SW); + } + + /* Configure SYSCLK input source */ + if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) { + /* Select HSE as system clock and wait till it's used as system clock */ + RCC->CFGR |= RCC_CFGR_SW_HSE; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {} + } + else if (IS_ACTIVE(CONFIG_USE_CLOCK_MSI)) { + /* Select MSI as system clock and wait till it's used as system clock */ + RCC->CFGR |= RCC_CFGR_SW_MSI; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) {} + } + else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) { + RCC->CFGR |= RCC_CFGR_SW_PLL; + /* Select PLL as system clock and wait till it's used as system clock */ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} + } + + if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) { + /* Disable HSI only if not needed */ stmclk_disable_hsi(); }