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cpu/stm32: adapt UART driver for stm32l4r5 cpu line

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Alexandre Abadie 2020-06-04 19:56:28 +02:00
parent 8e87dedbce
commit 1a095b36fa
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GPG Key ID: 1C919A403CAE1405
1 changed files with 16 additions and 4 deletions
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14
cpu/stm32/periph/uart.c
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@ -34,7 +34,14 @@
#include "periph/gpio.h" #include "periph/gpio.h"
#include "pm_layered.h" #include "pm_layered.h"
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \ #if defined(CPU_LINE_STM32L4R5xx)
#define ISR_REG ISR
#define ISR_TXE USART_ISR_TXE_TXFNF
#define ISR_RXNE USART_ISR_RXNE_RXFNE
#define ISR_TC USART_ISR_TC
#define TDR_REG TDR
#define RDR_REG RDR
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \ defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32F7) || \ defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32G4) defined(CPU_FAM_STM32G4)
@ -53,7 +60,12 @@
#define RDR_REG DR #define RDR_REG DR
#endif #endif
#if defined(CPU_LINE_STM32L4R5xx)
#define RXENABLE (USART_CR1_RE | USART_CR1_RXNEIE_RXFNEIE)
#define USART_ISR_RXNE (USART_ISR_RXNE_RXFNE)
#else
#define RXENABLE (USART_CR1_RE | USART_CR1_RXNEIE) #define RXENABLE (USART_CR1_RE | USART_CR1_RXNEIE)
#endif
#ifdef MODULE_PERIPH_UART_NONBLOCKING #ifdef MODULE_PERIPH_UART_NONBLOCKING