diff --git a/boards/common/blxxxpill/Makefile.include b/boards/common/blxxxpill/Makefile.include
index ecbe5bfa91..139555db3f 100644
--- a/boards/common/blxxxpill/Makefile.include
+++ b/boards/common/blxxxpill/Makefile.include
@@ -1,3 +1,4 @@
+INCLUDES += -I$(RIOTBOARD)/common/stm32/include
 INCLUDES += -I$(RIOTBOARD)/common/blxxxpill/include
 
 ifeq (dfu-util,$(PROGRAMMER))
diff --git a/boards/common/blxxxpill/include/periph_conf.h b/boards/common/blxxxpill/include/periph_conf.h
index 2e813b07eb..f6ad5a7799 100644
--- a/boards/common/blxxxpill/include/periph_conf.h
+++ b/boards/common/blxxxpill/include/periph_conf.h
@@ -24,41 +24,16 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+/* blxxxpill boards provide an LSE */
+#define CLOCK_LSE            (1)
+
 #include "periph_cpu.h"
+#include "f1f3/cfg_clock_default.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 72MHz */
-#define CLOCK_CORECLOCK     (72000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE           (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE           (1U)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2     /* max 36MHz */
-#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1     /* max 72MHz */
-#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
-
-/* PLL factors */
-#define CLOCK_PLL_PREDIV     (1)
-#define CLOCK_PLL_MUL        (9)
-/** @} */
-
 /**
  * @name    Real time counter configuration
  * @{
diff --git a/boards/maple-mini/Makefile.include b/boards/maple-mini/Makefile.include
index d39a097844..09912771ba 100644
--- a/boards/maple-mini/Makefile.include
+++ b/boards/maple-mini/Makefile.include
@@ -1,3 +1,6 @@
+# Include shared STM32 headers
+INCLUDES += -I$(RIOTBOARD)/common/stm32/include
+
 # define the default port depending on the host OS
 PORT_LINUX ?= /dev/ttyACM0
 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
diff --git a/boards/maple-mini/include/periph_conf.h b/boards/maple-mini/include/periph_conf.h
index 60a8f05102..a278044de4 100644
--- a/boards/maple-mini/include/periph_conf.h
+++ b/boards/maple-mini/include/periph_conf.h
@@ -20,40 +20,12 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
+#include "f1f3/cfg_clock_default.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 72MHz */
-#define CLOCK_CORECLOCK     (72000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE           (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE           (0U)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2     /* max 36MHz */
-#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1     /* max 72MHz */
-#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
-
-/* PLL factors */
-#define CLOCK_PLL_PREDIV     (1)
-#define CLOCK_PLL_MUL        (9)
-/** @} */
-
 /**
  * @name   Timer configuration
  * @{
diff --git a/boards/nucleo-f103rb/include/periph_conf.h b/boards/nucleo-f103rb/include/periph_conf.h
index c34ff0ffe9..4205f526aa 100644
--- a/boards/nucleo-f103rb/include/periph_conf.h
+++ b/boards/nucleo-f103rb/include/periph_conf.h
@@ -19,41 +19,16 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+/* This board provides an LSE */
+#define CLOCK_LSE            (1)
+
 #include "periph_cpu.h"
+#include "f1f3/cfg_clock_default.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 72MHz */
-#define CLOCK_CORECLOCK      (72000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE            (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE            (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV        RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB            (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV       RCC_CFGR_PPRE1_DIV2     /* max 36MHz */
-#define CLOCK_APB1           (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2_DIV       RCC_CFGR_PPRE2_DIV1     /* max 72MHz */
-#define CLOCK_APB2           (CLOCK_CORECLOCK / 1)
-
-/* PLL factors */
-#define CLOCK_PLL_PREDIV     (1)
-#define CLOCK_PLL_MUL        (9)
-/** @} */
-
 /**
  * @name   Timer configuration
  * @{
diff --git a/boards/olimexino-stm32/include/periph_conf.h b/boards/olimexino-stm32/include/periph_conf.h
index effbffbde8..1820912345 100644
--- a/boards/olimexino-stm32/include/periph_conf.h
+++ b/boards/olimexino-stm32/include/periph_conf.h
@@ -19,41 +19,16 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+/* This board provides an LSE */
+#define CLOCK_LSE            (1)
+
 #include "periph_cpu.h"
+#include "f1f3/cfg_clock_default.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 72MHz */
-#define CLOCK_CORECLOCK      (72000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE            (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE            (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV        RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB            (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV       RCC_CFGR_PPRE1_DIV2        /* max 36MHz */
-#define CLOCK_APB1           (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2_DIV       RCC_CFGR_PPRE2_DIV1        /* max 72MHz */
-#define CLOCK_APB2           (CLOCK_CORECLOCK / 1)
-
-/* PLL factors */
-#define CLOCK_PLL_PREDIV     (1)
-#define CLOCK_PLL_MUL        (9)
-/** @} */
-
 /**
  * @name   ADC configuration
  * @{
diff --git a/boards/opencm904/Makefile.include b/boards/opencm904/Makefile.include
index 702f620de9..9f534872e1 100644
--- a/boards/opencm904/Makefile.include
+++ b/boards/opencm904/Makefile.include
@@ -1,3 +1,6 @@
+# Include shared STM32 headers
+INCLUDES += -I$(RIOTBOARD)/common/stm32/include
+
 # define the default port depending on the host OS
 PORT_LINUX ?= /dev/ttyACM0
 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
diff --git a/boards/opencm904/include/periph_conf.h b/boards/opencm904/include/periph_conf.h
index 72a9ef9942..d18121c9e6 100644
--- a/boards/opencm904/include/periph_conf.h
+++ b/boards/opencm904/include/periph_conf.h
@@ -20,40 +20,12 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
+#include "f1f3/cfg_clock_default.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * @name    Clock settings
- *
- * @note    This is auto-generated from
- *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 72MHz */
-#define CLOCK_CORECLOCK     (72000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE           (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE           (0U)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2     /* max 36MHz */
-#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1     /* max 72MHz */
-#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
-
-/* PLL factors */
-#define CLOCK_PLL_PREDIV     (1)
-#define CLOCK_PLL_MUL        (9)
-/** @} */
-
 /**
  * @name   Timer configuration
  * @{
diff --git a/boards/spark-core/Makefile.include b/boards/spark-core/Makefile.include
index 2554641f79..06c8e18cda 100644
--- a/boards/spark-core/Makefile.include
+++ b/boards/spark-core/Makefile.include
@@ -1,3 +1,6 @@
+# Include shared STM32 headers
+INCLUDES += -I$(RIOTBOARD)/common/stm32/include
+
 # configure the serial interface
 PORT_LINUX ?= /dev/ttyUSB0
 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
diff --git a/boards/spark-core/include/periph_conf.h b/boards/spark-core/include/periph_conf.h
index 43ef4b8a1a..a60f56052e 100644
--- a/boards/spark-core/include/periph_conf.h
+++ b/boards/spark-core/include/periph_conf.h
@@ -20,40 +20,12 @@
 #define PERIPH_CONF_H
 
 #include "periph_cpu.h"
+#include "f1f3/cfg_clock_default.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
- /**
-  * @name    Clock settings
-  *
-  * @note    This is auto-generated from
-  *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
-  * @{
-  */
- /* give the target core clock (HCLK) frequency [in Hz],
-  * maximum: 72MHz */
- #define CLOCK_CORECLOCK     (72000000U)
- /* 0: no external high speed crystal available
-  * else: actual crystal frequency [in Hz] */
- #define CLOCK_HSE           (8000000U)
- /* 0: no external low speed crystal available,
-  * 1: external crystal available (always 32.768kHz) */
- #define CLOCK_LSE           (0U)
- /* peripheral clock setup */
- #define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
- #define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
- #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2     /* max 36MHz */
- #define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
- #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1     /* max 72MHz */
- #define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
-
- /* PLL factors */
- #define CLOCK_PLL_PREDIV     (1)
- #define CLOCK_PLL_MUL        (9)
- /** @} */
-
 /**
  * @name   Timer configuration
  * @{