diff --git a/cpu/stm32/Makefile.features b/cpu/stm32/Makefile.features
index 4e06213fe5..235d140231 100644
--- a/cpu/stm32/Makefile.features
+++ b/cpu/stm32/Makefile.features
@@ -11,7 +11,7 @@ FEATURES_PROVIDED += periph_wdt
 
 ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 wb))
   FEATURES_PROVIDED += periph_flashpage
-  FEATURES_PROVIDED += periph_flashpage_raw
+  FEATURES_PROVIDED += periph_flashpage_pagewise
 endif
 
 ifneq (,$(filter $(CPU_FAM),l0 l1))
diff --git a/cpu/stm32/include/cpu_conf.h b/cpu/stm32/include/cpu_conf.h
index 44e70e607b..8487ef8284 100644
--- a/cpu/stm32/include/cpu_conf.h
+++ b/cpu/stm32/include/cpu_conf.h
@@ -116,20 +116,20 @@ extern "C" {
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32L5)
-#define FLASHPAGE_RAW_BLOCKSIZE         (8U)
+#define FLASHPAGE_WRITE_BLOCK_SIZE      (8U)
 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
-#define FLASHPAGE_RAW_BLOCKSIZE         (4U)
+#define FLASHPAGE_WRITE_BLOCK_SIZE      (4U)
 #else
-#define FLASHPAGE_RAW_BLOCKSIZE         (2U)
+#define FLASHPAGE_WRITE_BLOCK_SIZE      (2U)
 #endif
 
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32L5)
-#define FLASHPAGE_RAW_ALIGNMENT         (8U)
+#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT       (8U)
 #else
 /* Writing should be always 4 bytes aligned */
-#define FLASHPAGE_RAW_ALIGNMENT         (4U)
+#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT       (4U)
 #endif
 /** @} */
 
diff --git a/cpu/stm32/kconfigs/f0/Kconfig b/cpu/stm32/kconfigs/f0/Kconfig
index e8596c5ea9..05ee6e6d14 100644
--- a/cpu/stm32/kconfigs/f0/Kconfig
+++ b/cpu/stm32/kconfigs/f0/Kconfig
@@ -14,7 +14,7 @@ config CPU_FAM_F0
     select CPU_CORE_CORTEX_M0
     select HAS_CPU_STM32F0
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
 
 config HAS_CPU_STM32F0
     bool
diff --git a/cpu/stm32/kconfigs/f1/Kconfig b/cpu/stm32/kconfigs/f1/Kconfig
index 47018d7b1f..66fd9f1dbd 100644
--- a/cpu/stm32/kconfigs/f1/Kconfig
+++ b/cpu/stm32/kconfigs/f1/Kconfig
@@ -11,7 +11,7 @@ config CPU_FAM_F1
     select CPU_CORE_CORTEX_M3
     select HAS_CPU_STM32F1
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
 
 config CPU_FAM
     default "f1" if CPU_FAM_F1
diff --git a/cpu/stm32/kconfigs/f3/Kconfig b/cpu/stm32/kconfigs/f3/Kconfig
index 9b1d5755b2..a3cdd4c810 100644
--- a/cpu/stm32/kconfigs/f3/Kconfig
+++ b/cpu/stm32/kconfigs/f3/Kconfig
@@ -11,7 +11,7 @@ config CPU_FAM_F3
     select CPU_CORE_CORTEX_M4F
     select HAS_CPU_STM32F3
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
 
 config CPU_FAM
     default "f3" if CPU_FAM_F3
diff --git a/cpu/stm32/kconfigs/g0/Kconfig b/cpu/stm32/kconfigs/g0/Kconfig
index cda1632539..f47bf05af7 100644
--- a/cpu/stm32/kconfigs/g0/Kconfig
+++ b/cpu/stm32/kconfigs/g0/Kconfig
@@ -11,7 +11,7 @@ config CPU_FAM_G0
     select CPU_CORE_CORTEX_M0PLUS
     select HAS_CPU_STM32G0
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
 
 config CPU_FAM
     default "g0" if CPU_FAM_G0
diff --git a/cpu/stm32/kconfigs/g4/Kconfig b/cpu/stm32/kconfigs/g4/Kconfig
index 8c6967e393..02851b1a22 100644
--- a/cpu/stm32/kconfigs/g4/Kconfig
+++ b/cpu/stm32/kconfigs/g4/Kconfig
@@ -12,7 +12,7 @@ config CPU_FAM_G4
     select HAS_CPU_STM32G4
     select HAS_CORTEXM_MPU
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_HWRNG
 
 config CPU_FAM
diff --git a/cpu/stm32/kconfigs/l0/Kconfig b/cpu/stm32/kconfigs/l0/Kconfig
index a59802a290..9f441b43c9 100644
--- a/cpu/stm32/kconfigs/l0/Kconfig
+++ b/cpu/stm32/kconfigs/l0/Kconfig
@@ -11,7 +11,7 @@ config CPU_FAM_L0
     select CPU_CORE_CORTEX_M0PLUS
     select HAS_CPU_STM32L0
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_EEPROM
 
 config CPU_FAM
diff --git a/cpu/stm32/kconfigs/l1/Kconfig b/cpu/stm32/kconfigs/l1/Kconfig
index f69fbd4c24..a99ea64a25 100644
--- a/cpu/stm32/kconfigs/l1/Kconfig
+++ b/cpu/stm32/kconfigs/l1/Kconfig
@@ -12,7 +12,7 @@ config CPU_FAM_L1
     select HAS_CPU_STM32L1
     select HAS_CORTEXM_MPU
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_EEPROM
 
 config CPU_FAM
diff --git a/cpu/stm32/kconfigs/l4/Kconfig b/cpu/stm32/kconfigs/l4/Kconfig
index c9b567db8d..5ddf175fd1 100644
--- a/cpu/stm32/kconfigs/l4/Kconfig
+++ b/cpu/stm32/kconfigs/l4/Kconfig
@@ -12,7 +12,7 @@ config CPU_FAM_L4
     select HAS_CPU_STM32L4
     select HAS_CORTEXM_MPU
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_HWRNG
 
 config CPU_FAM
diff --git a/cpu/stm32/kconfigs/l5/Kconfig b/cpu/stm32/kconfigs/l5/Kconfig
index 77dd324983..ff8a4c294a 100644
--- a/cpu/stm32/kconfigs/l5/Kconfig
+++ b/cpu/stm32/kconfigs/l5/Kconfig
@@ -11,7 +11,7 @@ config CPU_FAM_L5
     select CPU_CORE_CORTEX_M33
     select HAS_CPU_STM32L5
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_HWRNG
 
 config CPU_FAM
diff --git a/cpu/stm32/kconfigs/wb/Kconfig b/cpu/stm32/kconfigs/wb/Kconfig
index cd8bc8ef5f..76e922f318 100644
--- a/cpu/stm32/kconfigs/wb/Kconfig
+++ b/cpu/stm32/kconfigs/wb/Kconfig
@@ -11,7 +11,7 @@ config CPU_FAM_WB
     select CPU_CORE_CORTEX_M4
     select HAS_CPU_STM32WB
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_HWRNG
 
 config CPU_FAM
diff --git a/cpu/stm32/periph/flashpage.c b/cpu/stm32/periph/flashpage.c
index bf39b136d4..ca6c545940 100644
--- a/cpu/stm32/periph/flashpage.c
+++ b/cpu/stm32/periph/flashpage.c
@@ -163,15 +163,30 @@ static void _erase_page(void *page_addr)
 #endif
 }
 
-void flashpage_write_raw(void *target_addr, const void *data, size_t len)
+void flashpage_erase(unsigned page)
 {
-    /* assert multiples of FLASHPAGE_RAW_BLOCKSIZE are written and no less of
+    assert(page < (int)FLASHPAGE_NUMOF);
+
+    /* ensure there is no attempt to write to CPU2 protected area */
+#if defined(CPU_FAM_STM32WB)
+    assert(page < (int)(FLASH->SFR & FLASH_SFR_SFSA));
+#endif
+
+    void *page_addr = flashpage_addr(page);
+
+    /* ERASE sequence */
+    _erase_page(page_addr);
+}
+
+void flashpage_write(void *target_addr, const void *data, size_t len)
+{
+    /* assert multiples of FLASHPAGE_WRITE_BLOCK_SIZE are written and no less of
        that length. */
-    assert(!(len % FLASHPAGE_RAW_BLOCKSIZE));
+    assert(!(len % FLASHPAGE_WRITE_BLOCK_SIZE));
 
     /* ensure writes are aligned */
-    assert(!(((unsigned)target_addr % FLASHPAGE_RAW_ALIGNMENT) ||
-            ((unsigned)data % FLASHPAGE_RAW_ALIGNMENT)));
+    assert(!(((unsigned)target_addr % FLASHPAGE_WRITE_BLOCK_ALIGNMENT) ||
+            ((unsigned)data % FLASHPAGE_WRITE_BLOCK_ALIGNMENT)));
 
     /* ensure the length doesn't exceed the actual flash size */
     assert(((unsigned)target_addr + len) <
@@ -238,23 +253,3 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
     }
 #endif
 }
-
-void flashpage_write(int page, const void *data)
-{
-    assert(page < (int)FLASHPAGE_NUMOF);
-
-    /* ensure there is no attempt to write to CPU2 protected area */
-#if defined(CPU_FAM_STM32WB)
-    assert(page < (int)(FLASH->SFR & FLASH_SFR_SFSA));
-#endif
-
-    void *page_addr = flashpage_addr(page);
-
-    /* ERASE sequence */
-    _erase_page(page_addr);
-
-    /* WRITE sequence */
-    if (data != NULL) {
-        flashpage_write_raw(page_addr, data, FLASHPAGE_SIZE);
-    }
-}