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cpu/cc2538: adapt and cleanup periph/hwrng

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Some minor adaptions due to cleanup in periph/adc and usage of
    vendor header files.
This commit is contained in:
smlng 2018-08-10 09:31:33 +02:00
parent d40cfab95a
commit 214ddc4fc4
1 changed files with 20 additions and 11 deletions
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31
cpu/cc2538/periph/hwrng.c
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@ -21,22 +21,31 @@
* @} * @}
*/ */
#include "vendor/hw_memmap.h"
#include "vendor/hw_soc_adc.h"
#include "cpu.h" #include "cpu.h"
#include "periph/hwrng.h" #include "periph/hwrng.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
static cc2538_soc_adc_t *soc_adc = (cc2538_soc_adc_t *)SOC_ADC_BASE;
void hwrng_init(void) void hwrng_init(void)
{ {
uint16_t seed = 0; uint16_t seed = 0;
int i; int i;
/* Make sure the RNG is on */ /* Make sure the RNG is on */
SOC_ADC->cc2538_adc_adccon1.ADCCON1bits.RCTRL = 0; uint32_t reg32 = soc_adc->ADCCON1 & ~(SOC_ADC_ADCCON1_RCTRL_M);
soc_adc->ADCCON1 = reg32;
/* Enable clock for the RF Core */ /* Enable clock for the RF Core */
SYS_CTRL_RCGCRFC = 1; SYS_CTRL_RCGCRFC = 1;
/* Wait for the clock ungating to take effect */ /* Wait for the clock ungating to take effect */
while (SYS_CTRL_RCGCRFC != 1); while (SYS_CTRL_RCGCRFC != 1) {}
/* Infinite RX - FRMCTRL0[3:2] = 10. This will mess with radio operation */ /* Infinite RX - FRMCTRL0[3:2] = 10. This will mess with radio operation */
RFCORE_XREG_FRMCTRL0 = 0x00000008; RFCORE_XREG_FRMCTRL0 = 0x00000008;
@ -63,8 +72,8 @@ void hwrng_init(void)
} }
/* Seed the high byte first: */ /* Seed the high byte first: */
SOC_ADC_RNDL = (seed >> 8) & 0xff; soc_adc->RNDH = (seed >> 8) & 0xff;
SOC_ADC_RNDL = seed & 0xff; soc_adc->RNDL = seed & 0xff;
/* Turn RF off: */ /* Turn RF off: */
RFCORE_SFR_RFST = ISRFOFF; RFCORE_SFR_RFST = ISRFOFF;
@ -72,16 +81,16 @@ void hwrng_init(void)
void hwrng_read(void *buf, unsigned int num) void hwrng_read(void *buf, unsigned int num)
{ {
unsigned count;
uint8_t *b = (uint8_t *)buf; uint8_t *b = (uint8_t *)buf;
for (count = 0; count < num; ) { for (unsigned count = 0; count < num; count++) {
/* Clock the RNG LSFR once: */ /* Clock the RNG LSFR once: */
SOC_ADC->cc2538_adc_adccon1.ADCCON1bits.RCTRL = 1; soc_adc->ADCCON1 = soc_adc->ADCCON1 | (1UL << SOC_ADC_ADCCON1_RCTRL_S);
/* Read up to 2 bytes of hwrng data: */ /* Read up to 2 bytes of hwrng data: */
b[count++] = SOC_ADC_RNDL; b[count] = soc_adc->RNDL;
if (count >= num) break; count++;
b[count++] = SOC_ADC_RNDH; if (count < num) {
b[count] = soc_adc->RNDH;
}
} }
} }