From 4e235b8e7637e93b1f28831491e814d6aac0fb16 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Wed, 9 Sep 2020 15:59:38 +0200 Subject: [PATCH] cpu/stm32l4wb: fix APBx bitfields for divider factor 2 --- cpu/stm32/stmclk/stmclk_l4wb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/stm32/stmclk/stmclk_l4wb.c b/cpu/stm32/stmclk/stmclk_l4wb.c index 793847ce89..14213a781e 100644 --- a/cpu/stm32/stmclk/stmclk_l4wb.c +++ b/cpu/stm32/stmclk/stmclk_l4wb.c @@ -146,7 +146,7 @@ #if CONFIG_CLOCK_APB1_DIV == 1 #define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1) #elif CONFIG_CLOCK_APB1_DIV == 2 -#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV1) +#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV2) #elif CONFIG_CLOCK_APB1_DIV == 4 #define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_DIV4) #elif CONFIG_CLOCK_APB1_DIV == 8 @@ -158,7 +158,7 @@ #if CONFIG_CLOCK_APB2_DIV == 1 #define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1) #elif CONFIG_CLOCK_APB2_DIV == 2 -#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV1) +#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV2) #elif CONFIG_CLOCK_APB2_DIV == 4 #define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_DIV4) #elif CONFIG_CLOCK_APB2_DIV == 8