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kinetis: Unify all Kinetis CPUs in one directory

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This commit is contained in:
Joakim Nohlgård 2017-10-27 01:26:26 +02:00
parent cb8e3f19a2
commit 22c52bd3a8
97 changed files with 454 additions and 513 deletions
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6
boards/frdm-common/Makefile.include
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@ -19,12 +19,12 @@ ifeq (1,$(USE_OLD_OPENOCD))
# wdog-disable.bin is a precompiled binary which will disable the watchdog and
# return control to the debugger (OpenOCD)
export OPENOCD_PRE_VERIFY_CMDS += \
-c 'load_image $(RIOTCPU)/kinetis_common/dist/wdog-disable.bin 0x20000000 bin' \
-c 'load_image $(RIOTCPU)/$(CPU)/dist/wdog-disable.bin 0x20000000 bin' \
-c 'resume 0x20000000'
export OPENOCD_EXTRA_INIT
.PHONY: flash
flash: $(RIOTCPU)/kinetis_common/dist/wdog-disable.bin
flash: $(RIOTCPU)/$(CPU)/dist/wdog-disable.bin
# Reset the default goal.
.DEFAULT_GOAL :=
@ -36,7 +36,7 @@ endif
export OPENOCD_CONFIG ?= $(RIOTBOARD)/frdm-common/dist/openocd-$(FRDM_IFACE)-$(CPU_FAMILY).cfg
# Check the flash configuration field before flashing
export PRE_FLASH_CHECK_SCRIPT = $(RIOTCPU)/kinetis_common/dist/check-fcfield-elf.sh
export PRE_FLASH_CHECK_SCRIPT = $(RIOTCPU)/$(CPU)/dist/check-fcfield-elf.sh
# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk

2
boards/frdm-k22f/Makefile.dep
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@ -3,4 +3,4 @@ ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_adc
endif
-include $(RIOTCPU)/k22f/Makefile.dep
include $(RIOTCPU)/kinetis/Makefile.dep

3
boards/frdm-k22f/Makefile.features
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@ -1,6 +1,5 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
@ -12,4 +11,4 @@ FEATURES_PROVIDED += periph_uart
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_1
-include $(RIOTCPU)/k22f/Makefile.features
include $(RIOTCPU)/kinetis/Makefile.features

2
boards/frdm-k22f/Makefile.include
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@ -1,5 +1,5 @@
# define the cpu used by the board
export CPU = k22f
export CPU = kinetis
export CPU_MODEL = mk22fn512vlh12
# Include default FRDM board config

2
boards/frdm-k22f/include/periph_conf.h
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@ -161,7 +161,7 @@ static const pwm_conf_t pwm_config[] = {
* Clock configuration values based on the configured 48Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/

2
boards/frdm-k64f/Makefile.dep
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@ -1 +1 @@
-include $(RIOTCPU)/k64f/Makefile.dep
include $(RIOTCPU)/kinetis/Makefile.dep

3
boards/frdm-k64f/Makefile.features
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@ -1,6 +1,5 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
@ -12,4 +11,4 @@ FEATURES_PROVIDED += periph_uart
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_1
-include $(RIOTCPU)/k64f/Makefile.features
include $(RIOTCPU)/kinetis/Makefile.features

2
boards/frdm-k64f/Makefile.include
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@ -1,5 +1,5 @@
# define the cpu used by the FRDM-K64F board
export CPU = k64f
export CPU = kinetis
export CPU_MODEL = mk64fn1m0vll12
# Include default FRDM board config

2
boards/frdm-k64f/include/periph_conf.h
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@ -156,7 +156,7 @@ static const pwm_conf_t pwm_config[] = {
* Clock configuration values based on the configured 30Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/

4
boards/mulle/Makefile.dep
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@ -12,10 +12,12 @@ USEMODULE += nvram
USEMODULE += devfs
USEMODULE += mtd_spi_nor
# mulle always uses it's rtt
# mulle always uses the rtt for the oscillator
USEMODULE += periph_rtt
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
USEMODULE += saul_adc
endif
include $(RIOTCPU)/kinetis/Makefile.dep

3
boards/mulle/Makefile.features
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@ -1,7 +1,6 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_dac
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
@ -13,4 +12,4 @@ FEATURES_PROVIDED += periph_uart
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_2
-include $(RIOTCPU)/k60/Makefile.features
include $(RIOTCPU)/kinetis/Makefile.features

8
boards/mulle/Makefile.include
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@ -1,5 +1,5 @@
# define the cpu used by the Mulle board
export CPU = k60
export CPU = kinetis
# Default GDB port
export GDBPORT ?= 3333
@ -84,13 +84,13 @@ endif
# wdog-disable.bin is a precompiled binary which will disable the watchdog and
# return control to the debugger (OpenOCD)
export OPENOCD_PRE_VERIFY_CMDS += \
-c 'load_image $(RIOTCPU)/kinetis_common/dist/wdog-disable.bin 0x20000000 bin' \
-c 'load_image $(RIOTCPU)/$(CPU)/dist/wdog-disable.bin 0x20000000 bin' \
-c 'resume 0x20000000'
export OPENOCD_EXTRA_INIT
export PRE_FLASH_CHECK_SCRIPT = $(RIOTCPU)/kinetis_common/dist/check-fcfield-elf.sh
export PRE_FLASH_CHECK_SCRIPT = $(RIOTCPU)/$(CPU)/dist/check-fcfield-elf.sh
.PHONY: flash
flash: $(RIOTCPU)/kinetis_common/dist/wdog-disable.bin
flash: $(RIOTCPU)/$(CPU)/dist/wdog-disable.bin
# Reset the default goal.
.DEFAULT_GOAL :=

2
boards/mulle/include/periph_conf.h
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@ -238,7 +238,7 @@ static const pwm_conf_t pwm_config[] = {
* Clock configuration values based on the configured 47988736Hz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/

2
boards/pba-d-01-kw2x/Makefile.dep
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@ -12,4 +12,4 @@ ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += tmp006
endif
-include $(RIOTCPU)/kw2xd/Makefile.dep
include $(RIOTCPU)/kinetis/Makefile.dep

3
boards/pba-d-01-kw2x/Makefile.features
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@ -1,6 +1,5 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
@ -12,4 +11,4 @@ FEATURES_PROVIDED += periph_uart
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_3
-include $(RIOTCPU)/kw2xd/Makefile.features
include $(RIOTCPU)/kinetis/Makefile.features

10
boards/pba-d-01-kw2x/Makefile.include
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@ -1,10 +1,10 @@
# define the cpu used by the phyWAVE-KW22 board
export CPU = kw2xd
export CPU = kinetis
# the pba-d-01-kw2x board can embed either a kw21d256, kw21d512 or kw22d512 cpu.
# The default set up is kw21d256, the variable is overrideable to use the other
# cpu if needed.
export CPU_MODEL ?= kw21d256
export CPU_MODEL ?= mkw21d256vha5
export MCPU = cortex-m4
@ -13,7 +13,7 @@ PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
.PHONY: flash
flash: $(RIOTCPU)/kinetis_common/dist/wdog-disable.bin
flash: $(RIOTCPU)/$(CPU)/dist/wdog-disable.bin
# Reset the default goal.
.DEFAULT_GOAL :=
@ -23,10 +23,10 @@ flash: $(RIOTCPU)/kinetis_common/dist/wdog-disable.bin
# wdog-disable.bin is a precompiled binary which will disable the watchdog and
# return control to the debugger (OpenOCD)
export OPENOCD_PRE_VERIFY_CMDS += \
-c 'load_image $(RIOTCPU)/kinetis_common/dist/wdog-disable.bin 0x20000000 bin' \
-c 'load_image $(RIOTCPU)/$(CPU)/dist/wdog-disable.bin 0x20000000 bin' \
-c 'resume 0x20000000'
export OPENOCD_EXTRA_INIT
export PRE_FLASH_CHECK_SCRIPT = $(RIOTCPU)/kinetis_common/dist/check-fcfield-elf.sh
export PRE_FLASH_CHECK_SCRIPT = $(RIOTCPU)/$(CPU)/dist/check-fcfield-elf.sh
# Add board selector (USB serial) to OpenOCD options if specified.
# Use /dist/tools/usb-serial/list-ttys.sh to find out serial number.

2
boards/pba-d-01-kw2x/include/periph_conf.h
View File

@ -171,7 +171,7 @@ static const pwm_conf_t pwm_config[] = {
* Clock configuration values based on the configured 48Mhz module clock.
*
* Auto-generated by:
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
* cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c
*
* @{
*/

7
cpu/k22f/Makefile
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@ -1,7 +0,0 @@
# define the module that is build
MODULE = cpu
# add a list of subdirectories that should also be built
DIRS = periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON)
include $(RIOTBASE)/Makefile.base

1
cpu/k22f/Makefile.dep
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@ -1 +0,0 @@
-include $(RIOTCPU)/kinetis_common/Makefile.dep

1
cpu/k22f/Makefile.features
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@ -1 +0,0 @@
-include $(RIOTCPU)/kinetis_common/Makefile.features

22
cpu/k22f/Makefile.include
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@ -1,22 +0,0 @@
# define the CPU architecture for the k22f
export CPU_ARCH = cortex-m4
export CPU_FAMILY = kx
# map CPU models to generic Kinetis linker script
LD_MK22FN512VLH12 = kinetis_f512l64u64.ld
LD_MK22FN512VLL12 = kinetis_f512l64u64.ld
LD_MK22FN512VDC12 = kinetis_f512l64u64.ld
LD_MK22FN512VMP12 = kinetis_f512l64u64.ld
# tell the build system that the CPU depends on the Kinetis common files
export USEMODULE += kinetis_common
# define path to kinetis module, which is needed for this CPU
export KINETIS_COMMON = $(RIOTCPU)/kinetis_common/
# CPU depends on the kinetis module, so include it
include $(KINETIS_COMMON)Makefile.include
# this CPU implementation is using kinetis common startup
export COMMON_STARTUP = $(KINETIS_COMMON)
include $(RIOTMAKE)/arch/cortexm.inc.mk

7
cpu/k60/Makefile
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@ -1,7 +0,0 @@
# define the module that is build
MODULE = cpu
# add a list of subdirectories, that should also be build
DIRS = periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON)
include $(RIOTBASE)/Makefile.base

1
cpu/k60/Makefile.features
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@ -1 +0,0 @@
-include $(RIOTCPU)/kinetis_common/Makefile.features

19
cpu/k60/Makefile.include
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@ -1,19 +0,0 @@
# define the CPU architecture for the k60
export CPU_ARCH = cortex-m4
# map CPU models to generic Kinetis linkerscript
LD_MK60DN256VLL10 = kinetis_f256l16u16.ld
LD_MK60DN512VLL10 = kinetis_f512l64u64.ld
# tell the build system that the CPU depends on the Kinetis common files
export USEMODULE += kinetis_common
# define path to kinetis module, which is needed for this CPU
export KINETIS_COMMON = $(RIOTCPU)/kinetis_common/
# CPU depends on the kinetis module, so include it
include $(KINETIS_COMMON)Makefile.include
# this CPU implementation is using kinetis common startup
export COMMON_STARTUP = $(KINETIS_COMMON)
include $(RIOTMAKE)/arch/cortexm.inc.mk

51
cpu/k60/include/cpu_conf.h
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@ -1,51 +0,0 @@
/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup cpu_k60 NXP Kinetis K60
* @ingroup cpu
* @brief CPU specific implementations for the NXP Kinetis K60
* Cortex-M4 MCU
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef CPU_CONF_H
#define CPU_CONF_H
#if defined(CPU_MODEL_MK60DN512VLL10) || defined(CPU_MODEL_MK60DN256VLL10)
#include "vendor/MK60D10.h"
/* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */
#define KINETIS_RNGA (RNG)
#else
#error Unknown CPU model. Update Makefile.include in the board directory.
#endif
#include "cpu_conf_kinetis.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
*/
#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_H */
/** @} */

1
cpu/k60/periph/Makefile
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@ -1 +0,0 @@
include $(RIOTMAKE)/periph.mk

7
cpu/k64f/Makefile
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@ -1,7 +0,0 @@
# define the module that is build
MODULE = cpu
# add a list of subdirectories, that should also be build
DIRS = periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON)
include $(RIOTBASE)/Makefile.base

1
cpu/k64f/Makefile.dep
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@ -1 +0,0 @@
-include $(RIOTCPU)/kinetis_common/Makefile.dep

1
cpu/k64f/Makefile.features
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@ -1 +0,0 @@
-include $(RIOTCPU)/kinetis_common/Makefile.features

19
cpu/k64f/Makefile.include
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@ -1,19 +0,0 @@
# define the CPU architecture for the k64f
export CPU_ARCH = cortex-m4
export CPU_FAMILY = kx
# map CPU models to generic Kinetis linkerscript
LD_MK64FN1M0VLL12 = kinetis_f1024l64u192.ld
# tell the build system that the CPU depends on the Kinetis common files
export USEMODULE += kinetis_common
# define path to kinetis module, which is needed for this CPU
export KINETIS_COMMON = $(RIOTCPU)/kinetis_common/
# CPU depends on the kinetis module, so include it
include $(KINETIS_COMMON)Makefile.include
# this CPU implementation is using kinetis common startup
export COMMON_STARTUP = $(KINETIS_COMMON)
include $(RIOTMAKE)/arch/cortexm.inc.mk

45
cpu/k64f/include/cpu_conf.h
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@ -1,45 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
* Copyright (C) 2015 PHYTEC Messtechnik GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup cpu_k64f NXP Kinetis K64F
* @ingroup cpu
* @brief CPU specific implementations for the NXP Kinetis K64F
* Cortex-M4 MCU
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Johann Fischer <j.fischer@phytec.de>
*/
#ifndef CPU_CONF_H
#define CPU_CONF_H
#ifdef CPU_MODEL_MK64FN1M0VLL12
#include "vendor/MK64F12.h"
#else
#error "undefined CPU_MODEL"
#endif
#include "cpu_conf_kinetis.h"
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_H */
/** @} */

1
cpu/k64f/periph/Makefile
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@ -1 +0,0 @@
include $(RIOTMAKE)/periph.mk

10
cpu/kinetis/Makefile Normal file
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@ -0,0 +1,10 @@
# define the module that is build
MODULE = cpu
# add a list of subdirectories that should also be built
DIRS = periph $(RIOTCPU)/cortexm_common
# (file triggers compiler bug. see https://github.com/RIOT-OS/RIOT/issues/5775)
SRC_NOLTO += vectors.c
include $(RIOTBASE)/Makefile.base

0
cpu/kinetis_common/Makefile.dep → cpu/kinetis/Makefile.dep
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5
cpu/kinetis/Makefile.features Normal file
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@ -0,0 +1,5 @@
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_gpio
include $(RIOTCPU)/cortexm_common/Makefile.features

21
cpu/kinetis_common/Makefile.include → cpu/kinetis/Makefile.include
View File

@ -4,11 +4,8 @@ ifeq (,$(KINETIS_SERIES))
include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/kinetis-info.mk
endif
# include module specific includes
export INCLUDES += -I$(RIOTCPU)/kinetis_common/include
# Add search path for linker scripts
export LINKFLAGS += -L$(RIOTCPU)/kinetis_common/ldscripts
LINKFLAGS += -L$(RIOTCPU)/$(CPU)/ldscripts
# Use generic linker script for all Kinetis based CPUs
LINKER_SCRIPT = kinetis.ld
@ -33,14 +30,10 @@ LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_ram_start_addr=$(RAM_START_ADDR)
LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_rom_length=$(ROM_LEN)
LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_ram_length=$(RAM_LEN)
# add the CPU specific code for the linker
export UNDEF += $(BINDIR)/kinetis_common/fcfield.o
# add the CPU specific flash configuration field for the linker
export UNDEF += $(BINDIR)/cpu/fcfield.o
# add the CPU specific interrupt vector table definition for the linker
export UNDEF += $(BINDIR)/kinetis_common/vectors.o
# include kinetis common periph drivers
USEMODULE += kinetis_common_periph
# include common periph drivers
USEMODULE += periph_common
# select kinetis periph drivers
@ -48,8 +41,10 @@ USEMODULE += periph_mcg
USEMODULE += periph_wdog
# Define a recipe to build the watchdog disable binary, used when flashing
$(RIOTCPU)/kinetis_common/dist/wdog-disable.bin: $(RIOTCPU)/kinetis_common/dist/wdog-disable.s
$(Q)$(MAKE) -C $(RIOTCPU)/kinetis_common/dist/ $(notdir $@)
$(RIOTCPU)/$(CPU)/dist/wdog-disable.bin: $(RIOTCPU)/$(CPU)/dist/wdog-disable.s
$(Q)$(MAKE) -C $(RIOTCPU)/$(CPU)/dist/ $(notdir $@)
# Reset the default goal to not make wdog-disable.bin the default target.
.DEFAULT_GOAL :=
include $(RIOTMAKE)/arch/cortexm.inc.mk

2
cpu/kinetis_common/cpu.c → cpu/kinetis/cpu.c
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@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @{
*
* @file

0
cpu/kinetis_common/dist/Makefile → cpu/kinetis/dist/Makefile vendored
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0
cpu/kinetis_common/dist/README.md → cpu/kinetis/dist/README.md vendored
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0
cpu/kinetis_common/dist/calc_spi_scalers/Makefile → cpu/kinetis/dist/calc_spi_scalers/Makefile vendored
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0
cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c → cpu/kinetis/dist/calc_spi_scalers/calc_spi_scalers.c vendored
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0
cpu/kinetis_common/dist/check-fcfield-elf.sh → cpu/kinetis/dist/check-fcfield-elf.sh vendored
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0
cpu/kinetis_common/dist/check-fcfield-hex.sh → cpu/kinetis/dist/check-fcfield-hex.sh vendored
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0
cpu/kinetis_common/dist/wdog-disable.s → cpu/kinetis/dist/wdog-disable.s vendored
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76
cpu/kinetis_common/doc.txt → cpu/kinetis/doc.txt
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@ -1,13 +1,13 @@
/**
* @defgroup cpu_kinetis_common NXP Kinetis MCU
* @defgroup cpu_kinetis NXP Kinetis
* @ingroup cpu
* @brief NXP Kinetis CPU peripheral drivers
* @brief NXP Kinetis Cortex-M MCU specific implementation
*/
/**
* @defgroup cpu_kinetis_common_adc Kinetis ADC
* @ingroup cpu_kinetis_common
* @brief ADC driver
* @defgroup cpu_kinetis_adc Kinetis ADC
* @ingroup cpu_kinetis
* @brief Kinetis ADC driver
*
* ### ADC configuration example (for periph_conf.h) ###
*
@ -25,17 +25,17 @@
*/
/**
* @defgroup cpu_kinetis_common_cpuid Kinetis CPUID
* @ingroup cpu_kinetis_common
* @brief CPUID driver
* @defgroup cpu_kinetis_cpuid Kinetis CPUID
* @ingroup cpu_kinetis
* @brief Kinetis CPUID driver
*
* No configuration is necessary.
*/
/**
* @defgroup cpu_kinetis_common_gpio Kinetis GPIO
* @ingroup cpu_kinetis_common
* @brief GPIO driver
* @defgroup cpu_kinetis_gpio Kinetis GPIO
* @ingroup cpu_kinetis
* @brief Kinetis GPIO driver
*
* The GPIO driver uses the @ref GPIO_PIN(port, pin) macro to declare pins.
*
@ -43,9 +43,9 @@
*/
/**
* @defgroup cpu_kinetis_common_i2c Kinetis I2C
* @ingroup cpu_kinetis_common
* @brief I2C driver
* @defgroup cpu_kinetis_i2c Kinetis I2C
* @ingroup cpu_kinetis
* @brief Kinetis I2C driver
*
* ### I2C configuration example (for periph_conf.h) ###
*
@ -81,9 +81,9 @@
*/
/**
* @defgroup cpu_kinetis_common_pwm Kinetis PWM
* @ingroup cpu_kinetis_common
* @brief PWM driver
* @defgroup cpu_kinetis_pwm Kinetis PWM
* @ingroup cpu_kinetis
* @brief Kinetis PWM driver
*
* ### PWM configuration example (for periph_conf.h) ###
*
@ -112,9 +112,9 @@
*/
/**
* @defgroup cpu_kinetis_common_rnga Kinetis RNGA
* @ingroup cpu_kinetis_common
* @brief Driver for Freescale's RNGA module. RNGA generates data that
* @defgroup cpu_kinetis_rnga Kinetis RNGA
* @ingroup cpu_kinetis
* @brief Driver for NXP Kinetis RNGA module. RNGA generates data that
* looks random. Reference Manual recommends to use the RNGA as entropy
* source.
*
@ -127,10 +127,10 @@
*/
/**
* @defgroup cpu_kinetis_common_rngb Kinetis RNGB
* @ingroup cpu_kinetis_common
* @defgroup cpu_kinetis_rngb Kinetis RNGB
* @ingroup cpu_kinetis
* @brief Low-level random number generator driver implementation.
* Driver for Freescale's RNGB module. RNGB generates data that
* Driver for NXP Kinetis RNGB module. RNGB generates data that
* looks random. Reference Manual recommends to use the RNGB as entropy
* source.
*
@ -143,9 +143,12 @@
*/
/**
* @defgroup cpu_kinetis_common_rtc Kinetis RTC
* @ingroup cpu_kinetis_common
* @brief RTC is clocked by a 32.768 kHz clock.
* @defgroup cpu_kinetis_rtc Kinetis RTC
* @ingroup cpu_kinetis
* @brief Kinetis RTC driver
*
* RTC is clocked by a 32.768 kHz clock.
*
* Please note the manual of your MCU or SiP for the
* clock setting for the RTC module. After initialization
* Time Seconds Register (TSR) increments once a second.
@ -168,16 +171,16 @@
*/
/**
* @defgroup cpu_kinetis_common_spi Kinetis SPI
* @ingroup cpu_kinetis_common
* @brief Kinetis SPI driver for MCUs with Cortex-M4 core.
* @defgroup cpu_kinetis_spi Kinetis SPI
* @ingroup cpu_kinetis
* @brief Kinetis SPI driver
*
* The SPI baud rate and other timings are generated from the bus
* clock via prescalers, the hardware module allows for very
* detailed timing configuration, but a tool exists to generate a
* standard timing configuration for any given module clock frequency.
* The timing configuration tool is found in
* cpu/kinetis_common/dist/calc_spi_scalers
* cpu/kinetis/dist/calc_spi_scalers
*
* Finer tuning of timings than the RIOT SPI API is capable of is
* supported by modifying the generated configuration. See the
@ -203,7 +206,7 @@
* ### SPI configuration example (for periph_conf.h): ###
*
* static const uint32_t spi_clk_config[] = {
* // Use cpu/kinetis_common/dist/calc_spi_scalers to
* // Use cpu/kinetis/dist/calc_spi_scalers to
* // generate the timing configuration
* };
*
@ -244,8 +247,8 @@
*/
/**
* @defgroup cpu_kinetis_common_timer Kinetis Timer
* @ingroup cpu_kinetis_common
* @defgroup cpu_kinetis_timer Kinetis Timer
* @ingroup cpu_kinetis
* @brief Periodic Interrupt Timer (PIT) and Low-Power Timer (LPTMR) driver.
*
* The PIT is a count down timer, in order to use it with riot-os
@ -289,9 +292,10 @@
*/
/**
* @defgroup cpu_kinetis_common_uart Kinetis UART
* @ingroup cpu_kinetis_common
* @brief Kinetis UART driver.
* @defgroup cpu_kinetis_uart Kinetis UART
* @ingroup cpu_kinetis
* @brief Kinetis UART driver
*
* There are different implementations of the UART interface.
* The treatment of interrupts is also slightly different.
* The register UARTx_BDH to UARTx_C4 look almost the same.

2
cpu/kinetis_common/fcfield.c → cpu/kinetis/fcfield.c
View File

@ -8,7 +8,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @{
*
* @file

50
cpu/kinetis/include/cpu_conf.h Normal file
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@ -0,0 +1,50 @@
/*
* Copyright (C) 2017 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_kinetis
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef CPU_CONF_H
#define CPU_CONF_H
/* Dispatch to a separate file per family */
#if defined(KINETIS_SERIES_K)
#include "cpu_conf_kinetis_k.h"
#elif defined(KINETIS_SERIES_L)
#include "cpu_conf_kinetis_l.h"
#elif defined(KINETIS_SERIES_M)
#include "cpu_conf_kinetis_m.h"
#elif defined(KINETIS_SERIES_V)
#include "cpu_conf_kinetis_v.h"
#elif defined(KINETIS_SERIES_W)
#include "cpu_conf_kinetis_w.h"
#endif /* defined(KINETIS_SERIES_x) */
#ifndef MCU_MEM_MAP_VERSION
#error Missing vendor header for the chosen CPU_MODEL
#endif
#include "cpu_conf_kinetis.h"
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_H */
/** @} */

2
cpu/kinetis_common/include/cpu_conf_kinetis.h → cpu/kinetis/include/cpu_conf_kinetis.h
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@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @{
*
* @file

120
cpu/kinetis/include/cpu_conf_kinetis_k.h Normal file
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@ -0,0 +1,120 @@
/*
* Copyright (C) 2017 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_kinetis
* @brief CPU specific implementations for the NXP Kinetis K series of
* Cortex-M MCUs
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef CPU_CONF_KINETIS_K_H
#define CPU_CONF_KINETIS_K_H
#if (KINETIS_FAMILY == 2)
#if (KINETIS_SUBFAMILY == 2)
/* Kinetis K22 */
#if defined(CPU_MODEL_MK22FX512VLH12) || \
defined(CPU_MODEL_MK22FN1M0VLH12) || \
defined(CPU_MODEL_MK22FX512VLK12) || \
defined(CPU_MODEL_MK22FN1M0VLK12) || \
defined(CPU_MODEL_MK22FX512VLL12) || \
defined(CPU_MODEL_MK22FN1M0VLL12) || \
defined(CPU_MODEL_MK22FX512VLQ12) || \
defined(CPU_MODEL_MK22FN1M0VLQ12) || \
defined(CPU_MODEL_MK22FX512VMC12) || \
defined(CPU_MODEL_MK22FN1M0VMC12) || \
defined(CPU_MODEL_MK22FX512VMD12) || \
defined(CPU_MODEL_MK22FN1M0VMD12)
#include "vendor/MK22F12.h"
#elif defined(CPU_MODEL_MK22FN128VDC10) || \
defined(CPU_MODEL_MK22FN128VLH10) || \
defined(CPU_MODEL_MK22FN128VLL10) || \
defined(CPU_MODEL_MK22FN128VMP10)
#include "vendor/MK22F12810.h"
#elif defined(CPU_MODEL_MK22FN128CAH12) || \
defined(CPU_MODEL_MK22FN256CAH12) || \
defined(CPU_MODEL_MK22FN256VDC12) || \
defined(CPU_MODEL_MK22FN256VLH12) || \
defined(CPU_MODEL_MK22FN256VLL12) || \
defined(CPU_MODEL_MK22FN256VMP12)
#include "vendor/MK22F25612.h"
#elif defined(CPU_MODEL_MK22FN512CAP12) || \
defined(CPU_MODEL_MK22FN512VDC12) || \
defined(CPU_MODEL_MK22FN512VFX12) || \
defined(CPU_MODEL_MK22FN512VLH12) || \
defined(CPU_MODEL_MK22FN512VLL12) || \
defined(CPU_MODEL_MK22FN512VMP12)
#include "vendor/MK22F51212.h"
#elif defined(CPU_MODEL_MK22FN1M0AVLH12) || \
defined(CPU_MODEL_MK22FN1M0AVLK12) || \
defined(CPU_MODEL_MK22FN1M0AVLL12) || \
defined(CPU_MODEL_MK22FN1M0AVLQ12) || \
defined(CPU_MODEL_MK22FN1M0AVMC12) || \
defined(CPU_MODEL_MK22FN1M0AVMD12) || \
defined(CPU_MODEL_MK22FX512AVLH12) || \
defined(CPU_MODEL_MK22FX512AVLK12) || \
defined(CPU_MODEL_MK22FX512AVLL12) || \
defined(CPU_MODEL_MK22FX512AVLQ12) || \
defined(CPU_MODEL_MK22FX512AVMC12) || \
defined(CPU_MODEL_MK22FX512AVMD12)
#include "vendor/MK22FA12.h"
#endif
#endif /* (KINETIS_SUBFAMILY == y) */
#elif (KINETIS_FAMILY == 6)
#if (KINETIS_SUBFAMILY == 0)
#if defined(CPU_MODEL_MK60DN256VLL10) || \
defined(CPU_MODEL_MK60DN256VLQ10) || \
defined(CPU_MODEL_MK60DN256VMC10) || \
defined(CPU_MODEL_MK60DN256VMD10) || \
defined(CPU_MODEL_MK60DN512VLL10) || \
defined(CPU_MODEL_MK60DN512VLQ10) || \
defined(CPU_MODEL_MK60DN512VMC10) || \
defined(CPU_MODEL_MK60DN512VMD10) || \
defined(CPU_MODEL_MK60DX256VLL10) || \
defined(CPU_MODEL_MK60DX256VLQ10) || \
defined(CPU_MODEL_MK60DX256VMC10) || \
defined(CPU_MODEL_MK60DX256VMD10)
#include "vendor/MK60D10.h"
#endif
/**
* @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
*/
#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
#elif (KINETIS_SUBFAMILY == 4)
#if defined(CPU_MODEL_MK64FN1M0CAJ12) || \
defined(CPU_MODEL_MK64FN1M0VDC12) || \
defined(CPU_MODEL_MK64FN1M0VLL12) || \
defined(CPU_MODEL_MK64FN1M0VLQ12) || \
defined(CPU_MODEL_MK64FN1M0VMD12) || \
defined(CPU_MODEL_MK64FX512VDC12) || \
defined(CPU_MODEL_MK64FX512VLL12) || \
defined(CPU_MODEL_MK64FX512VLQ12) || \
defined(CPU_MODEL_MK64FX512VMD12)
#include "vendor/MK64F12.h"
#endif
#endif /* (KINETIS_SUBFAMILY == y) */
#endif /* (KINETIS_FAMILY == x) */
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_KINETIS_K_H */
/** @} */

25
cpu/k22f/include/cpu_conf.h → cpu/kinetis/include/cpu_conf_kinetis_l.h
View File

@ -7,10 +7,9 @@
*/
/**
* @defgroup cpu_k22f NXP Kinetis K22F
* @ingroup cpu
* @brief CPU specific implementations for the NXP Kinetis K22F
* Cortex-M4 MCU
* @ingroup cpu_kinetis
* @brief CPU specific implementations for the NXP Kinetis L series of
* Cortex-M MCUs
* @{
*
* @file
@ -19,16 +18,14 @@
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef CPU_CONF_H
#define CPU_CONF_H
#ifndef CPU_CONF_KINETIS_L_H
#define CPU_CONF_KINETIS_L_H
#ifdef CPU_MODEL_MK22FN512VLH12
#include "vendor/MK22F51212.h"
#else
#error "undefined CPU_MODEL"
#endif
#include "cpu_conf_kinetis.h"
#if (KINETIS_FAMILY == 2)
#if (KINETIS_SUBFAMILY == 2)
/* Put your vendor includes here */
#endif /* (KINETIS_SUBFAMILY == y) */
#endif /* (KINETIS_FAMILY == x) */
#ifdef __cplusplus
extern "C"
@ -39,5 +36,5 @@ extern "C"
}
#endif
#endif /* CPU_CONF_H */
#endif /* CPU_CONF_KINETIS_L_H */
/** @} */

40
cpu/kinetis/include/cpu_conf_kinetis_m.h Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (C) 2017 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_kinetis
* @brief CPU specific implementations for the NXP Kinetis M series of
* Cortex-M MCUs
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef CPU_CONF_KINETIS_M_H
#define CPU_CONF_KINETIS_M_H
#if (KINETIS_FAMILY == 2)
#if (KINETIS_SUBFAMILY == 2)
/* Put your vendor includes here */
#endif /* (KINETIS_SUBFAMILY == y) */
#endif /* (KINETIS_FAMILY == x) */
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_KINETIS_M_H */
/** @} */

40
cpu/kinetis/include/cpu_conf_kinetis_v.h Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (C) 2017 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_kinetis
* @brief CPU specific implementations for the NXP Kinetis V series of
* Cortex-M MCUs
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef CPU_CONF_KINETIS_V_H
#define CPU_CONF_KINETIS_V_H
#if (KINETIS_FAMILY == 2)
#if (KINETIS_SUBFAMILY == 2)
/* Put your vendor includes here */
#endif /* (KINETIS_SUBFAMILY == y) */
#endif /* (KINETIS_FAMILY == x) */
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_KINETIS_V_H */
/** @} */

79
cpu/kinetis/include/cpu_conf_kinetis_w.h Normal file
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@ -0,0 +1,79 @@
/*
* Copyright (C) 2017 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_kinetis
* @brief CPU specific implementations for the NXP Kinetis K series of
* Cortex-M MCUs
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
*/
#ifndef CPU_CONF_KINETIS_W_H
#define CPU_CONF_KINETIS_W_H
#if defined(KINETIS_CORE_D)
/* Kinetis KW2xD */
#if defined(CPU_MODEL_MKW21D256VHA5) || \
defined(CPU_MODEL_MKW21D512VHA5)
#include "vendor/MKW21D5.h"
#elif defined(CPU_MODEL_MKW22D512VHA5)
#include "vendor/MKW22D5.h"
#elif defined(CPU_MODEL_MKW24D512VHA5)
#include "vendor/MKW24D5.h"
#endif
/**
* @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
*/
#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
/**
* @name KW2XD SiP internal interconnects between MCU and radio
*
* @{
*/
#define KW2XDRF_PORT_DEV PORTB /**< MCU Port connected to radio*/
#define KW2XDRF_PORT PORT_B /**< MCU Port connected to radio*/
#define KW2XDRF_GPIO GPIOB /**< GPIO Device connected to radio */
#define KW2XDRF_PORT_IRQn PORTB_IRQn
/** Clock Enable for PORTB */
#define KW2XDRF_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define KW2XDRF_PIN_AF 2 /**< Pin Muxing Parameter for GPIO Device*/
#define KW2XDRF_PCS0_PIN 10 /**< Radio SPI chip select pin */
#define KW2XDRF_SCK_PIN 11 /**< Radio SPI clock pin */
#define KW2XDRF_SOUT_PIN 16 /**< Radio SPI MOSI pin */
#define KW2XDRF_SIN_PIN 17 /**< Radio SPI MISO pin */
#define KW2XDRF_RST_PIN 19 /**< Radio reset pin */
#define KW2XDRF_IRQ_PIN 3 /**< radio IRQ pin (active low) */
#define KW2XDRF_CLK_CTRL_PORT PORT_C /**< CLK_OUT control pin port */
#define KW2XDRF_CLK_CTRL_PORT_DEV PORTC /**< CLK_OUT control pin PORT device */
#define KW2XDRF_CLK_CTRL_GPIO GPIOC /**< CLK_OUT control pin GPIO device */
#define KW2XDRF_CLK_CTRL_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define KW2XDRF_CLK_CTRL_PIN 0 /**< CLK_OUT control pin */
/** @} */
#elif defined(KINETIS_CORE_Z)
/* Kinetis KWxxZ */
/* TODO */
#endif /* KINETIS_CORE_x */
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_KINETIS_W_H */
/** @} */

4
cpu/kinetis_common/include/mcg.h → cpu/kinetis/include/mcg.h
View File

@ -8,8 +8,8 @@
*/
/**
* @defgroup cpu_kinetis_common_mcg Kinetis MCG
* @ingroup cpu_kinetis_common
* @defgroup cpu_kinetis_mcg Kinetis MCG
* @ingroup cpu_kinetis
* @brief Implementation of the Kinetis Multipurpose Clock Generator
* (MCG) driver
*

2
cpu/kinetis_common/include/periph_cpu.h → cpu/kinetis/include/periph_cpu.h
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@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @{
*
* @file

0
cpu/kinetis_common/include/vectors_kinetis.h → cpu/kinetis/include/vectors_kinetis.h
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0
cpu/k22f/include/vendor/MK22F12.h → cpu/kinetis/include/vendor/MK22F12.h vendored
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0
cpu/k22f/include/vendor/MK22F12810.h → cpu/kinetis/include/vendor/MK22F12810.h vendored
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0
cpu/k22f/include/vendor/MK22F25612.h → cpu/kinetis/include/vendor/MK22F25612.h vendored
View File

0
cpu/k22f/include/vendor/MK22F51212.h → cpu/kinetis/include/vendor/MK22F51212.h vendored
View File

0
cpu/k22f/include/vendor/MK22FA12.h → cpu/kinetis/include/vendor/MK22FA12.h vendored
View File

0
cpu/k60/include/vendor/MK60D10.h → cpu/kinetis/include/vendor/MK60D10.h vendored
View File

0
cpu/k64f/include/vendor/MK64F12.h → cpu/kinetis/include/vendor/MK64F12.h vendored
View File

0
cpu/kw2xd/include/vendor/MKW21D5.h → cpu/kinetis/include/vendor/MKW21D5.h vendored
View File

0
cpu/kw2xd/include/vendor/MKW22D5.h → cpu/kinetis/include/vendor/MKW22D5.h vendored
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0
cpu/kw2xd/include/vendor/MKW24D5.h → cpu/kinetis/include/vendor/MKW24D5.h vendored
View File

4
cpu/kinetis_common/include/wdog.h → cpu/kinetis/include/wdog.h
View File

@ -8,8 +8,8 @@
*/
/**
* @defgroup cpu_kinetis_common_wdog Kinetis WDOG
* @ingroup cpu_kinetis_common
* @defgroup cpu_kinetis_wdog Kinetis WDOG
* @ingroup cpu_kinetis
* @brief Driver for Freescale WDOG device.
* There are different implementations of the Watchdog devices.
* Currently, it is only possible to turn the Watchdog off.

2
cpu/kinetis_common/isr_kinetis.c → cpu/kinetis/isr_kinetis.c
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@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @{
*
* @file

0
cpu/kinetis_common/kinetis-info.mk → cpu/kinetis/kinetis-info.mk
View File

0
cpu/kinetis_common/ldscripts/kinetis.ld → cpu/kinetis/ldscripts/kinetis.ld
View File

0
cpu/k22f/periph/Makefile → cpu/kinetis/periph/Makefile
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2
cpu/kinetis_common/periph/adc.c → cpu/kinetis/periph/adc.c
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_adc
* @{
*

2
cpu/kinetis_common/periph/dac.c → cpu/kinetis/periph/dac.c
View File

@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_dac
*
* @{

2
cpu/kinetis_common/periph/gpio.c → cpu/kinetis/periph/gpio.c
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_gpio
*
* @{

2
cpu/kinetis_common/periph/hwrng.c → cpu/kinetis/periph/hwrng.c
View File

@ -8,7 +8,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_hwng
*
* @{

0
cpu/kinetis_common/periph/i2c.c → cpu/kinetis/periph/i2c.c
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2
cpu/kinetis_common/periph/mcg.c → cpu/kinetis/periph/mcg.c
View File

@ -8,7 +8,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_mcg
* @{
*

2
cpu/kinetis_common/periph/pm.c → cpu/kinetis/periph/pm.c
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_pm
* @{
*

2
cpu/kinetis_common/periph/pwm.c → cpu/kinetis/periph/pwm.c
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_pwm
*
* @{

2
cpu/kinetis_common/periph/rtc.c → cpu/kinetis/periph/rtc.c
View File

@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_rtc
*
* @{

2
cpu/kinetis_common/periph/rtt.c → cpu/kinetis/periph/rtt.c
View File

@ -8,7 +8,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_rtt
*
* @{

2
cpu/kinetis_common/periph/spi.c → cpu/kinetis/periph/spi.c
View File

@ -10,7 +10,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_spi
*
* @{

2
cpu/kinetis_common/periph/timer.c → cpu/kinetis/periph/timer.c
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_timer
*
* @{

2
cpu/kinetis_common/periph/uart.c → cpu/kinetis/periph/uart.c
View File

@ -9,7 +9,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_uart
*
* @{

2
cpu/kinetis_common/periph/wdog.c → cpu/kinetis/periph/wdog.c
View File

@ -8,7 +8,7 @@
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup cpu_kinetis
* @ingroup drivers_periph_watchdog
*
* @{

0
cpu/kinetis_common/vectors.c → cpu/kinetis/vectors.c
View File

9
cpu/kinetis_common/Makefile
View File

@ -1,9 +0,0 @@
# define the module that is build
MODULE = kinetis_common
DIRS += periph
# (file triggers compiler bug. see #5775)
SRC_NOLTO += vectors.c
include $(RIOTBASE)/Makefile.base

4
cpu/kinetis_common/Makefile.features
View File

@ -1,4 +0,0 @@
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_hwrng
-include $(RIOTCPU)/cortexm_common/Makefile.features

3
cpu/kinetis_common/periph/Makefile
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@ -1,3 +0,0 @@
MODULE = kinetis_common_periph
include $(RIOTMAKE)/periph.mk

73
cpu/kinetis_common/periph/hwrng_rngb.c
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@ -1,73 +0,0 @@
/*
* Copyright (C) 2014-2016 Freie Universität Berlin
* Copyright (C) 2014 PHYTEC Messtechnik GmbH
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_kinetis_common
* @ingroup drivers_periph_hwng
* @{
*
* @file
* @brief HWRNG interface implementation
*
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se> (adaption for Freescale's RNGB)
* @author Johann Fischer <j.fischer@phytec.de> (adaption for Freescale's RNGA)
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "periph/hwrng.h"
#include "periph_conf.h"
#ifdef KINETIS_RNGB
void hwrng_init(void)
{
/* nothing to be done here */
}
void hwrng_read(void *buf, unsigned int num)
{
unsigned int count = 0;
uint8_t *b = (uint8_t *)buf;
HWRNG_CLKEN();
if ((KINETIS_RNGB->VER & RNG_VER_TYPE_MASK) != 0b0001) {
/* Wrong type of RNG */
/* TODO: Handle */
}
/* Software reset, bit is self-clearing */
BITBAND_REG32(KINETIS_RNGB->CMD, RNG_CMD_SR_SHIFT) = 1;
/* Set up automatic reseed */
KINETIS_RNGB->CR = RNG_CR_AR_MASK | RNG_CR_MASKERR_MASK | RNG_CR_MASKDONE_MASK;
while (count < num) {
uint32_t tmp;
/* wait for random data to be ready to read */
while (!(KINETIS_RNGB->SR & RNG_SR_FIFO_LVL_MASK));
tmp = KINETIS_RNGB->OUT;
/* copy data into result vector */
for (int i = 0; i < 4 && count < num; i++) {
b[count++] = (uint8_t)tmp;
tmp = tmp >> 8;
}
}
KINETIS_RNGB->CR = 0;
HWRNG_CLKDIS();
}
#endif /* KINETIS_RNGB */

7
cpu/kw2xd/Makefile
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@ -1,7 +0,0 @@
# define the module that is build
MODULE = cpu
# add a list of subdirectories, that should also be build
DIRS = periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON)
include $(RIOTBASE)/Makefile.base

1
cpu/kw2xd/Makefile.dep
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@ -1 +0,0 @@
-include $(RIOTCPU)/kinetis_common/Makefile.dep

1
cpu/kw2xd/Makefile.features
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@ -1 +0,0 @@
-include $(RIOTCPU)/kinetis_common/Makefile.features

20
cpu/kw2xd/Makefile.include
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@ -1,20 +0,0 @@
# define the CPU architecture for the kw2xd
export CPU_ARCH = cortex-m4
# map CPU models to generic Kinetis linkerscript
LD_KW21D256 = kinetis_f256l16u16.ld
LD_KW21D512 = kinetis_f512l32u32.ld
LD_KW22D512 = kinetis_f512l32u32.ld
# tell the build system that the CPU depends on the Kinetis common files
export USEMODULE += kinetis_common
# define path to kinetis module, which is needed for this CPU
export KINETIS_COMMON = $(RIOTCPU)/kinetis_common/
# CPU depends on the kinetis module, so include it
include $(KINETIS_COMMON)Makefile.include
# this CPU implementation is using kinetis common startup
export COMMON_STARTUP = $(KINETIS_COMMON)
include $(RIOTMAKE)/arch/cortexm.inc.mk

94
cpu/kw2xd/include/cpu_conf.h
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@ -1,94 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2014 PHYTEC Messtechnik GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup cpu_kw2xd NXP Kinetis KW2xD
* @ingroup cpu
* @brief CPU specific implementations for the NXP Kinetis KW2xD SiP
*
* The SiP incorporates a low power 2.4 GHz transceiver, and a
* Kinetis Cortex-M4 MCU.
*
* From the register map and functional description it seems
* like the transceiver is a close relative of the NXP MCR20A.
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Johann Fischer <j.fischer@phytec.de>
*/
#ifndef CPU_CONF_H
#define CPU_CONF_H
#ifdef CPU_MODEL_KW21D256
#include "vendor/MKW22D5.h"
#elif CPU_MODEL_KW21D512
#include "vendor/MKW22D5.h"
#elif CPU_MODEL_KW22D512
#include "vendor/MKW22D5.h"
#else
#error "undefined CPU_MODEL"
#endif
#include "cpu_conf_kinetis.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
*/
#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
/** @name PORT module clock gates */
/** @{ */
#define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
#define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
#define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
#define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
#define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
/** @} */
/**
* @name KW2XD SiP internal interconnects between MCU and Modem.
*
* @{
*/
#define KW2XDRF_PORT_DEV PORTB /**< MCU Port connected to Modem*/
#define KW2XDRF_PORT PORT_B /**< MCU Port connected to Modem*/
#define KW2XDRF_GPIO GPIOB /**< GPIO Device connected to Modem */
#define KW2XDRF_PORT_IRQn PORTB_IRQn
/** Clock Enable for PORTB*/
#define KW2XDRF_PORT_CLKEN() (PORTB_CLOCK_GATE = 1)
#define KW2XDRF_PIN_AF 2 /**< Pin Muxing Parameter for GPIO Device*/
#define KW2XDRF_PCS0_PIN 10 /**< SPI Slave Select Pin */
#define KW2XDRF_SCK_PIN 11 /**< SPI Clock Output Pin */
#define KW2XDRF_SOUT_PIN 16 /**< SPI Master Data Output Pin */
#define KW2XDRF_SIN_PIN 17 /**< SPI Master Data Input Pin */
#define KW2XDRF_RST_PIN 19 /**< Reset pin */
#define KW2XDRF_IRQ_PIN 3 /**< Modem's IRQ Output (activ low) */
#define KW2XDRF_CLK_CTRL_PORT PORT_C /**< CLK_OUT control pin port */
#define KW2XDRF_CLK_CTRL_PORT_DEV PORTC /**< CLK_OUT control pin PORT device */
#define KW2XDRF_CLK_CTRL_GPIO GPIOC /**< CLK_OUT control pin GPIO device */
#define KW2XDRF_CLK_CTRL_CLKEN() (PORTC_CLOCK_GATE = 1)
#define KW2XDRF_CLK_CTRL_PIN 0 /**< CLK_OUT control pin */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_H */
/** @} */

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cpu/kw2xd/periph/Makefile
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include $(RIOTMAKE)/periph.mk

2
doc/doxygen/src/mainpage.md
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@ -150,7 +150,7 @@ CPUs share the same code for task switching and interrupt handling). This
shared code is put in its own directories, following a `xxxxx_common` naming
scheme. Examples for this is code shared across architectures (e.g.
`cortexm_common`, `msp430_comon`) or code shared among vendors (e.g.
`kinetis_common`).
`stm32_common`).
See @ref cpu for more detailed informtation.