From 95ec5890b0fef801757f77054cd5a6aca9999774 Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benpicco@googlemail.com>
Date: Tue, 14 Jul 2020 22:33:30 +0200
Subject: [PATCH 01/11] cortexm_common: fix bit-banding check
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Not all MCUs ≥ Cortex-M3 provide the Bit-Banding feature.
It is up to the manufacturer to implement it.

Instead, rely on the CPU_HAS_BITBAND being set in `periph_cpu.h`.
---
 cpu/cortexm_common/include/bit.h | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/cpu/cortexm_common/include/bit.h b/cpu/cortexm_common/include/bit.h
index a4c34ac7d9..52513e6a1c 100644
--- a/cpu/cortexm_common/include/bit.h
+++ b/cpu/cortexm_common/include/bit.h
@@ -35,16 +35,8 @@ extern "C" {
 #define CPU_HAS_BITBAND 1 || 0 (1 for Cortex-M3 and up, 0 for Cortex-M0)
 #endif
 
-#ifndef CPU_HAS_BITBAND
-#if (__CORTEX_M >= 3)
-#define CPU_HAS_BITBAND 1
-#else
-#define CPU_HAS_BITBAND 0
-#endif
-#endif
-
 #if CPU_HAS_BITBAND || DOXYGEN
-/* Cortex-M3 and higher provide a bitband address space for atomically accessing
+/* Some MCUs provide a bitband address space for atomically accessing
  * single bits of peripheral registers, and sometimes for RAM as well */
 /**
  * @name Bit manipulation functions

From b716419462f2fa49c6cefcddcd375b3d4bbe482f Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benpicco@googlemail.com>
Date: Tue, 14 Jul 2020 22:35:04 +0200
Subject: [PATCH 02/11] cpu/efm32: set CPU_HAS_BITBAND

---
 cpu/efm32/include/cpu_conf.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/cpu/efm32/include/cpu_conf.h b/cpu/efm32/include/cpu_conf.h
index b4ee8b8ebb..e6427b0d82 100644
--- a/cpu/efm32/include/cpu_conf.h
+++ b/cpu/efm32/include/cpu_conf.h
@@ -51,6 +51,15 @@ extern "C" {
 #define FLASHPAGE_RAW_ALIGNMENT    (4U)
 /** @} */
 
+/**
+ * @brief   Bit-Band configuration
+ * @{
+ */
+#ifdef BITBAND_RAM_BASE
+#define CPU_HAS_BITBAND 1
+#endif
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

From 8f36c88b93f8fd725579fcb7fc443fc2a1a0b158 Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benpicco@googlemail.com>
Date: Tue, 14 Jul 2020 22:35:22 +0200
Subject: [PATCH 03/11] cpu/stm32: set CPU_HAS_BITBAND

---
 cpu/stm32/include/cpu_conf.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/cpu/stm32/include/cpu_conf.h b/cpu/stm32/include/cpu_conf.h
index e29ae25305..40e13f05f3 100644
--- a/cpu/stm32/include/cpu_conf.h
+++ b/cpu/stm32/include/cpu_conf.h
@@ -167,6 +167,15 @@ extern "C" {
 #endif
 /** @} */
 
+/**
+ * @brief   Bit-Band configuration
+ * @{
+ */
+#ifdef SRAM_BB_BASE
+#define CPU_HAS_BITBAND 1
+#endif
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

From f53ae74269346fc867de25c8584f157aa79d4a3d Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benpicco@googlemail.com>
Date: Tue, 14 Jul 2020 22:35:56 +0200
Subject: [PATCH 04/11] cpu/kinetis: set CPU_HAS_BITBAND

---
 cpu/kinetis/include/cpu_conf.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/cpu/kinetis/include/cpu_conf.h b/cpu/kinetis/include/cpu_conf.h
index 6aefecdc1e..f92fe6d3d0 100644
--- a/cpu/kinetis/include/cpu_conf.h
+++ b/cpu/kinetis/include/cpu_conf.h
@@ -44,6 +44,15 @@ extern "C"
 {
 #endif
 
+/**
+ * @brief   Bit-Band configuration
+ * @{
+ */
+#ifdef BITBAND_REG32
+#define CPU_HAS_BITBAND 1
+#endif
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

From 69c436b891efdb6998310bab687a9dffab7da160 Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benpicco@googlemail.com>
Date: Tue, 14 Jul 2020 22:36:15 +0200
Subject: [PATCH 05/11] cpu/ezr32wg: set CPU_HAS_BITBAND

---
 cpu/ezr32wg/include/cpu_conf.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/cpu/ezr32wg/include/cpu_conf.h b/cpu/ezr32wg/include/cpu_conf.h
index febf214b58..a27a63f6fb 100644
--- a/cpu/ezr32wg/include/cpu_conf.h
+++ b/cpu/ezr32wg/include/cpu_conf.h
@@ -42,6 +42,15 @@ extern "C" {
 #define CPU_FLASH_BASE                  FLASH_BASE
 /** @} */
 
+/**
+ * @brief   Bit-Band configuration
+ * @{
+ */
+#ifdef BITBAND_RAM_BASE
+#define CPU_HAS_BITBAND 1
+#endif
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

From b8d49fe6277d519c95d3e138fd61f15aa3c70644 Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Date: Fri, 7 Aug 2020 17:42:25 +0200
Subject: [PATCH 06/11] cpu/cc2538: set CPU_HAS_BITBAND

---
 cpu/cc2538/include/cpu_conf.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cpu/cc2538/include/cpu_conf.h b/cpu/cc2538/include/cpu_conf.h
index eb9fc3b103..27eaaf2647 100644
--- a/cpu/cc2538/include/cpu_conf.h
+++ b/cpu/cc2538/include/cpu_conf.h
@@ -40,6 +40,7 @@ extern "C" {
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
 #define CPU_IRQ_NUMOF                   PERIPH_COUNT_IRQn
 #define CPU_FLASH_BASE                  FLASH_BASE
+#define CPU_HAS_BITBAND                 (1)
 /** @} */
 
 #ifdef __cplusplus

From 098b37a7dcab86e562add01071678e9fc4a74dda Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Date: Fri, 7 Aug 2020 17:46:08 +0200
Subject: [PATCH 07/11] cpu/cc26x2_cc13x2: set CPU_HAS_BITBAND

> Bit-banding is supported in order to reduce the execution time for
> read-modify-write (RMW) operations to memory.
> With bit-banding, certain regions in the memory map
> (SRAM and peripheral space) can use address aliases to access
> individual bits in one atomic operation.

https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf
---
 cpu/cc26x2_cc13x2/include/cpu_conf.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/cpu/cc26x2_cc13x2/include/cpu_conf.h b/cpu/cc26x2_cc13x2/include/cpu_conf.h
index 40bf1e6125..f3d779da33 100644
--- a/cpu/cc26x2_cc13x2/include/cpu_conf.h
+++ b/cpu/cc26x2_cc13x2/include/cpu_conf.h
@@ -29,6 +29,11 @@
 #include "cc26x2_cc13x2_prcm.h"
 #include "cc26x2_cc13x2_setup.h"
 
+/**
+ * @brief   Bit-Band configuration
+ */
+#define CPU_HAS_BITBAND 1
+
 #ifdef __cplusplus
 extern "C" {
 #endif

From fae0b0091878bba96f106455c3337227e9f68725 Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Date: Fri, 7 Aug 2020 17:53:28 +0200
Subject: [PATCH 08/11] cpu/cc26x0: set CPU_HAS_BITBAND

> Bit-banding is supported in order to reduce the execution time for
> read-modify-write (RMW) operations to memory.
> With bit-banding, certain regions in the memory map
> (SRAM and peripheral space) can use address aliases to access
> individual bits in one atomic operation.

https://www.ti.com/lit/ug/swcu117i/swcu117i.pdf
---
 cpu/cc26x0/include/cpu_conf.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/cpu/cc26x0/include/cpu_conf.h b/cpu/cc26x0/include/cpu_conf.h
index d2f54a9174..661b545c40 100644
--- a/cpu/cc26x0/include/cpu_conf.h
+++ b/cpu/cc26x0/include/cpu_conf.h
@@ -27,6 +27,11 @@
 #include "cc26x0_fcfg.h"
 #include "cc26x0_prcm.h"
 
+/**
+ * @brief   Bit-Band configuration
+ */
+#define CPU_HAS_BITBAND 1
+
 #ifdef __cplusplus
 extern "C" {
 #endif

From 225f56b5e612d430155fec227ea05daa60e3fba2 Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Date: Fri, 7 Aug 2020 17:57:37 +0200
Subject: [PATCH 09/11] cpu/lm4f120: set CPU_HAS_BITBAND

> A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
> The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. A

https://www.mouser.com/datasheet/2/405/lm4f120h5qr-124014.pdf
---
 cpu/lm4f120/include/cpu_conf.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cpu/lm4f120/include/cpu_conf.h b/cpu/lm4f120/include/cpu_conf.h
index 1875501310..fc84c55f83 100644
--- a/cpu/lm4f120/include/cpu_conf.h
+++ b/cpu/lm4f120/include/cpu_conf.h
@@ -58,6 +58,7 @@ extern "C" {
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
 #define CPU_IRQ_NUMOF                   (139U)
 #define CPU_FLASH_BASE                  FLASH_BASE
+#define CPU_HAS_BITBAND                 (1)
 /** @} */
 
 /**

From e886dad430dbf06f7d4fa9b03a7017bee9b76f87 Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Date: Fri, 7 Aug 2020 18:02:16 +0200
Subject: [PATCH 10/11] cpu/lpc1768: set CPU_HAS_BITBAND

> Support for Cortex-M3 bit banding.

https://www.nxp.com/docs/en/data-sheet/LPC1769_68_67_66_65_64_63.pdf
---
 cpu/lpc1768/include/cpu_conf.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cpu/lpc1768/include/cpu_conf.h b/cpu/lpc1768/include/cpu_conf.h
index c9ce1e67d1..ae0814a9b8 100644
--- a/cpu/lpc1768/include/cpu_conf.h
+++ b/cpu/lpc1768/include/cpu_conf.h
@@ -36,6 +36,7 @@ extern "C" {
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
 #define CPU_IRQ_NUMOF                   (35U)
 #define CPU_FLASH_BASE                  LPC_FLASH_BASE
+#define CPU_HAS_BITBAND                 (1)
 /** @} */
 
 /**

From 0e22910c946d6ad4d47e858640b5ccfaabfaa54b Mon Sep 17 00:00:00 2001
From: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Date: Fri, 7 Aug 2020 18:06:26 +0200
Subject: [PATCH 11/11] cpu/sam_common: set CPU_HAS_BITBAND

- https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf
- http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11100-32-bit%20Cortex-M4-Microcontroller-SAM4S_Datasheet.pdf
---
 cpu/sam_common/include/cpu_conf.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cpu/sam_common/include/cpu_conf.h b/cpu/sam_common/include/cpu_conf.h
index b1dc8c926c..8aae7203dc 100644
--- a/cpu/sam_common/include/cpu_conf.h
+++ b/cpu/sam_common/include/cpu_conf.h
@@ -34,6 +34,7 @@ extern "C" {
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
 #define CPU_IRQ_NUMOF                   PERIPH_COUNT_IRQn
 #define CPU_FLASH_BASE                  IFLASH0_ADDR
+#define CPU_HAS_BITBAND                 (1)
 /** @} */
 
 #ifdef __cplusplus