diff --git a/cpu/cortexm_common/cortexm_init.c b/cpu/cortexm_common/cortexm_init.c index dccee08e79..73bd40c4d7 100644 --- a/cpu/cortexm_common/cortexm_init.c +++ b/cpu/cortexm_common/cortexm_init.c @@ -46,7 +46,7 @@ void cortexm_init(void) /* set SVC interrupt to same priority as the rest */ NVIC_SetPriority(SVCall_IRQn, CPU_DEFAULT_IRQ_PRIO); /* initialize all vendor specific interrupts with the same value */ - for (int i = 0; i < (int)CPU_IRQ_NUMOF; i++) { + for (unsigned i = 0; i < CPU_IRQ_NUMOF; i++) { NVIC_SetPriority((IRQn_Type) i, CPU_DEFAULT_IRQ_PRIO); } diff --git a/cpu/cortexm_common/include/vectors_cortexm.h b/cpu/cortexm_common/include/vectors_cortexm.h index bbbe2908c1..c4aa4bb05a 100644 --- a/cpu/cortexm_common/include/vectors_cortexm.h +++ b/cpu/cortexm_common/include/vectors_cortexm.h @@ -34,6 +34,14 @@ extern "C" { */ #define ISR_VECTORS __attribute__((used,section(".vectors"))) +/** + * @brief Number of Cortex-M non-ISR exceptions + * + * This means those that are no hardware interrupts, or the ones with a + * negative interrupt number. + */ +#define CPU_NONISR_EXCEPTIONS (15) + /** * @brief This function is the default entry point after a system reset * diff --git a/cpu/samd21/periph/gpio.c b/cpu/samd21/periph/gpio.c index 80e31f0162..e9d58d8cce 100644 --- a/cpu/samd21/periph/gpio.c +++ b/cpu/samd21/periph/gpio.c @@ -212,7 +212,7 @@ void gpio_write(gpio_t pin, int value) void isr_eic(void) { - for (int i = 0; i < NUMOF_IRQS; i++) { + for (unsigned i = 0; i < NUMOF_IRQS; i++) { if (EIC->INTFLAG.reg & (1 << i)) { EIC->INTFLAG.reg = (1 << i); if(EIC->INTENSET.reg & (1 << i)) { diff --git a/cpu/samd21/periph/spi.c b/cpu/samd21/periph/spi.c index 58ccc90a7e..f7eef079f6 100644 --- a/cpu/samd21/periph/spi.c +++ b/cpu/samd21/periph/spi.c @@ -208,13 +208,20 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed) int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char)) { + (void)dev; + (void)conf; + (void)cb; /* TODO */ + assert(false); return -1; } void spi_transmission_begin(spi_t dev, char reset_val) { - /* TODO*/ + (void)dev; + (void)reset_val; + /* TODO */ + assert(false); } int spi_acquire(spi_t dev) diff --git a/cpu/samd21/vectors.c b/cpu/samd21/vectors.c index 71b2fcc8f1..1675fd3b0e 100644 --- a/cpu/samd21/vectors.c +++ b/cpu/samd21/vectors.c @@ -20,6 +20,8 @@ */ #include + +#include "cpu_conf.h" #include "vectors_cortexm.h" /* get the start of the ISR stack as defined in the linkerscript */ @@ -66,54 +68,59 @@ WEAK_DEFAULT void isr_ptc(void); WEAK_DEFAULT void isr_i2c(void); /* interrupt vector table */ -ISR_VECTORS const void *interrupt_vector[] = { +ISR_VECTORS struct { + void* _estack; + void(*vectors[CPU_IRQ_NUMOF + CPU_NONISR_EXCEPTIONS])(void); +} interrupt_vector = { /* Exception stack pointer */ - (void*) (&_estack), /* pointer to the top of the stack */ - /* Cortex-M0+ handlers */ - (void*) reset_handler_default, /* entry point of the program */ - (void*) nmi_default, /* non maskable interrupt handler */ - (void*) hard_fault_default, /* hard fault exception */ - (void*) (0UL), /* reserved */ - (void*) (0UL), /* reserved */ - (void*) (0UL), /* reserved */ - (void*) (0UL), /* reserved */ - (void*) (0UL), /* reserved */ - (void*) (0UL), /* reserved */ - (void*) (0UL), /* reserved */ - (void*) isr_svc, /* system call interrupt, in RIOT used for - * switching into thread context on boot */ - (void*) (0UL), /* reserved */ - (void*) (0UL), /* reserved */ - (void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual - * context switching is happening here */ - (void*) isr_systick, /* SysTick interrupt, not used in RIOT */ - /* Atmel specific peripheral handlers */ - (void*) isr_pm, /* 0 Power Manager */ - (void*) isr_sysctrl, /* 1 System Control */ - (void*) isr_wdt, /* 2 Watchdog Timer */ - (void*) isr_rtc, /* 3 Real-Time Counter */ - (void*) isr_eic, /* 4 External Interrupt Controller */ - (void*) isr_nvmctrl, /* 5 Non-Volatile Memory Controller */ - (void*) isr_dmac, /* 6 Direct Memory Access Controller */ - (void*) isr_usb, /* 7 Universal Serial Bus */ - (void*) isr_evsys, /* 8 Event System Interface */ - (void*) isr_sercom0, /* 9 Serial Communication Interface 0 */ - (void*) isr_sercom1, /* 10 Serial Communication Interface 1 */ - (void*) isr_sercom2, /* 11 Serial Communication Interface 2 */ - (void*) isr_sercom3, /* 12 Serial Communication Interface 3 */ - (void*) isr_sercom4, /* 13 Serial Communication Interface 4 */ - (void*) isr_sercom5, /* 14 Serial Communication Interface 5 */ - (void*) isr_tcc0, /* 15 Timer Counter Control 0 */ - (void*) isr_tcc1, /* 16 Timer Counter Control 1 */ - (void*) isr_tcc2, /* 17 Timer Counter Control 2 */ - (void*) isr_tc3, /* 18 Basic Timer Counter 0 */ - (void*) isr_tc4, /* 19 Basic Timer Counter 1 */ - (void*) isr_tc5, /* 20 Basic Timer Counter 2 */ - (void*) isr_tc6, /* 21 Basic Timer Counter 3 */ - (void*) isr_tc7, /* 22 Basic Timer Counter 4 */ - (void*) isr_adc, /* 23 Analog Digital Converter */ - (void*) isr_ac, /* 24 Analog Comparators */ - (void*) isr_dac, /* 25 Digital Analog Converter */ - (void*) isr_ptc, /* 26 Peripheral Touch Controller */ - (void*) isr_i2c /* 27 Inter-IC Sound Interface */ + &_estack, /* pointer to the top of the stack */ + { + /* Cortex-M0+ handlers */ + reset_handler_default, /* entry point of the program */ + nmi_default, /* non maskable interrupt handler */ + hard_fault_default, /* hard fault exception */ + (0UL), /* reserved */ + (0UL), /* reserved */ + (0UL), /* reserved */ + (0UL), /* reserved */ + (0UL), /* reserved */ + (0UL), /* reserved */ + (0UL), /* reserved */ + isr_svc, /* system call interrupt, in RIOT used for + * switching into thread context on boot */ + (0UL), /* reserved */ + (0UL), /* reserved */ + isr_pendsv, /* pendSV interrupt, in RIOT the actual + * context switching is happening here */ + isr_systick, /* SysTick interrupt, not used in RIOT */ + /* Atmel specific peripheral handlers */ + isr_pm, /* 0 Power Manager */ + isr_sysctrl, /* 1 System Control */ + isr_wdt, /* 2 Watchdog Timer */ + isr_rtc, /* 3 Real-Time Counter */ + isr_eic, /* 4 External Interrupt Controller */ + isr_nvmctrl, /* 5 Non-Volatile Memory Controller */ + isr_dmac, /* 6 Direct Memory Access Controller */ + isr_usb, /* 7 Universal Serial Bus */ + isr_evsys, /* 8 Event System Interface */ + isr_sercom0, /* 9 Serial Communication Interface 0 */ + isr_sercom1, /* 10 Serial Communication Interface 1 */ + isr_sercom2, /* 11 Serial Communication Interface 2 */ + isr_sercom3, /* 12 Serial Communication Interface 3 */ + isr_sercom4, /* 13 Serial Communication Interface 4 */ + isr_sercom5, /* 14 Serial Communication Interface 5 */ + isr_tcc0, /* 15 Timer Counter Control 0 */ + isr_tcc1, /* 16 Timer Counter Control 1 */ + isr_tcc2, /* 17 Timer Counter Control 2 */ + isr_tc3, /* 18 Basic Timer Counter 0 */ + isr_tc4, /* 19 Basic Timer Counter 1 */ + isr_tc5, /* 20 Basic Timer Counter 2 */ + isr_tc6, /* 21 Basic Timer Counter 3 */ + isr_tc7, /* 22 Basic Timer Counter 4 */ + isr_adc, /* 23 Analog Digital Converter */ + isr_ac, /* 24 Analog Comparators */ + isr_dac, /* 25 Digital Analog Converter */ + isr_ptc, /* 26 Peripheral Touch Controller */ + isr_i2c /* 27 Inter-IC Sound Interface */ + } };