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Merge pull request #6714 from OTAkeys/pr/stm32_unify_gpio

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cpu/stm32_common: unify gpio driver
This commit is contained in:
lebrush 2017-03-13 21:08:00 +01:00 committed by GitHub
commit 2af148d8cd
33 changed files with 181 additions and 1427 deletions
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12
boards/f4vi1/include/board.h
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@ -42,16 +42,16 @@ extern "C" {
#define LED1_MASK (1 << 3) #define LED1_MASK (1 << 3)
#define LED2_MASK (1 << 2) #define LED2_MASK (1 << 2)
#define LED0_ON (LED_PORT->BSRRH = LED0_MASK) #define LED0_ON (LED_PORT->BSRR = LED0_MASK)
#define LED0_OFF (LED_PORT->BSRRL = LED0_MASK) #define LED0_OFF (LED_PORT->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (LED_PORT->ODR ^= LED0_MASK) #define LED0_TOGGLE (LED_PORT->ODR ^= LED0_MASK)
#define LED1_ON (LED_PORT->BSRRH = LED1_MASK) #define LED1_ON (LED_PORT->BSRR = LED1_MASK)
#define LED1_OFF (LED_PORT->BSRRL = LED1_MASK) #define LED1_OFF (LED_PORT->BSRR = (LED1_MASK << 16))
#define LED1_TOGGLE (LED_PORT->ODR ^= LED1_MASK) #define LED1_TOGGLE (LED_PORT->ODR ^= LED1_MASK)
#define LED2_ON (LED_PORT->BSRRH = LED2_MASK) #define LED2_ON (LED_PORT->BSRR = LED2_MASK)
#define LED2_OFF (LED_PORT->BSRRL = LED2_MASK) #define LED2_OFF (LED_PORT->BSRR = (LED2_MASK << 16))
#define LED2_TOGGLE (LED_PORT->ODR ^= LED2_MASK) #define LED2_TOGGLE (LED_PORT->ODR ^= LED2_MASK)
/** @} */ /** @} */

4
boards/limifrog-v1/include/board.h
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@ -39,8 +39,8 @@ extern "C" {
#define LED0_PORT (GPIOC) #define LED0_PORT (GPIOC)
#define LED0_MASK (1 << 3) #define LED0_MASK (1 << 3)
#define LED0_ON (LED0_PORT->BSRRL = LED0_MASK) #define LED0_ON (LED0_PORT->BSRR = LED0_MASK)
#define LED0_OFF (LED0_PORT->BSRRH = LED0_MASK) #define LED0_OFF (LED0_PORT->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK) #define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK)
/** @} */ /** @} */

20
boards/msbiot/board.c
View File

@ -19,6 +19,7 @@
*/ */
#include "board.h" #include "board.h"
#include "periph/gpio.h"
static void leds_init(void); static void leds_init(void);
@ -44,20 +45,7 @@ void board_init(void)
*/ */
static void leds_init(void) static void leds_init(void)
{ {
/* enable clock for port GPIOB */ gpio_init(GPIO_PIN(PORT_B, 8), GPIO_OUT);
periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN); gpio_init(GPIO_PIN(PORT_B, 14), GPIO_OUT);
gpio_init(GPIO_PIN(PORT_B, 15), GPIO_OUT);
/* set output speed to 50MHz */
LED_PORT->OSPEEDR &= ~(0xF0030000);
LED_PORT->OSPEEDR |= 0xA0020000;
/* set output type to push-pull */
LED_PORT->OTYPER &= ~(0x0000C100);
/* configure pins as general outputs */
LED_PORT->MODER &= ~(0xF0030000);
LED_PORT->MODER |= 0x50010000;
/* disable pull resistors */
LED_PORT->PUPDR &= ~(0xF0030000);
/* turn all LEDs off */
LED_PORT->BSRRL = 0xC100;
} }

12
boards/msbiot/include/board.h
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@ -61,16 +61,16 @@ extern "C" {
#define LED1_MASK (1 << 14) #define LED1_MASK (1 << 14)
#define LED2_MASK (1 << 15) #define LED2_MASK (1 << 15)
#define LED0_ON (LED_PORT->BSRRH = LED0_MASK) #define LED0_ON (LED_PORT->BSRR = LED0_MASK)
#define LED0_OFF (LED_PORT->BSRRL = LED0_MASK) #define LED0_OFF (LED_PORT->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (LED_PORT->ODR ^= LED0_MASK) #define LED0_TOGGLE (LED_PORT->ODR ^= LED0_MASK)
#define LED1_ON (LED_PORT->BSRRH = LED1_MASK) #define LED1_ON (LED_PORT->BSRR = LED1_MASK)
#define LED1_OFF (LED_PORT->BSRRL = LED1_MASK) #define LED1_OFF (LED_PORT->BSRR = (LED1_MASK << 16))
#define LED1_TOGGLE (LED_PORT->ODR ^= LED1_MASK) #define LED1_TOGGLE (LED_PORT->ODR ^= LED1_MASK)
#define LED2_ON (LED_PORT->BSRRH = LED2_MASK) #define LED2_ON (LED_PORT->BSRR = LED2_MASK)
#define LED2_OFF (LED_PORT->BSRRL = LED2_MASK) #define LED2_OFF (LED_PORT->BSRR = (LED2_MASK << 16))
#define LED2_TOGGLE (LED_PORT->ODR ^= LED2_MASK) #define LED2_TOGGLE (LED_PORT->ODR ^= LED2_MASK)
/** @} */ /** @} */

15
boards/nucleo-common/include/board_common.h
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@ -36,19 +36,8 @@ extern "C" {
#define LED0_MASK (1 << 5) #define LED0_MASK (1 << 5)
#if defined(CPU_FAM_STM32F4) #define LED0_ON (GPIOA->BSRR = LED0_MASK)
#define LED_CREG BSRRH #define LED0_OFF (GPIOA->BSRR = (LED0_MASK << 16))
#else
#define LED_CREG BRR
#endif
#if defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1)
#define LED_SREG BSRRL
#else
#define LED_SREG BSRR
#endif
#define LED0_ON (GPIOA->LED_SREG = LED0_MASK)
#define LED0_OFF (GPIOA->LED_CREG = LED0_MASK)
#define LED0_TOGGLE (GPIOA->ODR ^= LED0_MASK) #define LED0_TOGGLE (GPIOA->ODR ^= LED0_MASK)
/** @} */ /** @} */

21
boards/nucleo144-f413/include/board.h
View File

@ -41,26 +41,23 @@ extern "C" {
* @brief LED pin definitions and handlers * @brief LED pin definitions and handlers
* @{ * @{
*/ */
#define LED_CREG BSRRH
#define LED_SREG BSRRL
#define LED0_PIN GPIO_PIN(PORT_B, 0) #define LED0_PIN GPIO_PIN(PORT_B, 0)
#define LED0_MASK (1 << 0) #define LED0_MASK (1 << 0)
#define LED0_ON (GPIOA->LED_SREG = LED0_MASK) #define LED0_ON (GPIOB->BSRR = LED0_MASK)
#define LED0_OFF (GPIOA->LED_CREG = LED0_MASK) #define LED0_OFF (GPIOB->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (GPIOA->ODR ^= LED0_MASK) #define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK)
#define LED1_PIN GPIO_PIN(PORT_B, 7) #define LED1_PIN GPIO_PIN(PORT_B, 7)
#define LED1_MASK (1 << 7) #define LED1_MASK (1 << 7)
#define LED1_OFF (GPIOA->LED_CREG = LED1_MASK) #define LED1_ON (GPIOB->BSRR = LED1_MASK)
#define LED1_ON (GPIOA->LED_SREG = LED1_MASK) #define LED1_OFF (GPIOB->BSRR = (LED1_MASK << 16))
#define LED1_TOGGLE (GPIOA->ODR ^= LED1_MASK) #define LED1_TOGGLE (GPIOB->ODR ^= LED1_MASK)
#define LED2_PIN GPIO_PIN(PORT_B, 14) #define LED2_PIN GPIO_PIN(PORT_B, 14)
#define LED2_MASK (1 << 14) #define LED2_MASK (1 << 14)
#define LED2_ON (GPIOA->LED_SREG = LED2_MASK) #define LED2_ON (GPIOB->BSRR = LED2_MASK)
#define LED2_OFF (GPIOA->LED_CREG = LED2_MASK) #define LED2_OFF (GPIOB->BSRR = (LED2_MASK << 16))
#define LED2_TOGGLE (GPIOA->ODR ^= LED2_MASK) #define LED2_TOGGLE (GPIOB->ODR ^= LED2_MASK)
/** @} */ /** @} */
/** /**

4
boards/nucleo32-f303/include/board.h
View File

@ -33,8 +33,8 @@ extern "C" {
#define LED0_MASK (1 << 3) #define LED0_MASK (1 << 3)
#define LED0_ON (GPIOB->BSRRL = LED0_MASK) #define LED0_ON (GPIOB->BSRR = LED0_MASK)
#define LED0_OFF (GPIOB->BSRRH = LED0_MASK) #define LED0_OFF (GPIOB->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK) #define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK)
/** @} */ /** @} */

32
boards/stm32f3discovery/include/board.h
View File

@ -50,36 +50,36 @@ extern "C" {
#define LED6_MASK (1 << 12) #define LED6_MASK (1 << 12)
#define LED7_MASK (1 << 13) #define LED7_MASK (1 << 13)
#define LED0_ON (LED_PORT->BSRRL = LED0_MASK) #define LED0_ON (LED_PORT->BSRR = LED0_MASK)
#define LED0_OFF (LED_PORT->BSRRH = LED0_MASK) #define LED0_OFF (LED_PORT->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (LED_PORT->ODR ^= LED0_MASK) #define LED0_TOGGLE (LED_PORT->ODR ^= LED0_MASK)
#define LED1_ON (LED_PORT->BSRRL = LED1_MASK) #define LED1_ON (LED_PORT->BSRR = LED1_MASK)
#define LED1_OFF (LED_PORT->BSRRH = LED1_MASK) #define LED1_OFF (LED_PORT->BSRR = (LED1_MASK << 16))
#define LED1_TOGGLE (LED_PORT->ODR ^= LED1_MASK) #define LED1_TOGGLE (LED_PORT->ODR ^= LED1_MASK)
#define LED2_ON (LED_PORT->BSRRL = LED2_MASK) #define LED2_ON (LED_PORT->BSRR = LED2_MASK)
#define LED2_OFF (LED_PORT->BSRRH = LED2_MASK) #define LED2_OFF (LED_PORT->BSRR = (LED2_MASK << 16))
#define LED2_TOGGLE (LED_PORT->ODR ^= LED2_MASK) #define LED2_TOGGLE (LED_PORT->ODR ^= LED2_MASK)
#define LED3_ON (LED_PORT->BSRRL = LED3_MASK) #define LED3_ON (LED_PORT->BSRR = LED3_MASK)
#define LED3_OFF (LED_PORT->BSRRH = LED3_MASK) #define LED3_OFF (LED_PORT->BSRR = (LED3_MASK << 16))
#define LED3_TOGGLE (LED_PORT->ODR ^= LED3_MASK) #define LED3_TOGGLE (LED_PORT->ODR ^= LED3_MASK)
#define LED4_ON (LED_PORT->BSRRL = LED4_MASK) #define LED4_ON (LED_PORT->BSRR = LED4_MASK)
#define LED4_OFF (LED_PORT->BSRRH = LED4_MASK) #define LED4_OFF (LED_PORT->BSRR = (LED4_MASK << 16))
#define LED4_TOGGLE (LED_PORT->ODR ^= LED4_MASK) #define LED4_TOGGLE (LED_PORT->ODR ^= LED4_MASK)
#define LED5_ON (LED_PORT->BSRRL = LED5_MASK) #define LED5_ON (LED_PORT->BSRR = LED5_MASK)
#define LED5_OFF (LED_PORT->BSRRH = LED5_MASK) #define LED5_OFF (LED_PORT->BSRR = (LED5_MASK << 16))
#define LED5_TOGGLE (LED_PORT->ODR ^= LED5_MASK) #define LED5_TOGGLE (LED_PORT->ODR ^= LED5_MASK)
#define LED6_ON (LED_PORT->BSRRL = LED6_MASK) #define LED6_ON (LED_PORT->BSRR = LED6_MASK)
#define LED6_OFF (LED_PORT->BSRRH = LED6_MASK) #define LED6_OFF (LED_PORT->BSRR = (LED6_MASK << 16))
#define LED6_TOGGLE (LED_PORT->ODR ^= LED6_MASK) #define LED6_TOGGLE (LED_PORT->ODR ^= LED6_MASK)
#define LED7_ON (LED_PORT->BSRRL = LED7_MASK) #define LED7_ON (LED_PORT->BSRR = LED7_MASK)
#define LED7_OFF (LED_PORT->BSRRH = LED7_MASK) #define LED7_OFF (LED_PORT->BSRR = (LED7_MASK << 16))
#define LED7_TOGGLE (LED_PORT->ODR ^= LED7_MASK) #define LED7_TOGGLE (LED_PORT->ODR ^= LED7_MASK)
/** @} */ /** @} */

16
boards/stm32f4discovery/include/board.h
View File

@ -59,20 +59,20 @@ extern "C" {
#define LED2_MASK (1 << 14) #define LED2_MASK (1 << 14)
#define LED3_MASK (1 << 15) #define LED3_MASK (1 << 15)
#define LED0_ON (LED_PORT->BSRRL = LED0_MASK) #define LED0_ON (LED_PORT->BSRR = LED0_MASK)
#define LED0_OFF (LED_PORT->BSRRH = LED0_MASK) #define LED0_OFF (LED_PORT->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (LED_PORT->ODR ^= LED0_MASK) #define LED0_TOGGLE (LED_PORT->ODR ^= LED0_MASK)
#define LED1_ON (LED_PORT->BSRRL = LED1_MASK) #define LED1_ON (LED_PORT->BSRR = LED1_MASK)
#define LED1_OFF (LED_PORT->BSRRH = LED1_MASK) #define LED1_OFF (LED_PORT->BSRR = (LED1_MASK << 16))
#define LED1_TOGGLE (LED_PORT->ODR ^= LED1_MASK) #define LED1_TOGGLE (LED_PORT->ODR ^= LED1_MASK)
#define LED2_ON (LED_PORT->BSRRL = LED2_MASK) #define LED2_ON (LED_PORT->BSRR = LED2_MASK)
#define LED2_OFF (LED_PORT->BSRRH = LED2_MASK) #define LED2_OFF (LED_PORT->BSRR = (LED2_MASK << 16))
#define LED2_TOGGLE (LED_PORT->ODR ^= LED2_MASK) #define LED2_TOGGLE (LED_PORT->ODR ^= LED2_MASK)
#define LED3_ON (LED_PORT->BSRRL = LED3_MASK) #define LED3_ON (LED_PORT->BSRR = LED3_MASK)
#define LED3_OFF (LED_PORT->BSRRH = LED3_MASK) #define LED3_OFF (LED_PORT->BSRR = (LED3_MASK << 16))
#define LED3_TOGGLE (LED_PORT->ODR ^= LED3_MASK) #define LED3_TOGGLE (LED_PORT->ODR ^= LED3_MASK)
/** @} */ /** @} */

45
cpu/stm32_common/include/periph_cpu_common.h
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@ -1,5 +1,6 @@
/* /*
* Copyright (C) 2016 Freie Universität Berlin * Copyright (C) 2016 Freie Universität Berlin
* 2017 OTA keys S.A.
* *
* This file is subject to the terms and conditions of the GNU Lesser * This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level * General Public License v2.1. See the file LICENSE in the top level
@ -14,6 +15,7 @@
* @brief Shared CPU specific definitions for the STM32 family * @brief Shared CPU specific definitions for the STM32 family
* *
* @author Hauke Petersen <hauke.petersen@fu-berlin.de> * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
*/ */
#ifndef PERIPH_CPU_COMMON_H #ifndef PERIPH_CPU_COMMON_H
@ -120,11 +122,11 @@ typedef enum {
GPIO_AF1, /**< use alternate function 1 */ GPIO_AF1, /**< use alternate function 1 */
GPIO_AF2, /**< use alternate function 2 */ GPIO_AF2, /**< use alternate function 2 */
GPIO_AF3, /**< use alternate function 3 */ GPIO_AF3, /**< use alternate function 3 */
#ifndef CPU_FAM_STM32F0
GPIO_AF4, /**< use alternate function 4 */ GPIO_AF4, /**< use alternate function 4 */
GPIO_AF5, /**< use alternate function 5 */ GPIO_AF5, /**< use alternate function 5 */
GPIO_AF6, /**< use alternate function 6 */ GPIO_AF6, /**< use alternate function 6 */
GPIO_AF7, /**< use alternate function 7 */ GPIO_AF7, /**< use alternate function 7 */
#ifndef CPU_FAM_STM32F0
GPIO_AF8, /**< use alternate function 8 */ GPIO_AF8, /**< use alternate function 8 */
GPIO_AF9, /**< use alternate function 9 */ GPIO_AF9, /**< use alternate function 9 */
GPIO_AF10, /**< use alternate function 10 */ GPIO_AF10, /**< use alternate function 10 */
@ -137,6 +139,47 @@ typedef enum {
#endif #endif
} gpio_af_t; } gpio_af_t;
#ifndef CPU_FAM_STM32F1
/**
* @brief Generate GPIO mode bitfields
*
* We use 5 bit to encode the mode:
* - bit 0+1: pin mode (input / output)
* - bit 2+3: pull resistor configuration
* - bit 4: output type (0: push-pull, 1: open-drain)
*/
#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
#ifndef DOXYGEN
/**
* @brief Override GPIO mode options
* @{
*/
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_IN = GPIO_MODE(0, 0, 0), /**< input w/o pull R */
GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< input with pull-up */
GPIO_OUT = GPIO_MODE(1, 0, 0), /**< push-pull output */
GPIO_OD = GPIO_MODE(1, 0, 1), /**< open-drain w/o pull R */
GPIO_OD_PU = GPIO_MODE(1, 1, 1) /**< open-drain with pull-up */
} gpio_mode_t;
/** @} */
/**
* @brief Override flank configuration values
* @{
*/
#define HAVE_GPIO_FLANK_T
typedef enum {
GPIO_RISING = 1, /**< emit interrupt on rising flank */
GPIO_FALLING = 2, /**< emit interrupt on falling flank */
GPIO_BOTH = 3 /**< emit interrupt on both flanks */
} gpio_flank_t;
/** @} */
#endif /* ndef DOXYGEN */
#endif /* ndef CPU_FAM_STM32F1 */
/** /**
* @brief Timer configuration * @brief Timer configuration
*/ */

57
cpu/stm32f0/periph/gpio.c → cpu/stm32_common/periph/gpio.c
View File

@ -1,5 +1,8 @@
/* /*
* Copyright (C) 2014 Freie Universität Berlin * Copyright (C) 2014-2015 Freie Universität Berlin
* 2015 Hamburg University of Applied Sciences
* 2017 Inria
* 2017 OTA keys S.A.
* *
* This file is subject to the terms and conditions of the GNU Lesser General * This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more * Public License v2.1. See the file LICENSE in the top level directory for more
@ -7,17 +10,23 @@
*/ */
/** /**
* @ingroup cpu_stm32f0 * @ingroup cpu_stm32_common
* @{ * @{
* *
* @file * @file
* @brief Low-level GPIO driver implementation * @brief Low-level GPIO driver implementation
* *
* @author Hauke Petersen <mail@haukepetersen.de> * @author Hauke Petersen <mail@haukepetersen.de>
* @author Fabian Nack <nack@inf.fu-berlin.de>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
* @author Vincent Dupont <vincent@otakeys.com>
* *
* @} * @}
*/ */
#ifndef CPU_FAM_STM32F1
#include "cpu.h" #include "cpu.h"
#include "periph/gpio.h" #include "periph/gpio.h"
#include "periph_conf.h" #include "periph_conf.h"
@ -65,7 +74,13 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
int pin_num = _pin_num(pin); int pin_num = _pin_num(pin);
/* enable clock */ /* enable clock */
#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1)
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin))); periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L0)
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
#else
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
#endif
/* set mode */ /* set mode */
port->MODER &= ~(0x3 << (2 * pin_num)); port->MODER &= ~(0x3 << (2 * pin_num));
@ -78,7 +93,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
port->OTYPER |= (((mode >> 4) & 0x1) << pin_num); port->OTYPER |= (((mode >> 4) & 0x1) << pin_num);
/* finally set pin speed to maximum and reset output */ /* finally set pin speed to maximum and reset output */
port->OSPEEDR |= (3 << (2 * pin_num)); port->OSPEEDR |= (3 << (2 * pin_num));
port->BRR = (1 << pin_num); port->BSRR = (1 << (pin_num + 16));
return 0; return 0;
} }
@ -94,12 +109,17 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
isr_ctx[pin_num].arg = arg; isr_ctx[pin_num].arg = arg;
/* enable clock of the SYSCFG module for EXTI configuration */ /* enable clock of the SYSCFG module for EXTI configuration */
#ifdef CPU_FAN_STM32F0
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN); periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN);
#else
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
#endif
/* initialize pin as input */ /* initialize pin as input */
gpio_init(pin, mode); gpio_init(pin, mode);
/* enable global pin interrupt */ /* enable global pin interrupt */
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0)
if (pin_num < 2) { if (pin_num < 2) {
NVIC_EnableIRQ(EXTI0_1_IRQn); NVIC_EnableIRQ(EXTI0_1_IRQn);
} }
@ -109,6 +129,17 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
else { else {
NVIC_EnableIRQ(EXTI4_15_IRQn); NVIC_EnableIRQ(EXTI4_15_IRQn);
} }
#else
if (pin_num < 5) {
NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
}
else if (pin_num < 10) {
NVIC_EnableIRQ(EXTI9_5_IRQn);
}
else {
NVIC_EnableIRQ(EXTI15_10_IRQn);
}
#endif
/* configure the active flank */ /* configure the active flank */
EXTI->RTSR &= ~(1 << pin_num); EXTI->RTSR &= ~(1 << pin_num);
EXTI->RTSR |= ((flank & 0x1) << pin_num); EXTI->RTSR |= ((flank & 0x1) << pin_num);
@ -143,7 +174,13 @@ void gpio_init_analog(gpio_t pin)
{ {
/* enable clock, needed as this function can be used without calling /* enable clock, needed as this function can be used without calling
* gpio_init first */ * gpio_init first */
#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1)
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin))); periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L0)
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
#else
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
#endif
/* set to analog mode */ /* set to analog mode */
_port(pin)->MODER |= (0x3 << (2 * _pin_num(pin))); _port(pin)->MODER |= (0x3 << (2 * _pin_num(pin)));
} }
@ -175,24 +212,24 @@ void gpio_set(gpio_t pin)
void gpio_clear(gpio_t pin) void gpio_clear(gpio_t pin)
{ {
_port(pin)->BRR = (1 << _pin_num(pin)); _port(pin)->BSRR = (1 << (_pin_num(pin) + 16));
} }
void gpio_toggle(gpio_t pin) void gpio_toggle(gpio_t pin)
{ {
if (gpio_read(pin)) { if (gpio_read(pin)) {
_port(pin)->BRR = (1 << _pin_num(pin)); gpio_clear(pin);
} else { } else {
_port(pin)->BSRR = (1 << _pin_num(pin)); gpio_set(pin);
} }
} }
void gpio_write(gpio_t pin, int value) void gpio_write(gpio_t pin, int value)
{ {
if (value) { if (value) {
_port(pin)->BSRR = (1 << _pin_num(pin)); gpio_set(pin);
} else { } else {
_port(pin)->BRR = (1 << _pin_num(pin)); gpio_clear(pin);
} }
} }
@ -208,3 +245,7 @@ void isr_exti(void)
} }
cortexm_isr_end(); cortexm_isr_end();
} }
#else
typedef int dont_be_pedantic;
#endif

40
cpu/stm32f0/include/periph_cpu.h
View File

@ -25,45 +25,6 @@
extern "C" { extern "C" {
#endif #endif
/**
* @brief Generate GPIO mode bitfields
*
* We use 5 bit to encode the mode:
* - bit 0+1: pin mode (input / output)
* - bit 2+3: pull resistor configuration
* - bit 4: output type (0: push-pull, 1: open-drain)
*/
#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
#ifndef DOXYGEN
/**
* @brief Override GPIO mode options
* @{
*/
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_IN = GPIO_MODE(0, 0, 0), /**< input w/o pull R */
GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< input with pull-up */
GPIO_OUT = GPIO_MODE(1, 0, 0), /**< push-pull output */
GPIO_OD = GPIO_MODE(1, 0, 1), /**< open-drain w/o pull R */
GPIO_OD_PU = GPIO_MODE(1, 1, 1) /**< open-drain with pull-up */
} gpio_mode_t;
/** @} */
/**
* @brief Override flank configuration values
* @{
*/
#define HAVE_GPIO_FLANK_T
typedef enum {
GPIO_RISING = 1, /**< emit interrupt on rising flank */
GPIO_FALLING = 2, /**< emit interrupt on falling flank */
GPIO_BOTH = 3 /**< emit interrupt on both flanks */
} gpio_flank_t;
/** @} */
#endif /* ndef DOXYGEN */
/** /**
* @brief Available ports on the STM32F0 family * @brief Available ports on the STM32F0 family
*/ */
@ -72,6 +33,7 @@ enum {
PORT_B = 1, /**< port B */ PORT_B = 1, /**< port B */
PORT_C = 2, /**< port C */ PORT_C = 2, /**< port C */
PORT_D = 3, /**< port D */ PORT_D = 3, /**< port D */
PORT_E = 4, /**< port E */
PORT_F = 5, /**< port F */ PORT_F = 5, /**< port F */
}; };

25
cpu/stm32f2/include/periph_cpu.h
View File

@ -27,31 +27,6 @@
extern "C" { extern "C" {
#endif #endif
/**
* @brief Generate GPIO mode bitfields
*
* We use 5 bit to encode the mode:
* - bit 0+1: pin mode (input / output)
* - bit 2+3: pull resistor configuration
* - bit 4: output type (0: push-pull, 1: open-drain)
*/
#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
/**
* @brief Override GPIO mode options
* @{
*/
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_IN = GPIO_MODE(0, 0, 0), /**< input w/o pull R */
GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< input with pull-up */
GPIO_OUT = GPIO_MODE(1, 0, 0), /**< push-pull output */
GPIO_OD = GPIO_MODE(1, 0, 1), /**< open-drain w/o pull R */
GPIO_OD_PU = GPIO_MODE(1, 1, 1) /**< open-drain with pull-up */
} gpio_mode_t;
/** @} */
/** /**
* @brief Available ports on the STM32F2 family * @brief Available ports on the STM32F2 family
*/ */

217
cpu/stm32f2/periph/gpio.c
View File

@ -1,217 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f2
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Fabian Nack <nack@inf.fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "periph/gpio.h"
#include "periph_conf.h"
/**
* @brief Number of available external interrupt lines
*/
#define GPIO_ISR_CHAN_NUMOF (16U)
/**
* @brief Hold one callback function pointer for each interrupt line
*/
static gpio_isr_ctx_t exti_chan[GPIO_ISR_CHAN_NUMOF];
/**
* @brief Extract the port base address from the given pin identifier
*/
static inline GPIO_TypeDef *_port(gpio_t pin)
{
return (GPIO_TypeDef *)(pin & ~(0x0f));
}
/**
* @brief Extract the port number form the given identifier
*
* The port number is extracted by looking at bits 10, 11, 12, 13 of the base
* register addresses.
*/
static inline int _port_num(gpio_t pin)
{
return ((pin >> 10) & 0x0f);
}
/**
* @brief Extract the pin number from the last 4 bit of the pin identifier
*/
static inline int _pin_num(gpio_t pin)
{
return (pin & 0x0f);
}
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
GPIO_TypeDef *port = _port(pin);
int pin_num = _pin_num(pin);
/* enable clock */
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
/* set mode */
port->MODER &= ~(0x3 << (2 * pin_num));
port->MODER |= ((mode & 0x3) << (2 * pin_num));
/* set pull resistor configuration */
port->PUPDR &= ~(0x3 << (2 * pin_num));
port->PUPDR |= (((mode >> 2) & 0x3) << (2 * pin_num));
/* set output mode */
port->OTYPER &= ~(1 << pin_num);
port->OTYPER |= (((mode >> 4) & 0x1) << pin_num);
/* reset speed value and clear pin */
port->OSPEEDR |= (3 << (2 * pin_num));
port->BSRR = (1 << (pin_num + 16));
return 0;
}
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
int pin_num = _pin_num(pin);
int port_num = _port_num(pin);
/* configure and save exti configuration struct */
exti_chan[pin_num].cb = cb;
exti_chan[pin_num].arg = arg;
/* enable the SYSCFG clock */
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
/* initialize pin as input */
gpio_init(pin, mode);
/* enable global pin interrupt */
if (pin_num < 5) {
NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
}
else if (pin_num < 10) {
NVIC_EnableIRQ(EXTI9_5_IRQn);
}
else {
NVIC_EnableIRQ(EXTI15_10_IRQn);
}
/* configure the active edge(s) */
switch (flank) {
case GPIO_RISING:
EXTI->RTSR |= (1 << pin_num);
EXTI->FTSR &= ~(1 << pin_num);
break;
case GPIO_FALLING:
EXTI->RTSR &= ~(1 << pin_num);
EXTI->FTSR |= (1 << pin_num);
break;
case GPIO_BOTH:
EXTI->RTSR |= (1 << pin_num);
EXTI->FTSR |= (1 << pin_num);
break;
}
/* enable specific pin as exti sources */
SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4));
SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4));
/* clear any pending requests */
EXTI->PR = (1 << pin_num);
/* enable interrupt for EXTI line */
EXTI->IMR |= (1 << pin_num);
return 0;
}
void gpio_init_af(gpio_t pin, gpio_af_t af)
{
GPIO_TypeDef *port = _port(pin);
uint32_t pin_num = _pin_num(pin);
/* set pin to AF mode */
port->MODER &= ~(3 << (2 * pin_num));
port->MODER |= (2 << (2 * pin_num));
/* set selected function */
port->AFR[(pin_num > 7) ? 1 : 0] &= ~(0xf << ((pin_num & 0x07) * 4));
port->AFR[(pin_num > 7) ? 1 : 0] |= (af << ((pin_num & 0x07) * 4));
}
void gpio_init_analog(gpio_t pin)
{
/* enable clock */
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
/* set to analog mode */
_port(pin)->MODER |= (0x3 << (2 * _pin_num(pin)));
}
void gpio_irq_enable(gpio_t pin)
{
EXTI->IMR |= (1 << _pin_num(pin));
}
void gpio_irq_disable(gpio_t pin)
{
EXTI->IMR &= ~(1 << _pin_num(pin));
}
int gpio_read(gpio_t pin)
{
GPIO_TypeDef *port = _port(pin);
uint32_t pin_num = _pin_num(pin);
if (port->MODER & (3 << (pin_num * 2))) { /* if configured as output */
return port->ODR & (1 << pin_num); /* read output data reg */
} else {
return port->IDR & (1 << pin_num); /* else read input data reg */
}
}
void gpio_set(gpio_t pin)
{
_port(pin)->BSRR = (1 << _pin_num(pin));
}
void gpio_clear(gpio_t pin)
{
_port(pin)->BSRR = (1 << (_pin_num(pin) + 16));
}
void gpio_toggle(gpio_t pin)
{
if (gpio_read(pin)) {
gpio_clear(pin);
} else {
gpio_set(pin);
}
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
gpio_set(pin);
} else {
gpio_clear(pin);
}
}
void isr_exti(void)
{
/* only generate interrupts against lines which have their IMR set */
uint32_t pending_isr = (EXTI->PR & EXTI->IMR);
for (unsigned i = 0; i < GPIO_ISR_CHAN_NUMOF; i++) {
if (pending_isr & (1 << i)) {
EXTI->PR = (1 << i); /* clear by writing a 1 */
exti_chan[i].cb(exti_chan[i].arg);
}
}
cortexm_isr_end();
}

39
cpu/stm32f3/include/periph_cpu.h
View File

@ -25,33 +25,6 @@
extern "C" { extern "C" {
#endif #endif
/**
* @brief Generate GPIO mode bitfields
*
* We use 5 bit to encode the mode:
* - bit 0+1: pin mode (input / output)
* - bit 2+3: pull resistor configuration
* - bit 4: output type (0: push-pull, 1: open-drain)
*/
#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
#ifndef DOXYGEN
/**
* @brief Override GPIO mode options
* @{
*/
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_IN = GPIO_MODE(0, 0, 0), /**< input w/o pull R */
GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< input with pull-up */
GPIO_OUT = GPIO_MODE(1, 0, 0), /**< push-pull output */
GPIO_OD = GPIO_MODE(1, 0, 1), /**< open-drain w/o pull R */
GPIO_OD_PU = GPIO_MODE(1, 1, 1) /**< open-drain with pull-up */
} gpio_mode_t;
/** @} */
#endif /* ndef DOXYGEN */
/** /**
* @brief Available ports on the STM32F3 family * @brief Available ports on the STM32F3 family
*/ */
@ -62,6 +35,8 @@ enum {
PORT_D = 3, /**< port D */ PORT_D = 3, /**< port D */
PORT_E = 4, /**< port E */ PORT_E = 4, /**< port E */
PORT_F = 5, /**< port F */ PORT_F = 5, /**< port F */
PORT_G = 6, /**< port G */
PORT_H = 7, /**< port H */
}; };
/** /**
@ -73,16 +48,6 @@ typedef struct {
uint8_t chan; /**< DAC device used for this line */ uint8_t chan; /**< DAC device used for this line */
} dac_conf_t; } dac_conf_t;
/**
* @brief Configure the alternate function for the given pin
*
* @note This is meant for internal use in STM32F4 peripheral drivers only
*
* @param[in] pin pin to configure
* @param[in] af alternate function to use
*/
void gpio_init_af(gpio_t pin, gpio_af_t af);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

3
cpu/stm32f3/include/vendor/stm32f303x8.h vendored
View File

@ -412,8 +412,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */

3
cpu/stm32f3/include/vendor/stm32f303xc.h vendored
View File

@ -431,8 +431,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */

3
cpu/stm32f3/include/vendor/stm32f303xe.h vendored
View File

@ -492,8 +492,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */

3
cpu/stm32f3/include/vendor/stm32f334x8.h vendored
View File

@ -415,8 +415,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */

217
cpu/stm32f3/periph/gpio.c
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@ -1,217 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f3
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "periph/gpio.h"
#include "periph_conf.h"
/**
* @brief The STM32F3 has 16 EXTI channels
*/
#define EXTI_NUMOF (16U)
/**
* @brief Hold one callback function pointer for each interrupt line
*/
static gpio_isr_ctx_t exti_chan[EXTI_NUMOF];
/**
* @brief Extract the port base address from the given pin identifier
*/
static inline GPIO_TypeDef *_port(gpio_t pin)
{
return (GPIO_TypeDef *)(pin & ~(0x0f));
}
/**
* @brief Extract the port number form the given identifier
*
* The port number is extracted by looking at bits 10, 11, 12, 13 of the base
* register addresses.
*/
static inline int _port_num(gpio_t pin)
{
return ((pin >> 10) & 0x0f);
}
/**
* @brief Extract the pin number from the last 4 bit of the pin identifier
*/
static inline int _pin_num(gpio_t pin)
{
return (pin & 0x0f);
}
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
GPIO_TypeDef *port = _port(pin);
int pin_num = _pin_num(pin);
/* enable clock */
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
/* set mode */
port->MODER &= ~(0x3 << (2 * pin_num));
port->MODER |= ((mode & 0x3) << (2 * pin_num));
/* set pull resistor configuration */
port->PUPDR &= ~(0x3 << (2 * pin_num));
port->PUPDR |= (((mode >> 2) & 0x3) << (2 * pin_num));
/* set output mode */
port->OTYPER &= ~(1 << pin_num);
port->OTYPER |= (((mode >> 4) & 0x1) << pin_num);
/* reset speed value and clear pin */
port->OSPEEDR |= (3 << (2 * pin_num));
port->BSRRH = (1 << pin_num);
return 0;
}
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
int pin_num = _pin_num(pin);
int port_num = _port_num(pin);
/* configure and save exti configuration struct */
exti_chan[pin_num].cb = cb;
exti_chan[pin_num].arg = arg;
/* enable the SYSCFG clock */
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
/* configure pin as input */
gpio_init(pin, mode);
/* enable global pin interrupt */
if (pin_num < 5) {
NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
}
else if (pin_num < 10) {
NVIC_EnableIRQ(EXTI9_5_IRQn);
}
else {
NVIC_EnableIRQ(EXTI15_10_IRQn);
}
/* configure the active edge(s) */
switch (flank) {
case GPIO_RISING:
EXTI->RTSR |= (1 << pin_num);
EXTI->FTSR &= ~(1 << pin_num);
break;
case GPIO_FALLING:
EXTI->RTSR &= ~(1 << pin_num);
EXTI->FTSR |= (1 << pin_num);
break;
case GPIO_BOTH:
EXTI->RTSR |= (1 << pin_num);
EXTI->FTSR |= (1 << pin_num);
break;
}
/* enable specific pin as exti sources */
SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4));
SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4));
/* clear any pending requests */
EXTI->PR = (1 << pin_num);
/* enable interrupt for EXTI line */
EXTI->IMR |= (1 << pin_num);
return 0;
}
void gpio_init_af(gpio_t pin, gpio_af_t af)
{
GPIO_TypeDef *port = _port(pin);
uint32_t pin_num = _pin_num(pin);
/* set pin to AF mode */
port->MODER &= ~(3 << (2 * pin_num));
port->MODER |= (2 << (2 * pin_num));
/* set selected function */
port->AFR[(pin_num > 7) ? 1 : 0] &= ~(0xf << ((pin_num & 0x07) * 4));
port->AFR[(pin_num > 7) ? 1 : 0] |= (af << ((pin_num & 0x07) * 4));
}
void gpio_init_analog(gpio_t pin)
{
/* enable clock, needed as this function can be used without calling
* gpio_init first */
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
/* set to analog mode */
_port(pin)->MODER |= (0x3 << (2 * _pin_num(pin)));
}
void gpio_irq_enable(gpio_t pin)
{
EXTI->IMR |= (1 << _pin_num(pin));
}
void gpio_irq_disable(gpio_t pin)
{
EXTI->IMR &= ~(1 << _pin_num(pin));
}
int gpio_read(gpio_t pin)
{
GPIO_TypeDef *port = _port(pin);
uint32_t pin_num = _pin_num(pin);
if (port->MODER & (3 << (pin_num * 2))) { /* if configured as output */
return port->ODR & (1 << pin_num); /* read output data reg */
} else {
return port->IDR & (1 << pin_num); /* else read input data reg */
}
}
void gpio_set(gpio_t pin)
{
_port(pin)->BSRRL = (1 << _pin_num(pin));
}
void gpio_clear(gpio_t pin)
{
_port(pin)->BSRRH = (1 << _pin_num(pin));
}
void gpio_toggle(gpio_t pin)
{
if (gpio_read(pin)) {
gpio_clear(pin);
} else {
gpio_set(pin);
}
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
gpio_set(pin);
} else {
gpio_clear(pin);
}
}
void isr_exti(void)
{
/* only generate interrupts against lines which have their IMR set */
uint32_t pending_isr = (EXTI->PR & EXTI->IMR);
for (int i = 0; i < EXTI_NUMOF; i++) {
if (pending_isr & (1 << i)) {
EXTI->PR = (1 << i); /* clear by writing a 1 */
exti_chan[i].cb(exti_chan[i].arg);
}
}
cortexm_isr_end();
}

57
cpu/stm32f4/include/periph_cpu.h
View File

@ -25,6 +25,21 @@
extern "C" { extern "C" {
#endif #endif
/**
* @brief Available ports on the STM32F4 family
*/
enum {
PORT_A = 0, /**< port A */
PORT_B = 1, /**< port B */
PORT_C = 2, /**< port C */
PORT_D = 3, /**< port D */
PORT_E = 4, /**< port E */
PORT_F = 5, /**< port F */
PORT_G = 6, /**< port G */
PORT_H = 7, /**< port H */
PORT_I = 8 /**< port I */
};
/** /**
* @brief Available number of ADC devices * @brief Available number of ADC devices
*/ */
@ -51,48 +66,6 @@ typedef enum {
/** @} */ /** @} */
#endif /* ndef DOXYGEN */ #endif /* ndef DOXYGEN */
/**
* @brief Generate GPIO mode bitfields
*
* We use 5 bit to encode the mode:
* - bit 0+1: pin mode (input / output)
* - bit 2+3: pull resistor configuration
* - bit 4: output type (0: push-pull, 1: open-drain)
*/
#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
#ifndef DOXYGEN
/**
* @brief Override GPIO mode options
* @{
*/
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_IN = GPIO_MODE(0, 0, 0), /**< input w/o pull R */
GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< input with pull-up */
GPIO_OUT = GPIO_MODE(1, 0, 0), /**< push-pull output */
GPIO_OD = GPIO_MODE(1, 0, 1), /**< open-drain w/o pull R */
GPIO_OD_PU = GPIO_MODE(1, 1, 1) /**< open-drain with pull-up */
} gpio_mode_t;
/** @} */
#endif /* ndef DOXYGEN */
/**
* @brief Available ports on the STM32F4 family
*/
enum {
PORT_A = 0, /**< port A */
PORT_B = 1, /**< port B */
PORT_C = 2, /**< port C */
PORT_D = 3, /**< port D */
PORT_E = 4, /**< port E */
PORT_F = 5, /**< port F */
PORT_G = 6, /**< port G */
PORT_H = 7, /**< port H */
PORT_I = 8 /**< port I */
};
/** /**
* @brief ADC channel configuration data * @brief ADC channel configuration data
*/ */

3
cpu/stm32f4/include/vendor/stm32f401xe.h vendored
View File

@ -287,8 +287,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;

3
cpu/stm32f4/include/vendor/stm32f407xx.h vendored
View File

@ -546,8 +546,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;

3
cpu/stm32f4/include/vendor/stm32f411xe.h vendored
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@ -289,8 +289,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;

3
cpu/stm32f4/include/vendor/stm32f413xx.h vendored
View File

@ -466,8 +466,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;

3
cpu/stm32f4/include/vendor/stm32f415xx.h vendored
View File

@ -452,8 +452,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;

3
cpu/stm32f4/include/vendor/stm32f446xx.h vendored
View File

@ -480,8 +480,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef; } GPIO_TypeDef;

217
cpu/stm32f4/periph/gpio.c
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@ -1,217 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32f4
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Fabian Nack <nack@inf.fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "periph/gpio.h"
#include "periph_conf.h"
/**
* @brief Number of available external interrupt lines
*/
#define GPIO_ISR_CHAN_NUMOF (16U)
/**
* @brief Hold one callback function pointer for each interrupt line
*/
static gpio_isr_ctx_t exti_chan[GPIO_ISR_CHAN_NUMOF];
/**
* @brief Extract the port base address from the given pin identifier
*/
static inline GPIO_TypeDef *_port(gpio_t pin)
{
return (GPIO_TypeDef *)(pin & ~(0x0f));
}
/**
* @brief Extract the port number form the given identifier
*
* The port number is extracted by looking at bits 10, 11, 12, 13 of the base
* register addresses.
*/
static inline int _port_num(gpio_t pin)
{
return ((pin >> 10) & 0x0f);
}
/**
* @brief Extract the pin number from the last 4 bit of the pin identifier
*/
static inline int _pin_num(gpio_t pin)
{
return (pin & 0x0f);
}
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
GPIO_TypeDef *port = _port(pin);
int pin_num = _pin_num(pin);
/* enable clock */
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
/* set mode */
port->MODER &= ~(0x3 << (2 * pin_num));
port->MODER |= ((mode & 0x3) << (2 * pin_num));
/* set pull resistor configuration */
port->PUPDR &= ~(0x3 << (2 * pin_num));
port->PUPDR |= (((mode >> 2) & 0x3) << (2 * pin_num));
/* set output mode */
port->OTYPER &= ~(1 << pin_num);
port->OTYPER |= (((mode >> 4) & 0x1) << pin_num);
/* reset speed value and clear pin */
port->OSPEEDR |= (3 << (2 * pin_num));
port->BSRRH = (1 << pin_num);
return 0;
}
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
int pin_num = _pin_num(pin);
int port_num = _port_num(pin);
/* configure and save exti configuration struct */
exti_chan[pin_num].cb = cb;
exti_chan[pin_num].arg = arg;
/* enable the SYSCFG clock */
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
/* initialize pin as input */
gpio_init(pin, mode);
/* enable global pin interrupt */
if (pin_num < 5) {
NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
}
else if (pin_num < 10) {
NVIC_EnableIRQ(EXTI9_5_IRQn);
}
else {
NVIC_EnableIRQ(EXTI15_10_IRQn);
}
/* configure the active edge(s) */
switch (flank) {
case GPIO_RISING:
EXTI->RTSR |= (1 << pin_num);
EXTI->FTSR &= ~(1 << pin_num);
break;
case GPIO_FALLING:
EXTI->RTSR &= ~(1 << pin_num);
EXTI->FTSR |= (1 << pin_num);
break;
case GPIO_BOTH:
EXTI->RTSR |= (1 << pin_num);
EXTI->FTSR |= (1 << pin_num);
break;
}
/* enable specific pin as exti sources */
SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4));
SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4));
/* clear any pending requests */
EXTI->PR = (1 << pin_num);
/* enable interrupt for EXTI line */
EXTI->IMR |= (1 << pin_num);
return 0;
}
void gpio_init_af(gpio_t pin, gpio_af_t af)
{
GPIO_TypeDef *port = _port(pin);
uint32_t pin_num = _pin_num(pin);
/* set pin to AF mode */
port->MODER &= ~(3 << (2 * pin_num));
port->MODER |= (2 << (2 * pin_num));
/* set selected function */
port->AFR[(pin_num > 7) ? 1 : 0] &= ~(0xf << ((pin_num & 0x07) * 4));
port->AFR[(pin_num > 7) ? 1 : 0] |= (af << ((pin_num & 0x07) * 4));
}
void gpio_init_analog(gpio_t pin)
{
/* enable clock */
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
/* set to analog mode */
_port(pin)->MODER |= (0x3 << (2 * _pin_num(pin)));
}
void gpio_irq_enable(gpio_t pin)
{
EXTI->IMR |= (1 << _pin_num(pin));
}
void gpio_irq_disable(gpio_t pin)
{
EXTI->IMR &= ~(1 << _pin_num(pin));
}
int gpio_read(gpio_t pin)
{
GPIO_TypeDef *port = _port(pin);
uint32_t pin_num = _pin_num(pin);
if (port->MODER & (3 << (pin_num * 2))) { /* if configured as output */
return port->ODR & (1 << pin_num); /* read output data reg */
} else {
return port->IDR & (1 << pin_num); /* else read input data reg */
}
}
void gpio_set(gpio_t pin)
{
_port(pin)->BSRRL = (1 << _pin_num(pin));
}
void gpio_clear(gpio_t pin)
{
_port(pin)->BSRRH = (1 << _pin_num(pin));
}
void gpio_toggle(gpio_t pin)
{
if (gpio_read(pin)) {
gpio_clear(pin);
} else {
gpio_set(pin);
}
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
gpio_set(pin);
} else {
gpio_clear(pin);
}
}
void isr_exti(void)
{
/* only generate interrupts against lines which have their IMR set */
uint32_t pending_isr = (EXTI->PR & EXTI->IMR);
for (unsigned i = 0; i < GPIO_ISR_CHAN_NUMOF; i++) {
if (pending_isr & (1 << i)) {
EXTI->PR = (1 << i); /* clear by writing a 1 */
exti_chan[i].cb(exti_chan[i].arg);
}
}
cortexm_isr_end();
}

44
cpu/stm32l0/include/periph_cpu.h
View File

@ -29,53 +29,15 @@ extern "C" {
#endif #endif
/** /**
* @brief Generate GPIO mode bitfields * @brief Available ports on the STM32L0 family
*
* We use 5 bit to encode the mode:
* - bit 0+1: pin mode (input / output)
* - bit 2+3: pull resistor configuration
* - bit 4: output type (0: push-pull, 1: open-drain)
*/
#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
#ifndef DOXYGEN
/**
* @brief Override GPIO mode options
* @{
*/
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_IN = GPIO_MODE(0, 0, 0), /**< input w/o pull R */
GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< input with pull-up */
GPIO_OUT = GPIO_MODE(1, 0, 0), /**< push-pull output */
GPIO_OD = GPIO_MODE(1, 0, 1), /**< open-drain w/o pull R */
GPIO_OD_PU = GPIO_MODE(1, 1, 1) /**< open-drain with pull-up */
} gpio_mode_t;
/** @} */
/**
* @brief Override flank configuration values
* @{
*/
#define HAVE_GPIO_FLANK_T
typedef enum {
GPIO_RISING = 1, /**< emit interrupt on rising flank */
GPIO_FALLING = 2, /**< emit interrupt on falling flank */
GPIO_BOTH = 3 /**< emit interrupt on both flanks */
} gpio_flank_t;
/** @} */
#endif /* ndef DOXYGEN */
/**
* @brief Available ports on the STM32F0 family
*/ */
enum { enum {
PORT_A = 0, /**< port A */ PORT_A = 0, /**< port A */
PORT_B = 1, /**< port B */ PORT_B = 1, /**< port B */
PORT_C = 2, /**< port C */ PORT_C = 2, /**< port C */
PORT_D = 3, /**< port D */ PORT_D = 3, /**< port D */
PORT_F = 5, /**< port F */ PORT_E = 4, /**< port E */
PORT_H = 7, /**< port H */
}; };
#ifndef DOXYGEN #ifndef DOXYGEN

220
cpu/stm32l0/periph/gpio.c
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@ -1,220 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32l0
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* @author Hauke Petersen <mail@haukepetersen.de>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
#include "cpu.h"
#include "periph/gpio.h"
#include "periph_conf.h"
/**
* @brief The STM32L0 family has 16 external interrupt lines
*/
#define EXTI_NUMOF (16U)
/**
* @brief Allocate memory for one callback and argument per EXTI channel
*/
static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF];
/**
* @brief Extract the port base address from the given pin identifier
*/
static inline GPIO_TypeDef *_port(gpio_t pin)
{
return (GPIO_TypeDef *)(pin & ~(0x0f));
}
/**
* @brief Extract the port number form the given identifier
*
* The port number is extracted by looking at bits 10, 11, 12, 13 of the base
* register addresses.
*/
static inline int _port_num(gpio_t pin)
{
return ((pin >> 10) & 0x0f);
}
/**
* @brief Extract the pin number from the last 4 bit of the pin identifier
*/
static inline int _pin_num(gpio_t pin)
{
return (pin & 0x0f);
}
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
GPIO_TypeDef *port = _port(pin);
int pin_num = _pin_num(pin);
/* enable clock */
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
/* set mode */
port->MODER &= ~(0x3 << (2 * pin_num));
port->MODER |= ((mode & 0x3) << (2 * pin_num));
/* set pull resistor configuration */
port->PUPDR &= ~(0x3 << (2 * pin_num));
port->PUPDR |= (((mode >> 2) & 0x3) << (2 * pin_num));
/* set output mode */
port->OTYPER &= ~(1 << pin_num);
port->OTYPER |= (((mode >> 4) & 0x1) << pin_num);
/* finally set pin speed to maximum and reset output */
port->OSPEEDR |= (3 << (2 * pin_num));
port->BRR = (1 << pin_num);
return 0;
}
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
int pin_num = _pin_num(pin);
int port_num = _port_num(pin);
/* set callback */
isr_ctx[pin_num].cb = cb;
isr_ctx[pin_num].arg = arg;
/* enable clock of the SYSCFG module for EXTI configuration */
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
/* initialize pin as input */
gpio_init(pin, mode);
/* enable global pin interrupt */
if (pin_num < 2) {
NVIC_EnableIRQ(EXTI0_1_IRQn);
}
else if (pin_num < 4) {
NVIC_EnableIRQ(EXTI2_3_IRQn);
}
else {
NVIC_EnableIRQ(EXTI4_15_IRQn);
}
/* configure the active edge(s) */
switch (flank) {
case GPIO_RISING:
EXTI->RTSR |= (1 << pin_num);
EXTI->FTSR &= ~(1 << pin_num);
break;
case GPIO_FALLING:
EXTI->RTSR &= ~(1 << pin_num);
EXTI->FTSR |= (1 << pin_num);
break;
case GPIO_BOTH:
EXTI->RTSR |= (1 << pin_num);
EXTI->FTSR |= (1 << pin_num);
break;
}
/* enable specific pin as exti sources */
SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4));
SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4));
/* clear any pending requests */
EXTI->PR = (1 << pin_num);
/* enable interrupt for EXTI line */
EXTI->IMR |= (1 << pin_num);
return 0;
}
void gpio_init_af(gpio_t pin, gpio_af_t af)
{
GPIO_TypeDef *port = _port(pin);
uint32_t pin_num = _pin_num(pin);
/* set pin to AF mode */
port->MODER &= ~(3 << (2 * pin_num));
port->MODER |= (2 << (2 * pin_num));
/* set selected function */
port->AFR[(pin_num > 7) ? 1 : 0] &= ~(0xf << ((pin_num & 0x07) * 4));
port->AFR[(pin_num > 7) ? 1 : 0] |= (af << ((pin_num & 0x07) * 4));
}
void gpio_init_analog(gpio_t pin)
{
/* enable clock, needed as this function can be used without calling
* gpio_init first */
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
/* set to analog mode */
_port(pin)->MODER |= (0x3 << (2 * _pin_num(pin)));
}
void gpio_irq_enable(gpio_t pin)
{
EXTI->IMR |= (1 << _pin_num(pin));
}
void gpio_irq_disable(gpio_t pin)
{
EXTI->IMR &= ~(1 << _pin_num(pin));
}
int gpio_read(gpio_t pin)
{
if (_port(pin)->MODER & (0x3 << (_pin_num(pin) * 2))) {
return _port(pin)->ODR & (1 << _pin_num(pin));
}
else {
return _port(pin)->IDR & (1 << _pin_num(pin));
}
}
void gpio_set(gpio_t pin)
{
_port(pin)->BSRR = (1 << _pin_num(pin));
}
void gpio_clear(gpio_t pin)
{
_port(pin)->BRR = (1 << _pin_num(pin));
}
void gpio_toggle(gpio_t pin)
{
if (gpio_read(pin)) {
_port(pin)->BRR = (1 << _pin_num(pin));
} else {
_port(pin)->BSRR = (1 << _pin_num(pin));
}
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
_port(pin)->BSRR = (1 << _pin_num(pin));
} else {
_port(pin)->BRR = (1 << _pin_num(pin));
}
}
void isr_exti(void)
{
/* only generate interrupts against lines which have their IMR set */
uint32_t pending_isr = (EXTI->PR & EXTI->IMR);
for (size_t i = 0; i < EXTI_NUMOF; i++) {
if (pending_isr & (1 << i)) {
EXTI->PR = (1 << i); /* clear by writing a 1 */
isr_ctx[i].cb(isr_ctx[i].arg);
}
}
cortexm_isr_end();
}

37
cpu/stm32l1/include/periph_cpu.h
View File

@ -27,33 +27,6 @@
extern "C" { extern "C" {
#endif #endif
/**
* @brief Generate GPIO mode bitfields
*
* We use 5 bit to encode the mode:
* - bit 0+1: pin mode (input / output)
* - bit 2+3: pull resistor configuration
* - bit 4: output type (0: push-pull, 1: open-drain)
*/
#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
#ifndef DOXYGEN
/**
* @brief Override GPIO mode options
* @{
*/
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_IN = GPIO_MODE(0, 0, 0), /**< input w/o pull R */
GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
GPIO_IN_PU = GPIO_MODE(0, 1, 0), /**< input with pull-up */
GPIO_OUT = GPIO_MODE(1, 0, 0), /**< push-pull output */
GPIO_OD = GPIO_MODE(1, 0, 1), /**< open-drain w/o pull R */
GPIO_OD_PU = GPIO_MODE(1, 1, 1) /**< open-drain with pull-up */
} gpio_mode_t;
/** @} */
#endif /* ndef DOXYGEN */
/** /**
* @brief Available ports on the STM32L1 family * @brief Available ports on the STM32L1 family
*/ */
@ -89,16 +62,6 @@ typedef struct {
uint8_t ev_irqn; /**< event IRQ */ uint8_t ev_irqn; /**< event IRQ */
} i2c_conf_t; } i2c_conf_t;
/**
* @brief Configure the alternate function for the given pin
*
* @note This is meant for internal use in STM32L1 peripheral drivers only
*
* @param[in] pin pin to configure
* @param[in] af alternate function to use
*/
void gpio_init_af(gpio_t pin, gpio_af_t af);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

3
cpu/stm32l1/include/vendor/stm32l1xx.h vendored
View File

@ -573,8 +573,7 @@ typedef struct
uint16_t RESERVED1; /*!< Reserved, 0x12 */ uint16_t RESERVED1; /*!< Reserved, 0x12 */
__IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
uint16_t RESERVED2; /*!< Reserved, 0x16 */ uint16_t RESERVED2; /*!< Reserved, 0x16 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
#if defined (STM32L1XX_HD) || defined (STM32L1XX_XL) #if defined (STM32L1XX_HD) || defined (STM32L1XX_XL)

222
cpu/stm32l1/periph/gpio.c
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@ -1,222 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
* Copyright (C) 2015 Hamburg University of Applied Sciences
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_stm32l1
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
*
* @}
*/
#include "cpu.h"
#include "periph/gpio.h"
#include "periph_conf.h"
/**
* @brief Number of available external interrupt lines
*/
#define GPIO_ISR_CHAN_NUMOF (16U)
/**
* @brief Hold one callback function pointer for each interrupt line
*/
static gpio_isr_ctx_t exti_chan[GPIO_ISR_CHAN_NUMOF];
/**
* @brief Extract the port base address from the given pin identifier
*/
static inline GPIO_TypeDef *_port(gpio_t pin)
{
return (GPIO_TypeDef *)(pin & ~(0x0f));
}
/**
* @brief Extract the port number form the given identifier
*
* The port number is extracted by looking at bits 10, 11, 12, 13 of the base
* register addresses.
*/
static inline int _port_num(gpio_t pin)
{
return ((pin >> 10) & 0x0f);
}
/**
* @brief Extract the pin number from the last 4 bit of the pin identifier
*/
static inline int _pin_num(gpio_t pin)
{
return (pin & 0x0f);
}
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
GPIO_TypeDef *port = _port(pin);
int pin_num = _pin_num(pin);
/* enable clock */
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
/* set mode */
port->MODER &= ~(0x3 << (2 * pin_num));
port->MODER |= ((mode & 0x3) << (2 * pin_num));
/* set pull resistor configuration */
port->PUPDR &= ~(0x3 << (2 * pin_num));
port->PUPDR |= (((mode >> 2) & 0x3) << (2 * pin_num));
/* set output mode */
port->OTYPER &= ~(1 << pin_num);
port->OTYPER |= (((mode >> 4) & 0x1) << pin_num);
/* finally set pin speed to maximum and reset output */
port->OSPEEDR |= (3 << (2 * pin_num));
port->BRR = (1 << pin_num);
return 0;
}
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
int pin_num = _pin_num(pin);
int port_num = _port_num(pin);
/* configure and save exti configuration struct */
exti_chan[pin_num].cb = cb;
exti_chan[pin_num].arg = arg;
/* enable the SYSCFG clock */
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
/* initialize pin as input */
gpio_init(pin, mode);
/* enable global pin interrupt */
if (pin_num < 5) {
NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
}
else if (pin_num < 10) {
NVIC_EnableIRQ(EXTI9_5_IRQn);
}
else {
NVIC_EnableIRQ(EXTI15_10_IRQn);
}
/* configure the active edge(s) */
switch (flank) {
case GPIO_RISING:
EXTI->RTSR |= (1 << pin_num);
EXTI->FTSR &= ~(1 << pin_num);
break;
case GPIO_FALLING:
EXTI->RTSR &= ~(1 << pin_num);
EXTI->FTSR |= (1 << pin_num);
break;
case GPIO_BOTH:
EXTI->RTSR |= (1 << pin_num);
EXTI->FTSR |= (1 << pin_num);
break;
}
/* enable specific pin as exti sources */
SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4));
SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4));
/* clear any pending requests */
EXTI->PR = (1 << pin_num);
/* enable interrupt for EXTI line */
EXTI->IMR |= (1 << pin_num);
return 0;
}
void gpio_init_af(gpio_t pin, gpio_af_t af)
{
GPIO_TypeDef *port = _port(pin);
uint32_t pin_num = _pin_num(pin);
/* set pin to AF mode */
port->MODER &= ~(3 << (2 * pin_num));
port->MODER |= (2 << (2 * pin_num));
/* set selected function */
port->AFR[(pin_num > 7) ? 1 : 0] &= ~(0xf << ((pin_num & 0x07) * 4));
port->AFR[(pin_num > 7) ? 1 : 0] |= (af << ((pin_num & 0x07) * 4));
}
void gpio_init_analog(gpio_t pin)
{
/* enable clock, needed as this function can be used without calling
* gpio_init first */
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
/* set to analog mode */
_port(pin)->MODER |= (0x3 << (2 * _pin_num(pin)));
}
void gpio_irq_enable(gpio_t pin)
{
EXTI->IMR |= (1 << _pin_num(pin));
}
void gpio_irq_disable(gpio_t pin)
{
EXTI->IMR &= ~(1 << _pin_num(pin));
}
int gpio_read(gpio_t pin)
{
GPIO_TypeDef *port = _port(pin);
uint32_t pin_num = _pin_num(pin);
if (port->MODER & (3 << (pin_num * 2))) { /* if configured as output */
return port->ODR & (1 << pin_num); /* read output data reg */
}
else {
return port->IDR & (1 << pin_num); /* else read input data reg */
}
}
void gpio_set(gpio_t pin)
{
_port(pin)->BSRRL = (1 << _pin_num(pin));
}
void gpio_clear(gpio_t pin)
{
_port(pin)->BSRRH = (1 << _pin_num(pin));
}
void gpio_toggle(gpio_t pin)
{
if (gpio_read(pin)) {
gpio_clear(pin);
}
else {
gpio_set(pin);
}
}
void gpio_write(gpio_t pin, int value)
{
if (value) {
gpio_set(pin);
}
else {
gpio_clear(pin);
}
}
void isr_exti(void)
{
/* only generate interrupts against lines which have their IMR set */
uint32_t pending_isr = (EXTI->PR & EXTI->IMR);
for (int i = 0; i < GPIO_ISR_CHAN_NUMOF; i++) {
if (pending_isr & (1 << i)) {
EXTI->PR = (1 << i); /* clear by writing a 1 */
exti_chan[i].cb(exti_chan[i].arg);
}
}
cortexm_isr_end();
}