Merge pull request #15090 from aabadie/pr/boards/nucleo-g071rb

boards/nucleo-g071rb: add initial support

boards/nucleo-g071rb/Kconfig

@@ -0,0 +1,30 @@
+# Copyright (c) 2020 Inria
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+config BOARD
+    default "nucleo-g071rb" if BOARD_NUCLEO_G071RB
+
+config BOARD_NUCLEO_G071RB
+    bool
+    default y
+    select BOARD_COMMON_NUCLEO64
+    select CPU_MODEL_STM32G071RB
+
+    # Put defined MCU peripherals here (in alphabetical order)
+    select HAS_PERIPH_I2C
+    select HAS_PERIPH_RTT
+    select HAS_PERIPH_SPI
+    select HAS_PERIPH_TIMER
+    select HAS_PERIPH_UART
+
+    # Put other features for this board (in alphabetical order)
+    select HAS_RIOTBOOT
+    # Clock configuration
+    select BOARD_HAS_LSE
+
+source "$(RIOTBOARD)/common/stm32/Kconfig.g0"
+source "$(RIOTBOARD)/common/nucleo64/Kconfig"

boards/nucleo-g071rb/Makefile

@@ -0,0 +1,4 @@
+MODULE = board
+DIRS = $(RIOTBOARD)/common/nucleo
+
+include $(RIOTBASE)/Makefile.base

boards/nucleo-g071rb/Makefile.dep

@@ -0,0 +1 @@
+include $(RIOTBOARD)/common/nucleo/Makefile.dep

boards/nucleo-g071rb/Makefile.features

@@ -0,0 +1,15 @@
+CPU = stm32
+CPU_MODEL = stm32g071rb
+
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_rtt
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# Put other features for this board (in alphabetical order)
+FEATURES_PROVIDED += riotboot
+
+# load the common Makefile.features for Nucleo boards
+include $(RIOTBOARD)/common/nucleo64/Makefile.features

boards/nucleo-g071rb/Makefile.include

@@ -0,0 +1,2 @@
+# load the common Makefile.include for Nucleo boards
+include $(RIOTBOARD)/common/nucleo64/Makefile.include

boards/nucleo-g071rb/doc.txt

@@ -0,0 +1,5 @@
+/**
+@defgroup    boards_nucleo-g071rb STM32 Nucleo-G071RB
+@ingroup     boards_common_nucleo64
+@brief       Support for the STM32 Nucleo-G071RB
+ */

boards/nucleo-g071rb/include/periph_conf.h

@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2020 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_nucleo-g071rb
+ * @{
+ *
+ * @file
+ * @brief       Peripheral MCU configuration for the nucleo-g071rb board
+ *
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+/* Add specific clock configuration (HSE, LSE) for this board here */
+#ifndef CONFIG_BOARD_HAS_LSE
+#define CONFIG_BOARD_HAS_LSE            (1)
+#endif
+
+#include "g0/cfg_clock_default.h"
+#include "cfg_i2c1_pb8_pb9.h"
+#include "cfg_rtt_default.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    Timer configuration
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM3,
+        .max      = 0x0000ffff,
+        .rcc_mask = RCC_APBENR1_TIM3EN,
+        .bus      = APB1,
+        .irqn     = TIM3_IRQn
+    }
+};
+
+#define TIMER_0_ISR         isr_tim3
+
+#define TIMER_NUMOF         ARRAY_SIZE(timer_config)
+/** @} */
+
+/**
+ * @name    UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+    {
+        .dev        = USART2,
+        .rcc_mask   = RCC_APBENR1_USART2EN,
+        .rx_pin     = GPIO_PIN(PORT_A, 3),
+        .tx_pin     = GPIO_PIN(PORT_A, 2),
+        .rx_af      = GPIO_AF1,
+        .tx_af      = GPIO_AF1,
+        .bus        = APB1,
+        .irqn       = USART2_IRQn,
+    },
+    {   /* Arduino pinout on D0/D1 */
+        .dev        = USART1,
+        .rcc_mask   = RCC_APBENR2_USART1EN,
+        .rx_pin     = GPIO_PIN(PORT_C, 5),
+        .tx_pin     = GPIO_PIN(PORT_C, 4),
+        .rx_af      = GPIO_AF1,
+        .tx_af      = GPIO_AF1,
+        .bus        = APB12,
+        .irqn       = USART1_IRQn,
+    },
+};
+
+#define UART_0_ISR          (isr_usart2)
+#define UART_1_ISR          (isr_usart1)
+
+#define UART_NUMOF          ARRAY_SIZE(uart_config)
+/** @} */
+
+/**
+ * @name   SPI configuration
+ * @{
+ */
+static const spi_conf_t spi_config[] = {
+    {
+        .dev            = SPI1,
+        .mosi_pin       = GPIO_PIN(PORT_A, 7),  /* Arduino D11 */
+        .miso_pin       = GPIO_PIN(PORT_A, 6),  /* Arduino D12 */
+        .sclk_pin       = GPIO_PIN(PORT_A, 5),  /* Arduino D13 */
+        .cs_pin         = GPIO_UNDEF,
+        .mosi_af        = GPIO_AF0,
+        .miso_af        = GPIO_AF0,
+        .sclk_af        = GPIO_AF0,
+        .cs_af          = GPIO_AF0,
+        .rccmask        = RCC_APBENR2_SPI1EN,
+        .apbbus         = APB12,
+    },
+};
+
+#define SPI_NUMOF           ARRAY_SIZE(spi_config)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */

cpu/stm32/Kconfig

@@ -292,6 +292,10 @@ config CPU_MODEL_STM32G070RB
     bool
     select CPU_FAM_G0
 
+config CPU_MODEL_STM32G071RB
+    bool
+    select CPU_FAM_G0
+
 # STM32G4
 config CPU_MODEL_STM32G474RE
     bool
@@ -528,6 +532,7 @@ config CPU_MODEL
 
     # STM32G0
     default "stm32g070rb" if CPU_MODEL_STM32G070RB
+    default "stm32g071rb" if CPU_MODEL_STM32G071RB
 
     # STM32G4
     default "stm32g474re" if CPU_MODEL_STM32G474RE

cpu/stm32/periph/rtt_all.c

@@ -77,10 +77,13 @@ register. */
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
 #define IMR_REG             IMR2
 #define EXTI_IMR_BIT        EXTI_IMR2_IM32
+#elif defined(CPU_FAM_STM32G0)
+#define IMR_REG             IMR1
+#define EXTI_IMR_BIT        EXTI_IMR1_IM29
 #elif defined(CPU_FAM_STM32G4)
 #define IMR_REG             IMR2
 #define EXTI_IMR_BIT        EXTI_IMR2_IM37
-#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
+#elif defined(CPU_FAM_STM32L0)
 #define IMR_REG             IMR
 #define EXTI_IMR_BIT        EXTI_IMR_IM29
 #else
@@ -128,7 +131,11 @@ void rtt_init(void)
     EXTI->RTSR_REG |= EXTI_RTSR_BIT;
     EXTI->PR_REG = EXTI_PR_BIT;
 #endif
+#if defined(CPU_FAM_STM32G0)
+    NVIC_EnableIRQ(TIM6_DAC_LPTIM1_IRQn);
+#else
     NVIC_EnableIRQ(LPTIM1_IRQn);
+#endif
     /* enable timer */
     LPTIM1->CR = LPTIM_CR_ENABLE;
     /* set auto-reload value (timer needs to be enabled for this) */
@@ -185,6 +192,8 @@ void rtt_poweron(void)
 {
 #ifdef RCC_APB1ENR1_LPTIM1EN
     periph_clk_en(APB1, RCC_APB1ENR1_LPTIM1EN);
+#elif defined(RCC_APBENR1_LPTIM1EN)
+    periph_clk_en(APB1, RCC_APBENR1_LPTIM1EN);
 #else
     periph_clk_en(APB1, RCC_APB1ENR_LPTIM1EN);
 #endif
@@ -194,12 +203,18 @@ void rtt_poweroff(void)
 {
 #ifdef RCC_APB1ENR1_LPTIM1EN
     periph_clk_dis(APB1, RCC_APB1ENR1_LPTIM1EN);
+#elif defined(RCC_APBENR1_LPTIM1EN)
+    periph_clk_dis(APB1, RCC_APBENR1_LPTIM1EN);
 #else
     periph_clk_dis(APB1, RCC_APB1ENR_LPTIM1EN);
 #endif
 }
 
+#if defined(CPU_FAM_STM32G0)
+void isr_tim6_dac_lptim1(void)
+#else
 void isr_lptim1(void)
+#endif
 {
     if (LPTIM1->ISR & LPTIM_ISR_CMPM) {
         if (to_cb) {

examples/javascript/Makefile.ci

@@ -31,6 +31,7 @@ BOARD_INSUFFICIENT_MEMORY := \
     nucleo-f334r8 \
     nucleo-f410rb \
     nucleo-g070rb \
+    nucleo-g071rb \
     nucleo-l031k6 \
     nucleo-l053r8 \
     nucleo-l073rz \

examples/lua_REPL/Makefile.ci

@@ -47,6 +47,7 @@ BOARD_INSUFFICIENT_MEMORY := \
     nucleo-f334r8 \
     nucleo-f410rb \
     nucleo-g070rb \
+    nucleo-g071rb \
     nucleo-l031k6 \
     nucleo-l053r8 \
     nucleo-l073rz \

examples/lua_basic/Makefile.ci

@@ -24,6 +24,7 @@ BOARD_INSUFFICIENT_MEMORY := \
     nucleo-f334r8 \
     nucleo-f410rb \
     nucleo-g070rb \
+    nucleo-g071rb \
     nucleo-l031k6 \
     nucleo-l053r8 \
     nucleo-l412kb \

examples/micropython/Makefile.ci

@@ -14,6 +14,7 @@ BOARD_INSUFFICIENT_MEMORY := \
     nucleo-f303k8 \
     nucleo-f334r8 \
     nucleo-g070rb \
+    nucleo-g071rb \
     nucleo-l031k6 \
     nucleo-l053r8 \
     opencm904 \

examples/suit_update/Makefile.ci

@@ -16,6 +16,7 @@ BOARD_INSUFFICIENT_MEMORY := \
     nucleo-f303k8 \
     nucleo-f334r8 \
     nucleo-g070rb \
+    nucleo-g071rb \
     nucleo-l031k6 \
     nucleo-l053r8 \
     nucleo-l073rz \

tests/pkg_utensor/Makefile.ci

@@ -23,6 +23,7 @@ BOARD_INSUFFICIENT_MEMORY := \
     nucleo-f334r8 \
     nucleo-f410rb \
     nucleo-g070rb \
+    nucleo-g071rb \
     nucleo-l031k6 \
     nucleo-l053r8 \
     nucleo-l412kb \

tests/unittests/Makefile.ci

@@ -58,6 +58,7 @@ BOARD_INSUFFICIENT_MEMORY := \
     nucleo-f334r8 \
     nucleo-f410rb \
     nucleo-g070rb \
+    nucleo-g071rb \
     nucleo-l031k6 \
     nucleo-l053r8 \
     nucleo-l073rz \