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cpu/stm32: adapt timer driver to common CMSIS timer structure

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This commit is contained in:
Alexandre Abadie 2020-05-26 14:24:42 +02:00
parent d0a5e0527b
commit 2dc0ec00a1
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GPG Key ID: 1C919A403CAE1405
4 changed files with 10 additions and 5 deletions
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5
cpu/stm32/include/periph_cpu.h
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@ -83,6 +83,11 @@ extern "C" {
*/
#define TIMER_CHAN (4U)
/**
* @brief Define a macro for accessing a timer channel
*/
#define TIM_CHAN(tim, chan) *(&dev(tim)->CCR1 + chan)
/**
* @brief All STM QDEC timers have 2 capture channels
*/

4
cpu/stm32/periph/pwm.c
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@ -53,7 +53,7 @@ uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res)
dev(pwm)->CR1 = 0;
dev(pwm)->CR2 = 0;
for (unsigned i = 0; i < TIMER_CHAN; ++i) {
dev(pwm)->CCR[i] = 0;
TIM_CHAN(pwm, i) = 0;
}
/* configure the used pins */
@ -120,7 +120,7 @@ void pwm_set(pwm_t pwm, uint8_t channel, uint16_t value)
value = (uint16_t)dev(pwm)->ARR;
}
/* set new value */
dev(pwm)->CCR[pwm_config[pwm].chan[channel].cc_chan] = value;
TIM_CHAN(pwm, pwm_config[pwm].chan[channel].cc_chan) = value;
}
void pwm_poweron(pwm_t pwm)

4
cpu/stm32/periph/qdec.c
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@ -65,7 +65,7 @@ int32_t qdec_init(qdec_t qdec, qdec_mode_t mode, qdec_cb_t cb, void *arg)
dev(qdec)->SMCR = 0;
dev(qdec)->CCER = 0;
for (i = 0; i < QDEC_CHAN; i++) {
dev(qdec)->CCR[i] = 0;
TIM_CHAN(qdec, i) = 0;
}
/* Count on A (TI1) signal edges, B (TI2) signal edges or both,
@ -91,7 +91,7 @@ int32_t qdec_init(qdec_t qdec, qdec_mode_t mode, qdec_cb_t cb, void *arg)
/* Reset configuration and CC channels */
for (i = 0; i < QDEC_CHAN; i++) {
dev(qdec)->CCR[i] = 0;
TIM_CHAN(qdec, i) = 0;
}
/* Configure the used pins */

2
cpu/stm32/periph/timer.c
View File

@ -74,7 +74,7 @@ int timer_set_absolute(tim_t tim, int channel, unsigned int value)
return -1;
}
dev(tim)->CCR[channel] = (value & timer_config[tim].max);
TIM_CHAN(tim, channel) = (value & timer_config[tim].max);
dev(tim)->SR &= ~(TIM_SR_CC1IF << channel);
dev(tim)->DIER |= (TIM_DIER_CC1IE << channel);