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cpu/stm32f4: add support for stm32f410rb

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This commit is contained in:
Alexandre Abadie 2017-02-03 13:28:22 +01:00
parent 8e3ac4728c
commit 2eda4bf2fe
6 changed files with 4044 additions and 1 deletions
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6
cpu/stm32_common/cpu_common.c
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@ -59,12 +59,15 @@ void periph_clk_en(bus_t bus, uint32_t mask)
case AHB1: case AHB1:
RCC->AHB1ENR |= mask; RCC->AHB1ENR |= mask;
break; break;
/* STM32F410 RCC doesn't provide AHB2 and AHB3 */
#if !defined(CPU_MODEL_STM32F410RB)
case AHB2: case AHB2:
RCC->AHB2ENR |= mask; RCC->AHB2ENR |= mask;
break; break;
case AHB3: case AHB3:
RCC->AHB3ENR |= mask; RCC->AHB3ENR |= mask;
break; break;
#endif
#endif #endif
default: default:
DEBUG("unsupported bus %d\n", (int)bus); DEBUG("unsupported bus %d\n", (int)bus);
@ -99,12 +102,15 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
case AHB1: case AHB1:
RCC->AHB1ENR &= ~(mask); RCC->AHB1ENR &= ~(mask);
break; break;
/* STM32F410 RCC doesn't provide AHB2 and AHB3 */
#if !defined(CPU_MODEL_STM32F410RB)
case AHB2: case AHB2:
RCC->AHB2ENR &= ~(mask); RCC->AHB2ENR &= ~(mask);
break; break;
case AHB3: case AHB3:
RCC->AHB3ENR &= ~(mask); RCC->AHB3ENR &= ~(mask);
break; break;
#endif
#endif #endif
default: default:
DEBUG("unsupported bus %d\n", (int)bus); DEBUG("unsupported bus %d\n", (int)bus);

2
cpu/stm32f4/include/cpu_conf.h
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@ -27,6 +27,8 @@
#include "vendor/stm32f401xe.h" #include "vendor/stm32f401xe.h"
#elif defined(CPU_MODEL_STM32F407VG) #elif defined(CPU_MODEL_STM32F407VG)
#include "vendor/stm32f407xx.h" #include "vendor/stm32f407xx.h"
#elif defined(CPU_MODEL_STM32F410RB)
#include "vendor/stm32f410rx.h"
#elif defined(CPU_MODEL_STM32F411RE) #elif defined(CPU_MODEL_STM32F411RE)
#include "vendor/stm32f411xe.h" #include "vendor/stm32f411xe.h"
#elif defined(CPU_MODEL_STM32F413ZH) #elif defined(CPU_MODEL_STM32F413ZH)

2
cpu/stm32f4/include/periph_cpu.h
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@ -43,7 +43,7 @@ enum {
/** /**
* @brief Available number of ADC devices * @brief Available number of ADC devices
*/ */
#if defined(CPU_MODEL_STM32F401RE) || defined(CPU_MODEL_STM32F411RE)|| defined(CPU_MODEL_STM32F413ZH) #if defined(CPU_MODEL_STM32F401RE) || defined(CPU_MODEL_STM32F410RB) || defined(CPU_MODEL_STM32F411RE)|| defined(CPU_MODEL_STM32F413ZH)
#define ADC_DEVS (1U) #define ADC_DEVS (1U)
#elif defined(CPU_MODEL_STM32F407VG) || defined(CPU_MODEL_STM32F415RG) || defined(CPU_MODEL_STM32F446RE) #elif defined(CPU_MODEL_STM32F407VG) || defined(CPU_MODEL_STM32F415RG) || defined(CPU_MODEL_STM32F446RE)
#define ADC_DEVS (3U) #define ADC_DEVS (3U)

3995
cpu/stm32f4/include/vendor/stm32f410rx.h vendored Normal file
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File diff suppressed because it is too large Load Diff

32
cpu/stm32f4/ldscripts/stm32f410rb.ld Normal file
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@ -0,0 +1,32 @@
/*
* Copyright (C) 2016 Freie Universität Berlin
* 2016 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32f4
* @{
*
* @file
* @brief Memory definitions for the STM32F410RB
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

8
cpu/stm32f4/periph/hwrng.c
View File

@ -36,7 +36,11 @@ void hwrng_read(void *buf, unsigned int num)
uint8_t *b = (uint8_t *)buf; uint8_t *b = (uint8_t *)buf;
/* power on and enable the device */ /* power on and enable the device */
#if defined(CPU_MODEL_STM32F410RB)
periph_clk_en(AHB1, RCC_AHB1ENR_RNGEN);
#else
periph_clk_en(AHB2, RCC_AHB2ENR_RNGEN); periph_clk_en(AHB2, RCC_AHB2ENR_RNGEN);
#endif
RNG->CR = RNG_CR_RNGEN; RNG->CR = RNG_CR_RNGEN;
/* get random data */ /* get random data */
@ -54,7 +58,11 @@ void hwrng_read(void *buf, unsigned int num)
/* finally disable the device again */ /* finally disable the device again */
RNG->CR = 0; RNG->CR = 0;
#if defined(CPU_MODEL_STM32F410RB)
periph_clk_dis(AHB1, RCC_AHB1ENR_RNGEN);
#else
periph_clk_dis(AHB2, RCC_AHB2ENR_RNGEN); periph_clk_dis(AHB2, RCC_AHB2ENR_RNGEN);
#endif
} }
#endif /* RNG */ #endif /* RNG */