From 97942ddbe63df0b2a4f46fda1f8b0a19e4eaa5cc Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Tue, 26 May 2020 14:52:32 +0200 Subject: [PATCH 1/3] cpu/stm32: adapt gpio driver to default CMSIS exti structure --- cpu/stm32/periph/gpio_all.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/cpu/stm32/periph/gpio_all.c b/cpu/stm32/periph/gpio_all.c index 439345a138..db0f45cebb 100644 --- a/cpu/stm32/periph/gpio_all.c +++ b/cpu/stm32/periph/gpio_all.c @@ -43,6 +43,18 @@ static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF]; #endif /* MODULE_PERIPH_GPIO_IRQ */ +#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) +#define EXTI_REG_RTSR (EXTI->RTSR1) +#define EXTI_REG_FTSR (EXTI->FTSR1) +#define EXTI_REG_PR (EXTI->PR1) +#define EXTI_REG_IMR (EXTI->IMR1) +#else +#define EXTI_REG_RTSR (EXTI->RTSR) +#define EXTI_REG_FTSR (EXTI->FTSR) +#define EXTI_REG_PR (EXTI->PR) +#define EXTI_REG_IMR (EXTI->IMR) +#endif + /** * @brief Extract the port base address from the given pin identifier */ @@ -140,12 +152,12 @@ void gpio_init_analog(gpio_t pin) void gpio_irq_enable(gpio_t pin) { - EXTI->IMR |= (1 << _pin_num(pin)); + EXTI_REG_IMR |= (1 << _pin_num(pin)); } void gpio_irq_disable(gpio_t pin) { - EXTI->IMR &= ~(1 << _pin_num(pin)); + EXTI_REG_IMR &= ~(1 << _pin_num(pin)); } int gpio_read(gpio_t pin) @@ -227,28 +239,28 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, } #endif /* configure the active flank */ - EXTI->RTSR &= ~(1 << pin_num); - EXTI->RTSR |= ((flank & 0x1) << pin_num); - EXTI->FTSR &= ~(1 << pin_num); - EXTI->FTSR |= ((flank >> 1) << pin_num); + EXTI_REG_RTSR &= ~(1 << pin_num); + EXTI_REG_RTSR |= ((flank & 0x1) << pin_num); + EXTI_REG_FTSR &= ~(1 << pin_num); + EXTI_REG_FTSR |= ((flank >> 1) << pin_num); /* enable specific pin as exti sources */ SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4)); SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4)); /* clear any pending requests */ - EXTI->PR = (1 << pin_num); + EXTI_REG_PR = (1 << pin_num); /* unmask the pins interrupt channel */ - EXTI->IMR |= (1 << pin_num); + EXTI_REG_IMR |= (1 << pin_num); return 0; } void isr_exti(void) { /* only generate interrupts against lines which have their IMR set */ - uint32_t pending_isr = (EXTI->PR & EXTI->IMR); + uint32_t pending_isr = (EXTI_REG_PR & EXTI_REG_IMR); for (size_t i = 0; i < EXTI_NUMOF; i++) { if (pending_isr & (1 << i)) { - EXTI->PR = (1 << i); /* clear by writing a 1 */ + EXTI_REG_PR = (1 << i); /* clear by writing a 1 */ isr_ctx[i].cb(isr_ctx[i].arg); } } From 09c1afe9c5bd7332ff2431231508e6a9a0dad55b Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Tue, 26 May 2020 14:52:51 +0200 Subject: [PATCH 2/3] cpu/stm32l4/wb: restore exti structure in vendor headers --- cpu/stm32/include/vendor/stm32l412xx.h | 12 ++++++------ cpu/stm32/include/vendor/stm32l432xx.h | 14 +++++++------- cpu/stm32/include/vendor/stm32l433xx.h | 12 ++++++------ cpu/stm32/include/vendor/stm32l452xx.h | 12 ++++++------ cpu/stm32/include/vendor/stm32l475xx.h | 12 ++++++------ cpu/stm32/include/vendor/stm32l476xx.h | 14 +++++++------- cpu/stm32/include/vendor/stm32l496xx.h | 14 +++++++------- cpu/stm32/include/vendor/stm32l4r5xx.h | 12 ++++++------ cpu/stm32/include/vendor/stm32wb55xx.h | 12 ++++++------ 9 files changed, 57 insertions(+), 57 deletions(-) diff --git a/cpu/stm32/include/vendor/stm32l412xx.h b/cpu/stm32/include/vendor/stm32l412xx.h index e4efe61de3..a3e4b4c704 100644 --- a/cpu/stm32/include/vendor/stm32l412xx.h +++ b/cpu/stm32/include/vendor/stm32l412xx.h @@ -292,12 +292,12 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register 1, Address offset: 0x14 */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ diff --git a/cpu/stm32/include/vendor/stm32l432xx.h b/cpu/stm32/include/vendor/stm32l432xx.h index 3d2eac902d..aa19a55621 100644 --- a/cpu/stm32/include/vendor/stm32l432xx.h +++ b/cpu/stm32/include/vendor/stm32l432xx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral�s registers hardware * ****************************************************************************** * @attention @@ -404,12 +404,12 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register 1, Address offset: 0x14 */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ diff --git a/cpu/stm32/include/vendor/stm32l433xx.h b/cpu/stm32/include/vendor/stm32l433xx.h index 2b23d0e4df..9e5c01f80d 100644 --- a/cpu/stm32/include/vendor/stm32l433xx.h +++ b/cpu/stm32/include/vendor/stm32l433xx.h @@ -410,12 +410,12 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register 1, Address offset: 0x14 */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ diff --git a/cpu/stm32/include/vendor/stm32l452xx.h b/cpu/stm32/include/vendor/stm32l452xx.h index e013a9103f..a6cc7cfe09 100644 --- a/cpu/stm32/include/vendor/stm32l452xx.h +++ b/cpu/stm32/include/vendor/stm32l452xx.h @@ -445,12 +445,12 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register 1, Address offset: 0x14 */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ diff --git a/cpu/stm32/include/vendor/stm32l475xx.h b/cpu/stm32/include/vendor/stm32l475xx.h index ec1a289461..336ce6d7ab 100644 --- a/cpu/stm32/include/vendor/stm32l475xx.h +++ b/cpu/stm32/include/vendor/stm32l475xx.h @@ -447,12 +447,12 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register 1, Address offset: 0x14 */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ diff --git a/cpu/stm32/include/vendor/stm32l476xx.h b/cpu/stm32/include/vendor/stm32l476xx.h index 7815551e25..57c2370d6f 100644 --- a/cpu/stm32/include/vendor/stm32l476xx.h +++ b/cpu/stm32/include/vendor/stm32l476xx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral�s registers hardware * ****************************************************************************** * @attention @@ -448,12 +448,12 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR ; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register 1, Address offset: 0x14 */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ diff --git a/cpu/stm32/include/vendor/stm32l496xx.h b/cpu/stm32/include/vendor/stm32l496xx.h index b656d9511a..9c7db98934 100644 --- a/cpu/stm32/include/vendor/stm32l496xx.h +++ b/cpu/stm32/include/vendor/stm32l496xx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral�s registers hardware * ****************************************************************************** * @attention @@ -517,12 +517,12 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register 1, Address offset: 0x14 */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ diff --git a/cpu/stm32/include/vendor/stm32l4r5xx.h b/cpu/stm32/include/vendor/stm32l4r5xx.h index 9c75424da9..6fc2a0a4e7 100644 --- a/cpu/stm32/include/vendor/stm32l4r5xx.h +++ b/cpu/stm32/include/vendor/stm32l4r5xx.h @@ -527,12 +527,12 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register 1, Address offset: 0x14 */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ diff --git a/cpu/stm32/include/vendor/stm32wb55xx.h b/cpu/stm32/include/vendor/stm32wb55xx.h index 0abfb5ebd3..dc84c9713d 100644 --- a/cpu/stm32/include/vendor/stm32wb55xx.h +++ b/cpu/stm32/include/vendor/stm32wb55xx.h @@ -819,10 +819,10 @@ typedef struct */ typedef struct { - __IO uint32_t RTSR; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ - __IO uint32_t FTSR; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ - __IO uint32_t SWIER; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ - __IO uint32_t PR; /*!< EXTI pending register [31:0], Address offset: 0x0C */ + __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ + __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ @@ -831,8 +831,8 @@ typedef struct __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ - __IO uint32_t IMR; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t EMR; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ From c40f0a79bfbb41138c4f7d0b4c03ac98081a2040 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Tue, 26 May 2020 17:29:37 +0200 Subject: [PATCH 3/3] cpu/stm32: adapt rtc driver to default CMSIS exti structure --- cpu/stm32/periph/rtc_all.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/cpu/stm32/periph/rtc_all.c b/cpu/stm32/periph/rtc_all.c index da909e4f29..f06b43342d 100644 --- a/cpu/stm32/periph/rtc_all.c +++ b/cpu/stm32/periph/rtc_all.c @@ -42,6 +42,19 @@ #define CLKSEL_LSI (RCC_BDCR_RTCSEL_1) #endif +/* map some EXTI register names */ +#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) +#define EXTI_REG_RTSR (EXTI->RTSR1) +#define EXTI_REG_FTSR (EXTI->FTSR1) +#define EXTI_REG_PR (EXTI->PR1) +#define EXTI_REG_IMR (EXTI->IMR1) +#else +#define EXTI_REG_RTSR (EXTI->RTSR) +#define EXTI_REG_FTSR (EXTI->FTSR) +#define EXTI_REG_PR (EXTI->PR) +#define EXTI_REG_IMR (EXTI->IMR) +#endif + /* interrupt line name mapping */ #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) #define IRQN (RTC_IRQn) @@ -231,10 +244,10 @@ void rtc_init(void) /* configure the EXTI channel, as RTC interrupts are routed through it. * Needs to be configured to trigger on rising edges. */ - EXTI->FTSR &= ~(EXTI_FTSR_BIT); - EXTI->RTSR |= EXTI_RTSR_BIT; - EXTI->IMR |= EXTI_IMR_BIT; - EXTI->PR = EXTI_PR_BIT; + EXTI_REG_FTSR &= ~(EXTI_FTSR_BIT); + EXTI_REG_RTSR |= EXTI_RTSR_BIT; + EXTI_REG_IMR |= EXTI_IMR_BIT; + EXTI_REG_PR = EXTI_PR_BIT; /* enable global RTC interrupt */ NVIC_EnableIRQ(IRQN); } @@ -348,6 +361,6 @@ void ISR_NAME(void) } RTC->ISR &= ~RTC_ISR_ALRAF; } - EXTI->PR = EXTI_PR_BIT; /* only clear the associated bit */ + EXTI_REG_PR = EXTI_PR_BIT; /* only clear the associated bit */ cortexm_isr_end(); }