boards: added SPI definitions for NRF based boards
added SPI defines for - yunjia-nrf51822 - pca10005 - airfy-beacon
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@ -1,3 +1,4 @@
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FEATURES_PROVIDED += cpp
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FEATURES_PROVIDED += periph_uart periph_gpio periph_random periph_rtt periph_cpuid
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FEATURES_PROVIDED += periph_uart periph_gpio periph_random periph_rtt \
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periph_cpuid periph_spi
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FEATURES_MCU_GROUP = cortex_m0
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@ -108,6 +108,21 @@
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#define RANDOM_NUMOF (1U)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (1U)
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#define SPI_0_EN 1
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#define SPI_IRQ_PRIO 1
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/* SPI_0 device configuration */
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#define SPI_0_DEV NRF_SPI0
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#define SPI_0_PIN_MOSI 13
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#define SPI_0_PIN_MISO 14
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#define SPI_0_PIN_SCK 15
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/** @} */
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/**
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* @name GPIO configuration
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* @{
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@ -1,3 +1,4 @@
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FEATURES_PROVIDED += cpp
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FEATURES_PROVIDED += periph_uart periph_gpio periph_random periph_rtt periph_cpuid
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FEATURES_PROVIDED += periph_uart periph_gpio periph_random periph_rtt \
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periph_cpuid periph_spi
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FEATURES_MCU_GROUP = cortex_m0
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@ -108,6 +108,28 @@ extern "C" {
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#define RANDOM_NUMOF (1U)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (2U)
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#define SPI_0_EN 1
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#define SPI_1_EN 1
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#define SPI_IRQ_PRIO 1
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/* SPI_0 device configuration */
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#define SPI_0_DEV NRF_SPI0
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#define SPI_0_PIN_MOSI 17
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#define SPI_0_PIN_MISO 18
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#define SPI_0_PIN_SCK 19
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/* SPI_1 device configuration */
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#define SPI_1_DEV NRF_SPI1
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#define SPI_1_PIN_MOSI 20
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#define SPI_1_PIN_MISO 21
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#define SPI_1_PIN_SCK 22
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/** @} */
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/**
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* @name GPIO configuration
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* @{
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@ -1,3 +1,4 @@
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FEATURES_PROVIDED += cpp
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FEATURES_PROVIDED += periph_uart periph_gpio periph_random periph_rtt periph_cpuid
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FEATURES_PROVIDED += periph_uart periph_gpio periph_random periph_rtt \
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periph_cpuid periph_spi
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FEATURES_MCU_GROUP = cortex_m0
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@ -106,6 +106,29 @@ extern "C" {
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#define RANDOM_NUMOF (1U)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (2U)
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#define SPI_0_EN 1
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#define SPI_1_EN 1
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#define SPI_IRQ_PRIO 1
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/* SPI_0 device configuration */
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#define SPI_0_DEV NRF_SPI0
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#define SPI_0_PIN_MOSI 17
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#define SPI_0_PIN_MISO 18
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#define SPI_0_PIN_SCK 19
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/* SPI_1 device configuration */
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#define SPI_1_DEV NRF_SPI1
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#define SPI_1_PIN_MOSI 20
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#define SPI_1_PIN_MISO 21
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#define SPI_1_PIN_SCK 22
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/** @} */
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/**
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* @name GPIO configuration
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* @{
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