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Merge pull request #8769 from OTAkeys/pr/ublox-c030

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boards: add Ublox C030-U201
This commit is contained in:
Alexandre Abadie 2018-05-24 17:03:50 +02:00 committed by GitHub
commit 3738acb062
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GPG Key ID: 4AEE18F83AFDEB23
14 changed files with 17768 additions and 6 deletions
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3
boards/ublox-c030-u201/Makefile Normal file
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MODULE = board
include $(RIOTBASE)/Makefile.base

10
boards/ublox-c030-u201/Makefile.dep Normal file
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USEMODULE += stm32_periph_uart_hw_fc
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
# USEMODULE += si7034 # TODO: add when si70xx driver is updated
endif
ifneq (,$(filter vfs,$(USEMODULE)))
USEMODULE += mtd_sdcard
endif

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boards/ublox-c030-u201/Makefile.features Normal file
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# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_3
-include $(RIOTCPU)/stm32f4/Makefile.features

16
boards/ublox-c030-u201/Makefile.include Normal file
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## the cpu to build for
export CPU = stm32f4
export CPU_MODEL = stm32f437vg
# define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk
export DEBUG_ADAPTER ?= stlink
export STLINK_VERSION ?= 2-1
# this board uses openocd
include $(RIOTMAKE)/tools/openocd.inc.mk

32
boards/ublox-c030-u201/board.c Normal file
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/*
* Copyright (C) 2018 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_ublox-c030-u201
* @{
*
* @file
* @brief Board specific implementations for the Ublox C030-U201 board
*
* @author Vincent Dupont <vincent@otakeys.com>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU */
cpu_init();
gpio_init(LED0_PIN, GPIO_OUT);
gpio_init(LED1_PIN, GPIO_OUT);
gpio_init(LED2_PIN, GPIO_OUT);
}

3
boards/ublox-c030-u201/dist/openocd.cfg vendored Normal file
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source [find target/stm32f4x.cfg]
reset_config srst_only
$_TARGETNAME configure -rtos auto

80
boards/ublox-c030-u201/include/arduino_pinmap.h Normal file
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/*
* Copyright (C) 2018 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_ublox-c030-u201
* @{
*
* @file
* @brief Mapping from MCU pins to Arduino pins
*
* You can use the defines in this file for simplified interaction with the
* Arduino specific pin numbers.
*
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef ARDUINO_PINMAP_H
#define ARDUINO_PINMAP_H
#include "periph/gpio.h"
#include "periph/adc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Mapping of MCU pins to Arduino pins
* @{
*/
#define ARDUINO_PIN_0 GPIO_PIN(PORT_D, 9)
#define ARDUINO_PIN_1 GPIO_PIN(PORT_D, 8)
#define ARDUINO_PIN_2 GPIO_PIN(PORT_D, 11)
#define ARDUINO_PIN_3 GPIO_PIN(PORT_B, 14)
#define ARDUINO_PIN_4 GPIO_PIN(PORT_B, 1)
#define ARDUINO_PIN_5 GPIO_PIN(PORT_A, 5)
#define ARDUINO_PIN_6 GPIO_PIN(PORT_B, 8)
#define ARDUINO_PIN_7 GPIO_PIN(PORT_B, 15)
#define ARDUINO_PIN_8 GPIO_PIN(PORT_D, 15)
#define ARDUINO_PIN_9 GPIO_PIN(PORT_D, 12)
#define ARDUINO_PIN_10 GPIO_PIN(PORT_E, 11)
#define ARDUINO_PIN_11 GPIO_PIN(PORT_E, 6)
#define ARDUINO_PIN_12 GPIO_PIN(PORT_E, 5)
#define ARDUINO_PIN_13 GPIO_PIN(PORT_E, 2)
#define ARDUINO_PIN_14 GPIO_PIN(PORT_B, 7)
#define ARDUINO_PIN_15 GPIO_PIN(PORT_B, 6)
#define ARDUINO_PIN_A0 GPIO_PIN(PORT_A, 3)
#define ARDUINO_PIN_A1 GPIO_PIN(PORT_C, 0)
#define ARDUINO_PIN_A2 GPIO_PIN(PORT_C, 3)
#define ARDUINO_PIN_A3 GPIO_PIN(PORT_A, 4)
#define ARDUINO_PIN_A4 GPIO_PIN(PORT_B, 7)
#define ARDUINO_PIN_A5 GPIO_PIN(PORT_B, 6)
/** @ */
/**
* @name Mapping of Arduino analog pins to RIOT ADC lines
* @{
*/
#define ARDUINO_A0 ADC_LINE(0)
#define ARDUINO_A1 ADC_LINE(1)
#define ARDUINO_A2 ADC_LINE(2)
#define ARDUINO_A3 ADC_LINE(3)
#define ARDUINO_A4 ADC_LINE(4)
#define ARDUINO_A5 ADC_LINE(5)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* ARDUINO_PINMAP_H */
/** @} */

105
boards/ublox-c030-u201/include/board.h Normal file
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/*
* Copyright (C) 2018 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_ublox-c030-u201 Ublox C030-U201
* @ingroup boards
* @brief Support for the Ublox C030-U201 board
* @{
*
* @file
* @brief Board specific definitions for the Ublox C030-U201 board
*
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef BOARD_H
#define BOARD_H
#include <stdint.h>
#include "cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name LED pin definitions and handlers
* @{
*/
#define LED0_PIN GPIO_PIN(PORT_E, 3)
#define LED0_MASK (1 << 3)
#define LED0_ON (GPIOE->BSRR = LED0_MASK)
#define LED0_OFF (GPIOE->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (GPIOE->ODR ^= LED0_MASK)
#define LED1_PIN GPIO_PIN(PORT_E, 4)
#define LED1_MASK (1 << 4)
#define LED1_ON (GPIOE->BSRR = LED1_MASK)
#define LED1_OFF (GPIOE->BSRR = (LED1_MASK << 16))
#define LED1_TOGGLE (GPIOE->ODR ^= LED1_MASK)
#define LED2_PIN GPIO_PIN(PORT_E, 1)
#define LED2_MASK (1 << 1)
#define LED2_ON (GPIOE->BSRR = LED2_MASK)
#define LED2_OFF (GPIOE->BSRR = (LED2_MASK << 16))
#define LED2_TOGGLE (GPIOE->ODR ^= LED2_MASK)
/** @} */
/**
* @brief User button
*/
#define BTN_B1_PIN GPIO_PIN(PORT_C, 13)
/**
* @name si7034 temperature sensor configuration
* TODO: Check this when support is added in si70xx driver
* @{
*/
#define SI70XX_PARAM_I2C_DEV I2C_DEV(1)
#define SI70XX_PARAM_ADDR (0x70)
#define SI70XX_SAUL_INFO { .name = "si7034" }
/** @} */
/**
* @name SDCard configuration
* @{
*/
#define SDCARD_SPI_PARAM_SPI SPI_DEV(0)
#define SDCARD_SPI_PARAM_CS GPIO_PIN(PORT_E, 11)
#define SDCARD_SPI_PARAM_CLK GPIO_PIN(PORT_E, 2)
#define SDCARD_SPI_PARAM_MOSI GPIO_PIN(PORT_E, 6)
#define SDCARD_SPI_PARAM_MISO GPIO_PIN(PORT_E, 5)
/** @} */
/**
* @name Modem/GPS pins
* @{
*/
#define UB_PWRON_PIN GPIO_PIN(PORT_E, 14)
#define UB_M_RST_PIN GPIO_PIN(PORT_B, 5)
#define M_GPIO2_PIN GPIO_PIN(PORT_D, 1)
#define M_GPIO3_PIN GPIO_PIN(PORT_B, 4)
#define GPS_RST_PIN GPIO_PIN(PORT_C, 10) /* Not connected */
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

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boards/ublox-c030-u201/include/gpio_params.h Normal file
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/*
* Copyright (C) 2018 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_ublox-c030-u201
* @{
*
* @file
* @brief Board specific configuration of direct mapped GPIOs
*
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO pin configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LD1(red)",
.pin = LED0_PIN,
.mode = GPIO_OUT,
.flags = SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR,
},
{
.name = "LD2(green)",
.pin = LED1_PIN,
.mode = GPIO_OUT,
.flags = SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR,
},
{
.name = "LD3(blue)",
.pin = LED2_PIN,
.mode = GPIO_OUT,
.flags = SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR,
},
{
.name = "Button(B1 User)",
.pin = BTN_B1_PIN,
.mode = GPIO_IN,
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

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boards/ublox-c030-u201/include/periph_conf.h Normal file
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/*
* Copyright (C) 2018 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_ublox-c030-u201
* @{
*
* @file
* @brief Peripheral MCU configuration for the Ublox C030-U201 board
*
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 180MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (12000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM5,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM5EN,
.bus = APB1,
.irqn = TIM5_IRQn
}
};
#define TIMER_0_ISR isr_tim5
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn,
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
.cts_pin = GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_af = GPIO_AF7,
.rts_af = GPIO_AF7,
#endif
},
{ /* Modem UART */
.dev = USART2,
.rcc_mask = RCC_APB1ENR_USART2EN,
.rx_pin = GPIO_PIN(PORT_D, 6),
.tx_pin = GPIO_PIN(PORT_D, 5),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART2_IRQn,
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
.cts_pin = GPIO_PIN(PORT_D, 3),
.rts_pin = GPIO_PIN(PORT_D, 4),
.cts_af = GPIO_AF7,
.rts_af = GPIO_AF7,
#endif
},
{ /* GPS UART */
.dev = USART6,
.rcc_mask = RCC_APB2ENR_USART6EN,
.rx_pin = GPIO_PIN(PORT_C, 7),
.tx_pin = GPIO_PIN(PORT_C, 6),
.rx_af = GPIO_AF8,
.tx_af = GPIO_AF8,
.bus = APB2,
.irqn = USART6_IRQn,
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
.cts_pin = GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_af = GPIO_AF8,
.rts_af = GPIO_AF8,
#endif
},
{ /* Arduino Port UART */
.dev = USART3,
.rcc_mask = RCC_APB1ENR_USART3EN,
.rx_pin = GPIO_PIN(PORT_D, 9),
.tx_pin = GPIO_PIN(PORT_D, 8),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART3_IRQn,
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
.cts_pin = GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_af = GPIO_AF7,
.rts_af = GPIO_AF7,
#endif
},
};
#define UART_0_ISR (isr_usart1)
#define UART_1_ISR (isr_usart2)
#define UART_2_ISR (isr_usart6)
#define UART_3_ISR (isr_usart3)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI4,
.mosi_pin = GPIO_PIN(PORT_E, 6),
.miso_pin = GPIO_PIN(PORT_E, 5),
.sclk_pin = GPIO_PIN(PORT_E, 2),
.cs_pin = GPIO_PIN(PORT_E, 11),
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI4EN,
.apbbus = APB2
},
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name I2C configuration
* @{
*/
#define I2C_0_EN 1
#define I2C_1_EN 1
#define I2C_NUMOF 2
#define I2C_IRQ_PRIO 1
#define I2C_APBCLK (CLOCK_APB1)
/* I2C 0 device configuration */
#define I2C_0_DEV I2C1
#define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
#define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
#define I2C_0_EVT_IRQ I2C1_EV_IRQn
#define I2C_0_EVT_ISR isr_i2c1_ev
#define I2C_0_ERR_IRQ I2C1_ER_IRQn
#define I2C_0_ERR_ISR isr_i2c1_er
/* I2C 0 pin configuration */
#define I2C_0_SCL_PORT GPIOB
#define I2C_0_SCL_PIN 6
#define I2C_0_SCL_AF 4
#define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
#define I2C_0_SDA_PORT GPIOB
#define I2C_0_SDA_PIN 7
#define I2C_0_SDA_AF 4
#define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
/* I2C 1 device configuration */
#define I2C_1_DEV I2C3
#define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
#define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
#define I2C_1_EVT_IRQ I2C3_EV_IRQn
#define I2C_1_EVT_ISR isr_i2c3_ev
#define I2C_1_ERR_IRQ I2C3_ER_IRQn
#define I2C_1_ERR_ISR isr_i2c3_er
/* I2C 1 pin configuration */
#define I2C_1_SCL_PORT GPIOA
#define I2C_1_SCL_PIN 8
#define I2C_1_SCL_AF 4
#define I2C_1_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
#define I2C_1_SDA_PORT GPIOC
#define I2C_1_SDA_PIN 9
#define I2C_1_SDA_AF 4
#define I2C_1_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOCEN))
/** @} */
/**
* @name ADC configuration
*
* Note that we do not configure all ADC channels,
* and not in the STM32F437 order. Instead, we
* just define 6 ADC channels, for the
* Arduino header pins A0-A5
*
* @{
*/
#define ADC_NUMOF (6U)
#define ADC_CONFIG { \
{GPIO_PIN(PORT_A, 3), 0, 3}, \
{GPIO_PIN(PORT_C, 0), 0, 10}, \
{GPIO_PIN(PORT_C, 3), 0, 4}, \
{GPIO_PIN(PORT_A, 4), 0, 14}, \
{GPIO_PIN(PORT_B, 7), 0, 7}, \
{GPIO_PIN(PORT_B, 6), 0, 6}, \
}
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1U)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

10
cpu/stm32f4/include/cpu_conf.h
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@ -1,5 +1,6 @@
/* /*
* Copyright (C) 2014 Freie Universität Berlin * Copyright (C) 2014 Freie Universität Berlin
* 2048 OTA keys S.A.
* *
* This file is subject to the terms and conditions of the GNU Lesser General * This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more * Public License v2.1. See the file LICENSE in the top level directory for more
@ -16,6 +17,7 @@
* @brief Implementation specific CPU configuration options * @brief Implementation specific CPU configuration options
* *
* @author Hauke Petersen <hauke.petersen@fu-berlin.de> * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com>
*/ */
#ifndef CPU_CONF_H #ifndef CPU_CONF_H
@ -45,10 +47,12 @@
|| defined(CPU_MODEL_STM32F423MH) || defined(CPU_MODEL_STM32F423VH) \ || defined(CPU_MODEL_STM32F423MH) || defined(CPU_MODEL_STM32F423VH) \
|| defined(CPU_MODEL_STM32F423ZH) || defined(CPU_MODEL_STM32F423ZH)
#include "vendor/stm32f423xx.h" #include "vendor/stm32f423xx.h"
#elif defined(CPU_MODEL_STM32F446RE) || defined(CPU_MODEL_STM32F446ZE)
#include "vendor/stm32f446xx.h"
#elif defined(CPU_MODEL_STM32F429ZI) #elif defined(CPU_MODEL_STM32F429ZI)
#include "vendor/stm32f429xx.h" #include "vendor/stm32f429xx.h"
#elif defined(CPU_MODEL_STM32F437VG)
#include "vendor/stm32f437xx.h"
#elif defined(CPU_MODEL_STM32F446RE) || defined(CPU_MODEL_STM32F446ZE)
#include "vendor/stm32f446xx.h"
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
@ -80,7 +84,7 @@ extern "C" {
|| defined(CPU_MODEL_STM32F423MH) || defined(CPU_MODEL_STM32F423VH) \ || defined(CPU_MODEL_STM32F423MH) || defined(CPU_MODEL_STM32F423VH) \
|| defined(CPU_MODEL_STM32F423ZH) || defined(CPU_MODEL_STM32F423ZH)
#define CPU_IRQ_NUMOF (102U) #define CPU_IRQ_NUMOF (102U)
#elif defined(CPU_MODEL_STM32F429ZI) #elif defined(CPU_MODEL_STM32F429ZI) || defined(CPU_MODEL_STM32F437VG)
#define CPU_IRQ_NUMOF (91U) #define CPU_IRQ_NUMOF (91U)
#endif #endif
#define CPU_FLASH_BASE FLASH_BASE #define CPU_FLASH_BASE FLASH_BASE

4
cpu/stm32f4/include/periph_cpu.h
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@ -60,8 +60,8 @@ enum {
|| defined(CPU_MODEL_STM32F423ZH) || defined(CPU_MODEL_STM32F423ZH)
#define ADC_DEVS (1U) #define ADC_DEVS (1U)
#elif defined(CPU_MODEL_STM32F407VG) || defined(CPU_MODEL_STM32F415RG) \ #elif defined(CPU_MODEL_STM32F407VG) || defined(CPU_MODEL_STM32F415RG) \
|| defined(CPU_MODEL_STM32F429ZI) || defined(CPU_MODEL_STM32F446RE) \ || defined(CPU_MODEL_STM32F429ZI) || defined(CPU_MODEL_STM32F437VG) \
|| defined(CPU_MODEL_STM32F446ZE) || defined(CPU_MODEL_STM32F446RE) || defined(CPU_MODEL_STM32F446ZE)
#define ADC_DEVS (3U) #define ADC_DEVS (3U)
#endif #endif

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cpu/stm32f4/include/vendor/stm32f437xx.h vendored Normal file
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48
cpu/stm32f4/vectors.c
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@ -1,6 +1,6 @@
/* /*
* Copyright (C) 2014-2017 Freie Universität Berlin * Copyright (C) 2014-2017 Freie Universität Berlin
* 2017 OTA keys S.A. * 2017-2018 OTA keys S.A.
* *
* This file is subject to the terms and conditions of the GNU Lesser General * This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more * Public License v2.1. See the file LICENSE in the top level directory for more
@ -485,6 +485,52 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[88] = isr_ltdc, /* [88] LTDC global Interrupt */ [88] = isr_ltdc, /* [88] LTDC global Interrupt */
[89] = isr_ltdc_er, /* [89] LTDC Error global Interrupt */ [89] = isr_ltdc_er, /* [89] LTDC Error global Interrupt */
[90] = isr_dma2d, /* [90] DMA2D global Interrupt */ [90] = isr_dma2d, /* [90] DMA2D global Interrupt */
#elif defined(CPU_MODEL_STM32F437VG)
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
[19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */
[20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */
[21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */
[22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */
[25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */
[28] = isr_tim2, /* [28] TIM2 global Interrupt */
[29] = isr_tim3, /* [29] TIM3 global Interrupt */
[30] = isr_tim4, /* [30] TIM4 global Interrupt */
[39] = isr_usart3, /* [39] USART3 global Interrupt */
[42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */
[43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */
[44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */
[45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
[46] = isr_tim8_cc, /* [46] TIM8 Capture Compare global interrupt */
[48] = isr_fmc, /* [48] FMC global Interrupt */
[49] = isr_sdio, /* [49] SDIO global Interrupt */
[51] = isr_spi3, /* [51] SPI3 global Interrupt */
[52] = isr_uart4, /* [52] UART4 global Interrupt */
[53] = isr_uart5, /* [53] UART5 global Interrupt */
[54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */
[55] = isr_tim7, /* [55] TIM7 global interrupt */
[61] = isr_eth, /* [61] Ethernet global Interrupt */
[62] = isr_eth_wkup, /* [62] Ethernet Wakeup through EXTI line Interrupt */
[63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */
[64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */
[65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */
[66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */
[67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */
[72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */
[73] = isr_i2c3_er, /* [73] I2C3 error interrupt */
[74] = isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out global interrupt */
[75] = isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In global interrupt */
[76] = isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */
[77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */
[78] = isr_dcmi, /* [78] DCMI global interrupt */
[79] = isr_cryp, /* [79] CRYP crypto global interrupt */
[80] = isr_hash_rng, /* [80] Hash and Rng global interrupt */
[82] = isr_uart7, /* [82] UART7 global interrupt */
[83] = isr_uart8, /* [83] UART8 global interrupt */
[84] = isr_spi4, /* [84] SPI4 global Interrupt */
[85] = isr_spi5, /* [85] SPI5 global Interrupt */
[86] = isr_spi6, /* [86] SPI6 global Interrupt */
[87] = isr_sai1, /* [87] SAI1 global Interrupt */
[90] = isr_dma2d, /* [90] DMA2D global Interrupt */
#elif defined(CPU_MODEL_STM32F446RE) || defined(CPU_MODEL_STM32F446ZE) #elif defined(CPU_MODEL_STM32F446RE) || defined(CPU_MODEL_STM32F446ZE)
[18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */
[19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */