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boards/ublox-c030-u201: use common timer configuration

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This also requires to include the STM32 shared include directory
This commit is contained in:
Alexandre Abadie 2019-07-05 19:29:48 +02:00
parent 27230c7c10
commit 3c00d41764
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GPG Key ID: 1C919A403CAE1405
2 changed files with 4 additions and 19 deletions
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3
boards/ublox-c030-u201/Makefile.include
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@ -2,6 +2,9 @@
export CPU = stm32f4 export CPU = stm32f4
export CPU_MODEL = stm32f437vg export CPU_MODEL = stm32f437vg
# we use shared STM32 configuration snippets
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# define the default port depending on the host OS # define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyACM0 PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*))) PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))

20
boards/ublox-c030-u201/include/periph_conf.h
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@ -20,6 +20,7 @@
#define PERIPH_CONF_H #define PERIPH_CONF_H
#include "periph_cpu.h" #include "periph_cpu.h"
#include "cfg_timer_tim5.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -56,25 +57,6 @@ extern "C" {
#define CLOCK_PLL_Q (7) #define CLOCK_PLL_Q (7)
/** @} */ /** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM5,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM5EN,
.bus = APB1,
.irqn = TIM5_IRQn
}
};
#define TIMER_0_ISR isr_tim5
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/** /**
* @name UART configuration * @name UART configuration
* @{ * @{