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cpu/saml21: adapted to centralized cpu conf

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This commit is contained in:
Hauke Petersen 2015-05-27 23:07:10 +02:00
parent 4d3b147122
commit 3c48722e0f
3 changed files with 11 additions and 37 deletions
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4
cpu/saml21/cpu.c
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@ -28,8 +28,8 @@ void cpu_init(void)
/* disable the watchdog timer */
WDT->CTRLA.bit.ENABLE = 0;
/* set pendSV interrupt to lowest possible priority */
NVIC_SetPriority(PendSV_IRQn, 0xff);
/* initialize the Cortex-M core */
cortexm_init();
/* turn on MCLK */
MCLK->APBAMASK.reg |= MCLK_APBAMASK_GCLK;

38
cpu/saml21/include/cpu_conf.h
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@ -18,36 +18,19 @@
#ifndef __CPU_CONF_H
#define __CPU_CONF_H
#include "atmel/saml21.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "atmel/saml21.h"
/**
* @name Kernel configuration
*
* TODO: measure and adjust for the cortex-m0
* @brief ARM Cortex-M specific CPU configuration
* @{
*/
#define THREAD_EXTRA_STACKSIZE_PRINTF (512)
#ifndef THREAD_STACKSIZE_DEFAULT
#define THREAD_STACKSIZE_DEFAULT (1024)
#endif
#define THREAD_STACKSIZE_IDLE (256)
/** @} */
/**
* @name UART0 buffer size definition for compatibility reasons
*
* TODO: remove once the remodeling of the uart0 driver is done
* @{
*/
#ifndef UART0_BUFSIZE
#define UART0_BUFSIZE (128)
#endif
#define CPU_DEFAULT_IRQ_PRIO (1U)
#define CPU_IRQ_NUMOF PERIPH_COUNT_IRQn
#define CPU_FLASH_BASE FLASH_ADDR
/** @} */
/**
@ -55,15 +38,6 @@ extern "C" {
*/
#define CPUID_ID_LEN (16) /* 128 bits long, 16 bytes long */
/**
* @brief Definition of different panic modes
*/
typedef enum {
NMI_HANDLER, /**< non maskable interrupt */
HARD_FAULT, /**< hard fault */
DUMMY_HANDLER /**< dummy interrupt handler */
} panic_t;
#ifdef __cplusplus
}
#endif

6
cpu/saml21/startup.c
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@ -82,12 +82,12 @@ void reset_handler(void)
void isr_nmi(void)
{
core_panic(NMI_HANDLER, "NMI HANDLER");
core_panic(PANIC_NMI_HANDLER, "NMI HANDLER");
}
void isr_hard_fault(void)
{
core_panic(HARD_FAULT, "HARD FAULT");
core_panic(PANIC_HARD_FAULT, "HARD FAULT");
}
/**
@ -95,7 +95,7 @@ void isr_hard_fault(void)
*/
void dummy_handler(void)
{
core_panic(DUMMY_HANDLER, "DUMMY HANDLER");
core_panic(PANIC_DUMMY_HANDLER, "DUMMY HANDLER");
}
/* Cortex-M specific interrupt vectors */