From 3d29a9e3d3091e1658bb5ffce6a865541d98c152 Mon Sep 17 00:00:00 2001
From: Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
Date: Fri, 29 Aug 2014 18:30:37 +0200
Subject: [PATCH] native: add support for Linux on ARM

---
 boards/native/Makefile.include |  7 +++++-
 cpu/native/irq_cpu.c           | 12 +++++++++-
 cpu/native/tramp.S             | 44 +++++++++++++++++++++++++++++++++-
 3 files changed, 60 insertions(+), 3 deletions(-)

diff --git a/boards/native/Makefile.include b/boards/native/Makefile.include
index e639f07fa0..50702b83a3 100644
--- a/boards/native/Makefile.include
+++ b/boards/native/Makefile.include
@@ -25,7 +25,10 @@ export CGANNOTATE ?= cg_annotate
 export GPROF ?= gprof
 
 # basic cflags:
-export CFLAGS += -Wall -Wextra -pedantic -m32
+export CFLAGS += -Wall -Wextra -pedantic
+ifeq ($(shell uname -m),x86_64)
+export CFLAGS += -m32
+endif
 ifneq (,$(filter -DDEVELHELP,$(CFLAGS)))
 export CFLAGS += -fstack-protector-all
 endif
@@ -39,7 +42,9 @@ endif
 export CXXUWFLAGS +=
 export CXXEXFLAGS +=
 
+ifeq ($(shell uname -m),x86_64)
 export LINKFLAGS += -m32
+endif
 ifeq ($(shell uname -s),FreeBSD)
 ifeq ($(shell uname -m),amd64)
 export LINKFLAGS += -DCOMPAT_32BIT -L/usr/lib32 -B/usr/lib32
diff --git a/cpu/native/irq_cpu.c b/cpu/native/irq_cpu.c
index 96ac53db33..e78f1a440f 100644
--- a/cpu/native/irq_cpu.c
+++ b/cpu/native/irq_cpu.c
@@ -30,7 +30,7 @@
 #define VALGRIND_DEBUG(...)
 #endif
 
-// __USE_GNU for gregs[REG_EIP] access under Linux
+/* __USE_GNU for gregs[REG_EIP] access under Linux */
 #define __USE_GNU
 #include <signal.h>
 #undef __USE_GNU
@@ -331,17 +331,27 @@ void native_isr_entry(int sig, siginfo_t *info, void *context)
     /* disable interrupts in context */
     isr_set_sigmask((ucontext_t *)context);
     _native_in_isr = 1;
+    /*
+     * For register access on new platforms see:
+     * http://google-glog.googlecode.com/svn/trunk/m4/pc_from_ucontext.m4
+     * (URL added on Fri Aug 29 17:17:45 CEST 2014)
+     */
 #ifdef __MACH__
     _native_saved_eip = ((ucontext_t *)context)->uc_mcontext->__ss.__eip;
     ((ucontext_t *)context)->uc_mcontext->__ss.__eip = (unsigned int)&_native_sig_leave_tramp;
 #elif defined(__FreeBSD__)
     _native_saved_eip = ((struct sigcontext *)context)->sc_eip;
     ((struct sigcontext *)context)->sc_eip = (unsigned int)&_native_sig_leave_tramp;
+#else
+#ifdef __arm__
+    _native_saved_eip = ((ucontext_t *)context)->uc_mcontext.arm_pc;
+    ((ucontext_t *)context)->uc_mcontext.arm_pc = (unsigned int)&_native_sig_leave_tramp;
 #else
     //printf("\n\033[31mEIP:\t%p\ngo switching\n\n\033[0m", (void*)((ucontext_t *)context)->uc_mcontext.gregs[REG_EIP]);
     _native_saved_eip = ((ucontext_t *)context)->uc_mcontext.gregs[REG_EIP];
     ((ucontext_t *)context)->uc_mcontext.gregs[REG_EIP] = (unsigned int)&_native_sig_leave_tramp;
 #endif
+#endif
 }
 
 /**
diff --git a/cpu/native/tramp.S b/cpu/native/tramp.S
index 8d70a26081..c53e93d3cd 100644
--- a/cpu/native/tramp.S
+++ b/cpu/native/tramp.S
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) 2014 Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
+ * Copyright (C) 2013, 2014 Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
+ * Copyright (C) 2014 Thomas Eichinger <thomas.eichinger1@gmail.com>
  *
  * This file is subject to the terms and conditions of the GNU Lesser
  * General Public License v2.1. See the file LICENSE in the top level
@@ -27,6 +28,47 @@ __native_sig_leave_tramp:
     popfl
 
     ret
+#elif __arm__
+.extern _native_saved_eip
+.extern _native_isr_ctx
+.extern _native_cur_ctx
+.extern _native_in_isr
+
+.globl _native_sig_leave_tramp
+_native_sig_leave_tramp:
+    /* save _native_saved_eip and registers */
+    stmdb   sp!, {r0}
+    ldr     r0, =_native_saved_eip
+    ldr     r0, [r0]
+    stmdb   sp!, {r0-r12}
+    stmdb   sp!, {lr}
+
+    /* exchange r0 and _native_saved_eip */
+    ldr     r0, [sp,#56]
+    ldr     r1, [sp,#4 ]
+    str     r0, [sp,#4 ]
+    str     r1, [sp,#56]
+
+    /* call swapcontext ( _native_cur_ctx, _native_isr_ctx ) */
+    ldr     r2, =_native_cur_ctx
+    ldr     r0, [r2]
+    ldr     r2, =_native_isr_ctx
+    ldr     r1, [r2]
+    bl      swapcontext
+
+    /* reeanble interrupts */
+    bl      eINT
+
+    /* _native_in_isr = 0 */
+    eor     r0, r0, r0
+    ldr     r2, =_native_in_isr
+    str     r0, [r2]
+
+    /* restore registers, jump to (saved) _native_saved_eip */
+    ldmia   sp!, {lr}
+    ldmia   sp!, {r0-r12}
+    ldmia   sp!, {pc}
+
 #else
 .extern $_native_saved_eip
 .extern $_native_isr_ctx