Merge pull request #15360 from benpicco/drivers/mtd_spi_nor_enhance
drivers/mtd_spi_nor: enable 32 bit addressing, define WP and HOLD pins
This commit is contained in:
commit
3d30266736
@ -36,6 +36,8 @@ static const mtd_spi_nor_params_t _ikea_tradfri_nor_params = {
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.spi = IKEA_TRADFRI_NOR_SPI_DEV,
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.spi = IKEA_TRADFRI_NOR_SPI_DEV,
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.mode = IKEA_TRADFRI_NOR_SPI_MODE,
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.mode = IKEA_TRADFRI_NOR_SPI_MODE,
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.cs = IKEA_TRADFRI_NOR_SPI_CS,
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.cs = IKEA_TRADFRI_NOR_SPI_CS,
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.wp = GPIO_UNDEF,
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.hold = GPIO_UNDEF,
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.addr_width = 3,
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.addr_width = 3,
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};
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};
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@ -55,9 +55,11 @@ static const mtd_spi_nor_params_t mulle_nor_params = {
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.wait_32k_erase = 20LU * US_PER_MS,
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.wait_32k_erase = 20LU * US_PER_MS,
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.wait_chip_wake_up = 1LU * US_PER_MS,
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.wait_chip_wake_up = 1LU * US_PER_MS,
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.spi = MULLE_NOR_SPI_DEV,
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.spi = MULLE_NOR_SPI_DEV,
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.cs = MULLE_NOR_SPI_CS,
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.addr_width = 3,
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.addr_width = 3,
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.mode = SPI_MODE_3,
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.mode = SPI_MODE_3,
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.cs = MULLE_NOR_SPI_CS,
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.wp = GPIO_UNDEF,
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.hold = GPIO_UNDEF,
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.clk = SPI_CLK_10MHZ,
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.clk = SPI_CLK_10MHZ,
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};
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};
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@ -38,6 +38,8 @@ static const mtd_spi_nor_params_t _nrf52840dk_nor_params = {
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.spi = NRF52840DK_NOR_SPI_DEV,
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.spi = NRF52840DK_NOR_SPI_DEV,
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.mode = NRF52840DK_NOR_SPI_MODE,
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.mode = NRF52840DK_NOR_SPI_MODE,
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.cs = NRF52840DK_NOR_SPI_CS,
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.cs = NRF52840DK_NOR_SPI_CS,
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.wp = GPIO_UNDEF,
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.hold = GPIO_UNDEF,
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.addr_width = 3,
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.addr_width = 3,
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};
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};
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@ -41,6 +41,8 @@ static const mtd_spi_nor_params_t _pinetime_nor_params = {
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.spi = PINETIME_NOR_SPI_DEV,
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.spi = PINETIME_NOR_SPI_DEV,
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.mode = PINETIME_NOR_SPI_MODE,
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.mode = PINETIME_NOR_SPI_MODE,
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.cs = PINETIME_NOR_SPI_CS,
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.cs = PINETIME_NOR_SPI_CS,
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.wp = GPIO_UNDEF,
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.hold = GPIO_UNDEF,
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.addr_width = 3,
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.addr_width = 3,
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};
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};
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@ -39,6 +39,8 @@ static const mtd_spi_nor_params_t _serpente_nor_params = {
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.spi = SERPENTE_NOR_SPI_DEV,
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.spi = SERPENTE_NOR_SPI_DEV,
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.mode = SERPENTE_NOR_SPI_MODE,
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.mode = SERPENTE_NOR_SPI_MODE,
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.cs = SERPENTE_NOR_SPI_CS,
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.cs = SERPENTE_NOR_SPI_CS,
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.wp = GPIO_UNDEF,
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.hold = GPIO_UNDEF,
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.addr_width = 3,
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.addr_width = 3,
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};
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};
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@ -38,6 +38,8 @@ static const mtd_spi_nor_params_t _weact_nor_params = {
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.spi = WEACT_411CE_NOR_SPI_DEV,
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.spi = WEACT_411CE_NOR_SPI_DEV,
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.mode = WEACT_411CE_NOR_SPI_MODE,
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.mode = WEACT_411CE_NOR_SPI_MODE,
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.cs = WEACT_411CE_NOR_SPI_CS,
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.cs = WEACT_411CE_NOR_SPI_CS,
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.wp = GPIO_UNDEF,
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.hold = GPIO_UNDEF,
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.addr_width = 3,
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.addr_width = 3,
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};
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};
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@ -111,6 +111,8 @@ typedef struct {
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spi_t spi; /**< SPI bus the device is connected to */
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spi_t spi; /**< SPI bus the device is connected to */
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spi_mode_t mode; /**< SPI mode */
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spi_mode_t mode; /**< SPI mode */
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gpio_t cs; /**< CS pin GPIO handle */
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gpio_t cs; /**< CS pin GPIO handle */
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gpio_t wp; /**< Write Protect pin GPIO handle */
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gpio_t hold; /**< HOLD pin GPIO handle */
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uint8_t addr_width; /**< Number of bytes in addresses, usually 3 for small devices */
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uint8_t addr_width; /**< Number of bytes in addresses, usually 3 for small devices */
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} mtd_spi_nor_params_t;
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} mtd_spi_nor_params_t;
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@ -46,6 +46,9 @@
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#define MTD_POWER_UP_WAIT_FOR_ID (0x0F)
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#define MTD_POWER_UP_WAIT_FOR_ID (0x0F)
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#endif
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#endif
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#define SFLASH_CMD_4_BYTE_ADDR (0xB7) /**< enable 32 bit addressing */
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#define SFLASH_CMD_3_BYTE_ADDR (0xE9) /**< enable 24 bit addressing */
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#define MTD_64K (65536ul)
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#define MTD_64K (65536ul)
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#define MTD_64K_ADDR_MASK (0xFFFF)
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#define MTD_64K_ADDR_MASK (0xFFFF)
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#define MTD_32K (32768ul)
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#define MTD_32K (32768ul)
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@ -356,6 +359,26 @@ static inline void wait_for_write_complete(const mtd_spi_nor_t *dev, uint32_t us
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DEBUG("\n");
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DEBUG("\n");
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}
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}
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static void _init_pins(mtd_spi_nor_t *dev)
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{
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DEBUG("mtd_spi_nor_init: init pins\n");
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/* CS */
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spi_init_cs(_get_spi(dev), dev->params->cs);
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/* Write Protect - not used by the driver */
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if (gpio_is_valid(dev->params->wp)) {
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gpio_init(dev->params->wp, GPIO_OUT);
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gpio_set(dev->params->wp);
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}
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/* Hold - not used by the driver */
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if (gpio_is_valid(dev->params->hold)) {
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gpio_init(dev->params->hold, GPIO_OUT);
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gpio_set(dev->params->hold);
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}
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}
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static int mtd_spi_nor_power(mtd_dev_t *mtd, enum mtd_power_state power)
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static int mtd_spi_nor_power(mtd_dev_t *mtd, enum mtd_power_state power)
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{
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{
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mtd_spi_nor_t *dev = (mtd_spi_nor_t *)mtd;
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mtd_spi_nor_t *dev = (mtd_spi_nor_t *)mtd;
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@ -378,6 +401,11 @@ static int mtd_spi_nor_power(mtd_dev_t *mtd, enum mtd_power_state power)
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return -EIO;
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return -EIO;
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}
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}
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#endif
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#endif
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/* enable 32 bit address mode */
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if (dev->params->addr_width == 4) {
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mtd_spi_cmd(dev, SFLASH_CMD_4_BYTE_ADDR);
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}
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break;
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break;
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case MTD_POWER_DOWN:
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case MTD_POWER_DOWN:
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mtd_spi_cmd(dev, dev->params->opcode->sleep);
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mtd_spi_cmd(dev, dev->params->opcode->sleep);
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@ -396,13 +424,12 @@ static int mtd_spi_nor_init(mtd_dev_t *mtd)
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DEBUG("mtd_spi_nor_init: -> spi: %lx, cs: %lx, opcodes: %p\n",
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DEBUG("mtd_spi_nor_init: -> spi: %lx, cs: %lx, opcodes: %p\n",
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(unsigned long)_get_spi(dev), (unsigned long)dev->params->cs, (void *)dev->params->opcode);
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(unsigned long)_get_spi(dev), (unsigned long)dev->params->cs, (void *)dev->params->opcode);
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if (dev->params->addr_width == 0) {
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/* verify configuration */
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return -EINVAL;
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assert(dev->params->addr_width > 0);
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}
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assert(dev->params->addr_width <= 4);
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/* CS */
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/* CS, WP, Hold */
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DEBUG("mtd_spi_nor_init: CS init\n");
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_init_pins(dev);
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spi_init_cs(_get_spi(dev), dev->params->cs);
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/* power up the MTD device*/
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/* power up the MTD device*/
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DEBUG("mtd_spi_nor_init: power up MTD device");
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DEBUG("mtd_spi_nor_init: power up MTD device");
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