Merge pull request #15360 from benpicco/drivers/mtd_spi_nor_enhance

drivers/mtd_spi_nor: enable 32 bit addressing, define WP and HOLD pins
This commit is contained in:
benpicco 2020-11-02 23:39:56 +01:00 committed by GitHub
commit 3d30266736
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 48 additions and 7 deletions

View File

@ -36,6 +36,8 @@ static const mtd_spi_nor_params_t _ikea_tradfri_nor_params = {
.spi = IKEA_TRADFRI_NOR_SPI_DEV, .spi = IKEA_TRADFRI_NOR_SPI_DEV,
.mode = IKEA_TRADFRI_NOR_SPI_MODE, .mode = IKEA_TRADFRI_NOR_SPI_MODE,
.cs = IKEA_TRADFRI_NOR_SPI_CS, .cs = IKEA_TRADFRI_NOR_SPI_CS,
.wp = GPIO_UNDEF,
.hold = GPIO_UNDEF,
.addr_width = 3, .addr_width = 3,
}; };

View File

@ -55,9 +55,11 @@ static const mtd_spi_nor_params_t mulle_nor_params = {
.wait_32k_erase = 20LU * US_PER_MS, .wait_32k_erase = 20LU * US_PER_MS,
.wait_chip_wake_up = 1LU * US_PER_MS, .wait_chip_wake_up = 1LU * US_PER_MS,
.spi = MULLE_NOR_SPI_DEV, .spi = MULLE_NOR_SPI_DEV,
.cs = MULLE_NOR_SPI_CS,
.addr_width = 3, .addr_width = 3,
.mode = SPI_MODE_3, .mode = SPI_MODE_3,
.cs = MULLE_NOR_SPI_CS,
.wp = GPIO_UNDEF,
.hold = GPIO_UNDEF,
.clk = SPI_CLK_10MHZ, .clk = SPI_CLK_10MHZ,
}; };

View File

@ -38,6 +38,8 @@ static const mtd_spi_nor_params_t _nrf52840dk_nor_params = {
.spi = NRF52840DK_NOR_SPI_DEV, .spi = NRF52840DK_NOR_SPI_DEV,
.mode = NRF52840DK_NOR_SPI_MODE, .mode = NRF52840DK_NOR_SPI_MODE,
.cs = NRF52840DK_NOR_SPI_CS, .cs = NRF52840DK_NOR_SPI_CS,
.wp = GPIO_UNDEF,
.hold = GPIO_UNDEF,
.addr_width = 3, .addr_width = 3,
}; };

View File

@ -41,6 +41,8 @@ static const mtd_spi_nor_params_t _pinetime_nor_params = {
.spi = PINETIME_NOR_SPI_DEV, .spi = PINETIME_NOR_SPI_DEV,
.mode = PINETIME_NOR_SPI_MODE, .mode = PINETIME_NOR_SPI_MODE,
.cs = PINETIME_NOR_SPI_CS, .cs = PINETIME_NOR_SPI_CS,
.wp = GPIO_UNDEF,
.hold = GPIO_UNDEF,
.addr_width = 3, .addr_width = 3,
}; };

View File

@ -39,6 +39,8 @@ static const mtd_spi_nor_params_t _serpente_nor_params = {
.spi = SERPENTE_NOR_SPI_DEV, .spi = SERPENTE_NOR_SPI_DEV,
.mode = SERPENTE_NOR_SPI_MODE, .mode = SERPENTE_NOR_SPI_MODE,
.cs = SERPENTE_NOR_SPI_CS, .cs = SERPENTE_NOR_SPI_CS,
.wp = GPIO_UNDEF,
.hold = GPIO_UNDEF,
.addr_width = 3, .addr_width = 3,
}; };

View File

@ -38,6 +38,8 @@ static const mtd_spi_nor_params_t _weact_nor_params = {
.spi = WEACT_411CE_NOR_SPI_DEV, .spi = WEACT_411CE_NOR_SPI_DEV,
.mode = WEACT_411CE_NOR_SPI_MODE, .mode = WEACT_411CE_NOR_SPI_MODE,
.cs = WEACT_411CE_NOR_SPI_CS, .cs = WEACT_411CE_NOR_SPI_CS,
.wp = GPIO_UNDEF,
.hold = GPIO_UNDEF,
.addr_width = 3, .addr_width = 3,
}; };

View File

@ -111,6 +111,8 @@ typedef struct {
spi_t spi; /**< SPI bus the device is connected to */ spi_t spi; /**< SPI bus the device is connected to */
spi_mode_t mode; /**< SPI mode */ spi_mode_t mode; /**< SPI mode */
gpio_t cs; /**< CS pin GPIO handle */ gpio_t cs; /**< CS pin GPIO handle */
gpio_t wp; /**< Write Protect pin GPIO handle */
gpio_t hold; /**< HOLD pin GPIO handle */
uint8_t addr_width; /**< Number of bytes in addresses, usually 3 for small devices */ uint8_t addr_width; /**< Number of bytes in addresses, usually 3 for small devices */
} mtd_spi_nor_params_t; } mtd_spi_nor_params_t;

View File

@ -46,6 +46,9 @@
#define MTD_POWER_UP_WAIT_FOR_ID (0x0F) #define MTD_POWER_UP_WAIT_FOR_ID (0x0F)
#endif #endif
#define SFLASH_CMD_4_BYTE_ADDR (0xB7) /**< enable 32 bit addressing */
#define SFLASH_CMD_3_BYTE_ADDR (0xE9) /**< enable 24 bit addressing */
#define MTD_64K (65536ul) #define MTD_64K (65536ul)
#define MTD_64K_ADDR_MASK (0xFFFF) #define MTD_64K_ADDR_MASK (0xFFFF)
#define MTD_32K (32768ul) #define MTD_32K (32768ul)
@ -356,6 +359,26 @@ static inline void wait_for_write_complete(const mtd_spi_nor_t *dev, uint32_t us
DEBUG("\n"); DEBUG("\n");
} }
static void _init_pins(mtd_spi_nor_t *dev)
{
DEBUG("mtd_spi_nor_init: init pins\n");
/* CS */
spi_init_cs(_get_spi(dev), dev->params->cs);
/* Write Protect - not used by the driver */
if (gpio_is_valid(dev->params->wp)) {
gpio_init(dev->params->wp, GPIO_OUT);
gpio_set(dev->params->wp);
}
/* Hold - not used by the driver */
if (gpio_is_valid(dev->params->hold)) {
gpio_init(dev->params->hold, GPIO_OUT);
gpio_set(dev->params->hold);
}
}
static int mtd_spi_nor_power(mtd_dev_t *mtd, enum mtd_power_state power) static int mtd_spi_nor_power(mtd_dev_t *mtd, enum mtd_power_state power)
{ {
mtd_spi_nor_t *dev = (mtd_spi_nor_t *)mtd; mtd_spi_nor_t *dev = (mtd_spi_nor_t *)mtd;
@ -378,6 +401,11 @@ static int mtd_spi_nor_power(mtd_dev_t *mtd, enum mtd_power_state power)
return -EIO; return -EIO;
} }
#endif #endif
/* enable 32 bit address mode */
if (dev->params->addr_width == 4) {
mtd_spi_cmd(dev, SFLASH_CMD_4_BYTE_ADDR);
}
break; break;
case MTD_POWER_DOWN: case MTD_POWER_DOWN:
mtd_spi_cmd(dev, dev->params->opcode->sleep); mtd_spi_cmd(dev, dev->params->opcode->sleep);
@ -396,13 +424,12 @@ static int mtd_spi_nor_init(mtd_dev_t *mtd)
DEBUG("mtd_spi_nor_init: -> spi: %lx, cs: %lx, opcodes: %p\n", DEBUG("mtd_spi_nor_init: -> spi: %lx, cs: %lx, opcodes: %p\n",
(unsigned long)_get_spi(dev), (unsigned long)dev->params->cs, (void *)dev->params->opcode); (unsigned long)_get_spi(dev), (unsigned long)dev->params->cs, (void *)dev->params->opcode);
if (dev->params->addr_width == 0) { /* verify configuration */
return -EINVAL; assert(dev->params->addr_width > 0);
} assert(dev->params->addr_width <= 4);
/* CS */ /* CS, WP, Hold */
DEBUG("mtd_spi_nor_init: CS init\n"); _init_pins(dev);
spi_init_cs(_get_spi(dev), dev->params->cs);
/* power up the MTD device*/ /* power up the MTD device*/
DEBUG("mtd_spi_nor_init: power up MTD device"); DEBUG("mtd_spi_nor_init: power up MTD device");