boards/*: instead of cpp-style, use C-style comments
This commit is contained in:
parent
c61c44a1ae
commit
3d4d9c7902
@ -117,8 +117,8 @@ void msp430_init_dco(void)
|
||||
/* Stop watchdog */
|
||||
WDTCTL = WDTPW + WDTHOLD;
|
||||
|
||||
//Init crystal for mclk
|
||||
//XT2 = HF XTAL
|
||||
/* Init crystal for mclk */
|
||||
/* XT2 = HF XTAL */
|
||||
BCSCTL1 = RSEL2;
|
||||
|
||||
/* Wait for xtal to stabilize */
|
||||
|
||||
@ -44,10 +44,10 @@ init_mam(void)
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void init_clks2(void)
|
||||
{
|
||||
// Wait for the PLL to lock to set frequency
|
||||
/* Wait for the PLL to lock to set frequency */
|
||||
while (!(PLLSTAT & BIT26));
|
||||
|
||||
// Connect the PLL as the clock source
|
||||
/* Connect the PLL as the clock source */
|
||||
PLLCON = 0x0003;
|
||||
pllfeed();
|
||||
|
||||
@ -57,8 +57,8 @@ void init_clks2(void)
|
||||
|
||||
void watchdog_init(void)
|
||||
{
|
||||
WDCLKSEL = 0; // clock source: RC oscillator
|
||||
WDMOD &= ~WDTOF; // clear time-out flag
|
||||
WDCLKSEL = 0; /* clock source: RC oscillator */
|
||||
WDMOD &= ~WDTOF; /* clear time-out flag */
|
||||
WDTC = (F_RC_OSCILLATOR / 4) * WD_INTERVAL;
|
||||
}
|
||||
|
||||
@ -66,7 +66,7 @@ void watchdog_init(void)
|
||||
void bl_init_clks(void)
|
||||
{
|
||||
watchdog_init();
|
||||
PCONP = PCRTC; // switch off everything except RTC
|
||||
PCONP = PCRTC; /* switch off everything except RTC */
|
||||
init_clks1();
|
||||
init_clks2();
|
||||
init_mam();
|
||||
|
||||
@ -32,7 +32,7 @@ void bl_init_ports(void)
|
||||
gpio_init_ports();
|
||||
|
||||
/* UART0 */
|
||||
PINSEL0 |= BIT4 + BIT6; // RxD0 and TxD0
|
||||
PINSEL0 |= BIT4 + BIT6; /* RxD0 and TxD0 */
|
||||
PINSEL0 &= ~(BIT5 + BIT7);
|
||||
|
||||
/* LEDS */
|
||||
@ -45,31 +45,31 @@ void bl_init_ports(void)
|
||||
|
||||
void init_clks1(void)
|
||||
{
|
||||
// Disconnect PLL
|
||||
/* Disconnect PLL */
|
||||
PLLCON &= ~0x0002;
|
||||
pllfeed();
|
||||
|
||||
// Disable PLL
|
||||
/* Disable PLL */
|
||||
PLLCON &= ~0x0001;
|
||||
pllfeed();
|
||||
|
||||
SCS |= 0x20; // Enable main OSC
|
||||
SCS |= 0x20; /* Enable main OSC */
|
||||
|
||||
while (!(SCS & 0x40)); // Wait until main OSC is usable
|
||||
while (!(SCS & 0x40)); /* Wait until main OSC is usable */
|
||||
|
||||
/* select main OSC, 16MHz, as the PLL clock source */
|
||||
CLKSRCSEL = 0x0001;
|
||||
|
||||
// Setting Multiplier and Divider values
|
||||
PLLCFG = 0x0008; // M=9 N=1 Fcco = 288 MHz
|
||||
/* Setting Multiplier and Divider values */
|
||||
PLLCFG = 0x0008; /* M=9 N=1 Fcco = 288 MHz */
|
||||
pllfeed();
|
||||
|
||||
// Enabling the PLL */
|
||||
/* Enabling the PLL */
|
||||
PLLCON = 0x0001;
|
||||
pllfeed();
|
||||
|
||||
/* Set clock divider to 4 (value+1) */
|
||||
CCLKCFG = CL_CPU_DIV - 1; // Fcpu = 72 MHz
|
||||
CCLKCFG = CL_CPU_DIV - 1; /* Fcpu = 72 MHz */
|
||||
|
||||
#if USE_USB
|
||||
USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user