diff --git a/cpu/sam0_common/Kconfig b/cpu/sam0_common/Kconfig
index fedf79cc31..c548bfe4d5 100644
--- a/cpu/sam0_common/Kconfig
+++ b/cpu/sam0_common/Kconfig
@@ -15,6 +15,7 @@ config CPU_COMMON_SAM0
     select HAS_PERIPH_GPIO
     select HAS_PERIPH_GPIO_IRQ
     select HAS_PERIPH_I2C_RECONFIGURE
+    select HAS_PERIPH_SPI_RECONFIGURE
     select HAS_PERIPH_TIMER_PERIODIC
     select HAS_PERIPH_UART_MODECFG
     select HAS_PERIPH_UART_NONBLOCKING
diff --git a/cpu/sam0_common/Makefile.features b/cpu/sam0_common/Makefile.features
index a149991e88..89d252458a 100644
--- a/cpu/sam0_common/Makefile.features
+++ b/cpu/sam0_common/Makefile.features
@@ -5,6 +5,7 @@ FEATURES_PROVIDED += periph_flashpage_raw
 FEATURES_PROVIDED += periph_flashpage_rwee
 FEATURES_PROVIDED += periph_gpio periph_gpio_irq
 FEATURES_PROVIDED += periph_i2c_reconfigure
+FEATURES_PROVIDED += periph_spi_reconfigure
 FEATURES_PROVIDED += periph_timer_periodic # implements timer_set_periodic()
 FEATURES_PROVIDED += periph_uart_modecfg
 FEATURES_PROVIDED += periph_uart_nonblocking
diff --git a/cpu/sam0_common/include/periph_cpu_common.h b/cpu/sam0_common/include/periph_cpu_common.h
index 9796867d6d..dab7a4a507 100644
--- a/cpu/sam0_common/include/periph_cpu_common.h
+++ b/cpu/sam0_common/include/periph_cpu_common.h
@@ -263,6 +263,16 @@ typedef enum {
     SPI_CLK_10MHZ  = 10000000U  /**< drive the SPI bus with 10MHz */
 } spi_clk_t;
 /** @} */
+
+/**
+ * @brief   SPI pin getters
+ * @{
+ */
+#define spi_pin_mosi(dev) spi_config[dev].mosi_pin
+#define spi_pin_miso(dev) spi_config[dev].miso_pin
+#define spi_pin_clk(dev)  spi_config[dev].clk_pin
+/** @} */
+
 #endif /* ndef DOXYGEN */
 
 /**
diff --git a/cpu/sam0_common/periph/spi.c b/cpu/sam0_common/periph/spi.c
index b7dfc1cd85..934b0d1992 100644
--- a/cpu/sam0_common/periph/spi.c
+++ b/cpu/sam0_common/periph/spi.c
@@ -134,6 +134,16 @@ void spi_init_pins(spi_t bus)
     gpio_init_mux(spi_config[bus].miso_pin, spi_config[bus].miso_mux);
     gpio_init_mux(spi_config[bus].mosi_pin, spi_config[bus].mosi_mux);
     /* clk_pin will be muxed during acquire / release */
+
+    mutex_unlock(&locks[bus]);
+}
+
+void spi_deinit_pins(spi_t bus)
+{
+    mutex_lock(&locks[bus]);
+
+    gpio_disable_mux(spi_config[bus].miso_pin);
+    gpio_disable_mux(spi_config[bus].mosi_pin);
 }
 
 int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)