Merge pull request #12794 from gschorcht/cpu/esp32/cpu_clk_workaround
cpu/esp32: workaround for UART problems
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commit
40a419baef
@ -281,6 +281,8 @@ static void _uart_config (uart_t uart)
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/* setup the baudrate */
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/* setup the baudrate */
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if (uart == UART_DEV(0) || uart == UART_DEV(1)) {
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if (uart == UART_DEV(0) || uart == UART_DEV(1)) {
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/* wait until TX FIFO is empty */
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while (_uarts[uart].regs->status.txfifo_cnt) { }
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/* for UART0 and UART1, we can us the ROM function */
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/* for UART0 and UART1, we can us the ROM function */
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uart_div_modify(uart, (UART_CLK_FREQ << 4) / _uarts[uart].baudrate);
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uart_div_modify(uart, (UART_CLK_FREQ << 4) / _uarts[uart].baudrate);
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}
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}
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@ -197,8 +197,8 @@ static void IRAM system_clk_init (void)
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rtc_init_module(rtc_cfg);
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rtc_init_module(rtc_cfg);
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/* configure main crystal frequency if necessary */
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/* configure main crystal frequency if necessary */
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if (CONFIG_ESP32_XTAL_FREQ != RTC_XTAL_FREQ_AUTO
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if (CONFIG_ESP32_XTAL_FREQ != RTC_XTAL_FREQ_AUTO &&
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&& CONFIG_ESP32_XTAL_FREQ != rtc_clk_xtal_freq_get()) {
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CONFIG_ESP32_XTAL_FREQ != rtc_clk_xtal_freq_get()) {
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bootloader_clock_configure();
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bootloader_clock_configure();
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}
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}
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@ -208,10 +208,10 @@ static void IRAM system_clk_init (void)
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/* set SLOW_CLK to internal low power clock of 150 kHz */
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/* set SLOW_CLK to internal low power clock of 150 kHz */
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rtc_select_slow_clk(RTC_SLOW_FREQ_RTC);
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rtc_select_slow_clk(RTC_SLOW_FREQ_RTC);
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ets_printf("Switching system clocks can lead to some unreadable characters\n");
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/* wait until UART is idle to avoid losing output */
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/* wait until UART is idle to avoid losing output */
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uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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ets_printf("Switching system clocks can lead to some unreadable characters\n");
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ets_printf("This message is usually not visible at the console\n");
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/* determine configured CPU clock frequency from sdk_conf.h */
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/* determine configured CPU clock frequency from sdk_conf.h */
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rtc_cpu_freq_t freq;
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rtc_cpu_freq_t freq;
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@ -230,12 +230,14 @@ static void IRAM system_clk_init (void)
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uint32_t freq_before = rtc_clk_cpu_freq_value(rtc_clk_cpu_freq_get()) / MHZ ;
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uint32_t freq_before = rtc_clk_cpu_freq_value(rtc_clk_cpu_freq_get()) / MHZ ;
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/* set configured CPU frequency */
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if (freq_before != CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) {
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rtc_clk_cpu_freq_set(freq);
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/* set configured CPU frequency */
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rtc_clk_cpu_freq_set(freq);
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/* Recalculate the ccount to make time calculation correct. */
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/* Recalculate the ccount to make time calculation correct. */
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uint32_t freq_after = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
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uint32_t freq_after = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
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XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * freq_after / freq_before );
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XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * freq_after / freq_before );
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}
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}
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}
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extern void IRAM_ATTR thread_yield_isr(void* arg);
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extern void IRAM_ATTR thread_yield_isr(void* arg);
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@ -340,7 +342,7 @@ static NORETURN void IRAM system_init (void)
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esp_event_handler_init();
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esp_event_handler_init();
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/* starting RIOT */
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/* starting RIOT */
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ets_printf("Starting RIOT kernel on PRO cpu\n");
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printf("Starting RIOT kernel on PRO cpu\n");
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kernel_init();
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kernel_init();
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UNREACHABLE();
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UNREACHABLE();
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}
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}
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