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cpu/cc2538: uart init overhaul

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This commit is contained in:
Ian Martin 2015-05-19 20:29:44 -04:00
parent aca53006b0
commit 40b93ea6ad
1 changed files with 33 additions and 27 deletions
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42
cpu/cc2538/periph/uart.c
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@ -197,17 +197,12 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t t
int uart_init_blocking(uart_t uart, uint32_t baudrate) int uart_init_blocking(uart_t uart, uint32_t baudrate)
{ {
cc2538_uart_t *u; cc2538_uart_t *u;
unsigned int uart_num;
uint32_t divisor;
switch (uart) { switch (uart) {
#if UART_0_EN #if UART_0_EN
case UART_0: case UART_0:
u = UART_0_DEV; u = UART_0_DEV;
/* Run on SYS_DIV */
u->CC = 0;
/* /*
* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register * Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
*/ */
@ -230,9 +225,6 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
case UART_1: case UART_1:
u = UART_1_DEV; u = UART_1_DEV;
/* Run on SYS_DIV */
u->CC = 0;
/* /*
* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register * Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
*/ */
@ -249,7 +241,29 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
/* Set RX and TX pins to peripheral mode */ /* Set RX and TX pins to peripheral mode */
gpio_hardware_control(UART_1_TX_PIN); gpio_hardware_control(UART_1_TX_PIN);
gpio_hardware_control(UART_1_RX_PIN); gpio_hardware_control(UART_1_RX_PIN);
break;
#endif
default:
(void)u;
return -1;
}
#if UART_0_EN || UART_1_EN
/* Enable clock for the UART while Running, in Sleep and Deep Sleep */
unsigned int uart_num = ( (uintptr_t)u - (uintptr_t)UART0 ) / 0x1000;
SYS_CTRL_RCGCUART |= (1 << uart_num);
SYS_CTRL_SCGCUART |= (1 << uart_num);
SYS_CTRL_DCGCUART |= (1 << uart_num);
/* Make sure the UART is disabled before trying to configure it */
u->CTL = 0;
/* Run on SYS_DIV */
u->CC = 0;
/* On the CC2538, hardware flow control is supported only on UART1 */
if (u == UART1) {
#ifdef UART_1_RTS_PIN #ifdef UART_1_RTS_PIN
IOC_PXX_SEL[UART_1_RTS_PIN] = UART1_RTS; IOC_PXX_SEL[UART_1_RTS_PIN] = UART1_RTS;
gpio_hardware_control(UART_1_RTS_PIN); gpio_hardware_control(UART_1_RTS_PIN);
@ -263,12 +277,6 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
IOC_PXX_OVER[UART_1_CTS_PIN] = IOC_OVERRIDE_DIS; IOC_PXX_OVER[UART_1_CTS_PIN] = IOC_OVERRIDE_DIS;
u->CTLbits.CTSEN = 1; u->CTLbits.CTSEN = 1;
#endif #endif
break;
#endif
default:
return -1;
} }
/* Enable clock for the UART while Running, in Sleep and Deep Sleep */ /* Enable clock for the UART while Running, in Sleep and Deep Sleep */
@ -293,15 +301,12 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
u->IFLSbits.RXIFLSEL = FIFO_LEVEL_1_8TH; u->IFLSbits.RXIFLSEL = FIFO_LEVEL_1_8TH;
u->IFLSbits.TXIFLSEL = FIFO_LEVEL_4_8TH; u->IFLSbits.TXIFLSEL = FIFO_LEVEL_4_8TH;
/* Make sure the UART is disabled before trying to configure it */
u->CTL = 0;
u->CTLbits.RXE = 1; u->CTLbits.RXE = 1;
u->CTLbits.TXE = 1; u->CTLbits.TXE = 1;
u->CTLbits.HSE = UART_CTL_HSE_VALUE; u->CTLbits.HSE = UART_CTL_HSE_VALUE;
/* Set the divisor for the baud rate generator */ /* Set the divisor for the baud rate generator */
divisor = sys_clock_freq(); uint32_t divisor = sys_clock_freq();
divisor <<= UART_CTL_HSE_VALUE + 2; divisor <<= UART_CTL_HSE_VALUE + 2;
divisor += baudrate / 2; /**< Avoid a rounding error */ divisor += baudrate / 2; /**< Avoid a rounding error */
divisor /= baudrate; divisor /= baudrate;
@ -318,6 +323,7 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
u->CTLbits.UARTEN = 1; u->CTLbits.UARTEN = 1;
return 0; return 0;
#endif /* UART_0_EN || UART_1_EN */
} }
void uart_tx_begin(uart_t uart) void uart_tx_begin(uart_t uart)