boards/im880b: add initial support
This commit is contained in:
francisco
Francisco Molina
parent
ec2aff4546
commit
4618a5ce0e
3
boards/im880b/Makefile
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3
boards/im880b/Makefile
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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3
boards/im880b/Makefile.dep
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3
boards/im880b/Makefile.dep
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ifneq (,$(filter netdev_default,$(USEMODULE)))
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USEMODULE += sx1272
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endif
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11
boards/im880b/Makefile.features
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11
boards/im880b/Makefile.features
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## the cpu to build for
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CPU = stm32l1
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CPU_MODEL = stm32l151cb
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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14
boards/im880b/Makefile.include
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14
boards/im880b/Makefile.include
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# define the default port depending on the host OS
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PORT_LINUX ?= /dev/ttyUSB0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
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# setup serial terminal
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include $(RIOTMAKE)/tools/serial.inc.mk
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DEBUG_ADAPTER ?= stlink
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CFLAGS+=-DSX127X_TX_SWITCH
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CFLAGS+=-DSX127X_RX_SWITCH
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# this board uses openocd
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include $(RIOTMAKE)/tools/openocd.inc.mk
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28
boards/im880b/board.c
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28
boards/im880b/board.c
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/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_im880b
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* @{
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*
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* @file
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* @brief Board specific implementations for the im880b board
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*
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* @author Francisco Molina <francois-xavier.molina@inria.fr>
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*
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* @}
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*/
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#include "board.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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/* initialize the CPU */
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cpu_init();
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}
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73
boards/im880b/doc.txt
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73
boards/im880b/doc.txt
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/**
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@defgroup boards_im880b im880b
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@ingroup boards
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@brief Support for the im880b with stm32l151cb-a
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## Hardware
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### MCU
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| MCU | stm32l151cb-a |
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|:------------- |:--------------------- |
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| Family | ARM Cortex-M3 |
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| Vendor | ST Microelectronics |
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| RAM | 16Kb |
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| Flash | 128Kb |
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| Frequency | 32MHz (no external oscilator connected) |
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| FPU | no |
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| Timers | 10 (8x 16-bit, 2x watchdog timers) |
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| ADCs | 1x 24-channel 12-bit |
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| UARTs | 3 |
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| SPIs | 2 |
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| I2Cs | 2 |
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| Vcc | 1.65V - 3.6V |
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| Datasheet | [Datasheet](https://www.st.com/resource/en/datasheet/stm32l151cb-a.pdf) |
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| Reference Manual | [Reference Manual](https://www.st.com/content/ccc/resource/technical/document/reference_manual/cc/f9/93/b2/f0/82/42/57/CD00240193.pdf/files/CD00240193.pdf/jcr:content/translations/en.CD00240193.pdf) |
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| Programming Manual | [Programming Manual](https://www.st.com/content/ccc/resource/technical/document/programming_manual/5b/ca/8d/83/56/7f/40/08/CD00228163.pdf/files/CD00228163.pdf/jcr:content/translations/en.CD00228163.pdf) |
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| Board Manual | [Board Manual](https://cdn.sos.sk/productdata/29/eb/a68245ed/im880b-l-lorawan.pdf)|
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### User Interface
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## Flashing
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As no usb connector is present on the device an external programmer must
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be connected to the board for flashing. You can use JTAG or STLINK programmer.
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* JTAG:
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* - JTDO: PB_3 / P39
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* - JTDI: PA_15 / P38
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* - JTCK: PA_14 / P37
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* - JTMS: PA_13 / P34
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* STLINK:
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* - NRST: NRST / P7
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* - SWCLK: PA_14 / P37
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* - SWDAT: PA_13 / P34
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### STM32 Loader
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To flash RIOT on the board, after connecting the UART-USB bridge, just run:
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```
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BOARD=im880b make flash
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```
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This uses the stm32loader script to erase the memory and flash it interfacing
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with the STM32 ROM bootloader.
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## Connecting via Serial
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The default UART port is the USART1, there is no usb connection a USB/TTL
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converter must be used to connect to the board TX & RX pins. The default
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port is /dev/ttyUSB0. The pin connections are:
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* USART1:
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* - TX: PA_9 / P30
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* - RX: PA_10 / P31
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```
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BOARD=im880b make term
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```
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*/
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## SX1272 radio
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Please note that the board has a Semtech SX1272 radio. This means that when the
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semtech-loramac package or the sx127x driver are used the correct driver version
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(sx1272) must be selected.
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68
boards/im880b/include/board.h
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68
boards/im880b/include/board.h
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/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_im880b
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* @brief Support for im880b
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* @{
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*
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* @file
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* @brief Board specific definitions for the im880b board.
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*
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* @author Francisco Molina <francois-xavier.molina@inria.fr>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include <stdint.h>
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#include "cpu.h"
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#include "periph_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name xtimer configuration
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* @{
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*/
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#define XTIMER_BACKOFF (11)
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#define XTIMER_WIDTH (16)
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/** @} */
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/**
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* @name sx1272 configuration
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* @{
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*/
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#define SX127X_PARAM_SPI_NSS GPIO_PIN(PORT_B, 0)
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#define SX127X_PARAM_RESET GPIO_PIN(PORT_A, 2)
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#define SX127X_PARAM_DIO0 GPIO_PIN(PORT_B, 1)
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#define SX127X_PARAM_DIO1 GPIO_PIN(PORT_B, 10)
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#define SX127X_PARAM_DIO2 GPIO_PIN(PORT_B, 11)
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/* stm32l1xxx Errata: Pull-up on PB7 when configured in analog mode */
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#define SX127X_PARAM_DIO3 GPIO_PIN(PORT_B, 7)
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#define SX127X_PARAM_RX_SWITCH GPIO_PIN(PORT_C, 13)
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#define SX127X_PARAM_TX_SWITCH GPIO_PIN(PORT_A, 4)
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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209
boards/im880b/include/periph_conf.h
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209
boards/im880b/include/periph_conf.h
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/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_im880b
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the im808b board
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*
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* @author Francisco Molina <francois-xavier.molina@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSE (16000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
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/*
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* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz)
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*/
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (1)
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#endif
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSE / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
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#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM3,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.bus = APB1,
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.irqn = TIM3_IRQn
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}
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};
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#define TIMER_0_ISR (isr_tim3)
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn
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},
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};
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#define UART_0_ISR (isr_usart1)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 32000000Hz */
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7, /* -> 125000Hz */
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5, /* -> 500000Hz */
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4, /* -> 1000000Hz */
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2, /* -> 4000000Hz */
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1 /* -> 8000000Hz */
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},
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{ /* for APB2 @ 32000000Hz */
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7, /* -> 125000Hz */
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5, /* -> 500000Hz */
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4, /* -> 1000000Hz */
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2, /* -> 4000000Hz */
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1 /* -> 8000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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},
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{
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.dev = SPI2,
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.mosi_pin = GPIO_PIN(PORT_B, 14),
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.miso_pin = GPIO_PIN(PORT_B, 15),
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.sclk_pin = GPIO_PIN(PORT_B, 13),
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.cs_pin = GPIO_PIN(PORT_B, 12),
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB1ENR_SPI2EN,
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.apbbus = APB1
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C1,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 8),
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.sda_pin = GPIO_PIN(PORT_B, 9),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.clk = CLOCK_APB1,
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.irqn = I2C1_EV_IRQn
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}
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};
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#define I2C_0_ISR isr_i2c1_ev
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#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
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/** @} */
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/**
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* @name RTC configuration
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* @{
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*/
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#define RTC_NUMOF (1U)
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_CONFIG { \
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{ GPIO_PIN(PORT_A, 0), 0 }, /* P14 */ \
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{ GPIO_PIN(PORT_A, 1), 1 }, /* P15 */ \
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{ GPIO_PIN(PORT_A, 3), 3 }, /* P17 */ \
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/* ADC Temperature channel */ \
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{ GPIO_UNDEF, 16 }, \
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/* ADC VREF channel */ \
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{ GPIO_UNDEF, 17 }, \
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}
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#define ADC_NUMOF (5)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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