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cpu/esp8266: vendor files that are no longer needed removed

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This commit is contained in:
Gunar Schorcht 2019-09-05 13:11:13 +02:00
parent c1edee074a
commit 464bb9f4c4
19 changed files with 0 additions and 5225 deletions
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45
cpu/esp8266/vendor/esp/FreeRTOS.h vendored
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/*
* Copyright (C) 2018 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
* FreeRTOS to RIOT-OS adaption module
*/
#ifndef FREERTOS_H
#define FREERTOS_H
#ifndef DOXYGEN
#include "stdlib.h"
#include "mutex.h"
#include "irq.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SemaphoreHandle_t mutex_t*
static inline SemaphoreHandle_t xSemaphoreCreateMutex(void)
{
mutex_t* _tmp = malloc (sizeof(mutex_t));
mutex_init(_tmp);
return _tmp;
}
#define xSemaphoreTake(s,to) mutex_lock(s)
#define xSemaphoreGive(s) mutex_unlock(s)
#define vPortEnterCritical() int _irq_state = irq_disable ()
#define vPortExitCritical() irq_restore(_irq_state)
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* FREERTOS_H */

67
cpu/esp8266/vendor/esp/flashchip.h vendored
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/* flashchip.h
*
* sdk_flashchip_t structure used by the SDK and some bootrom routines
*
* This is in a separate include file because it's referenced by several other
* headers which are otherwise independent of each other.
*
* Part of esp-open-rtos
* Copyright (C) 2015 Alex Stewart and Angus Gratton
* BSD Licensed as described in the file LICENSE
*/
/*
Copyright (C) 2015 Alex Stewart and Angus Gratton
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef FLASHCHIP_H
#define FLASHCHIP_H
#ifndef DOXYGEN
#ifdef __cplusplus
extern "C" {
#endif
/* SDK/bootrom uses this structure internally to account for flash size.
chip_size field is initialised during startup from the flash size
saved in the image header (on the first 8 bytes of SPI flash).
Other field are initialised to hardcoded values by the SDK.
** NOTE: This structure is passed to some bootrom routines and is therefore
fixed. Be very careful if you want to change it that you do not break
things. **
Based on RE work by @foogod at
http://esp8266-re.foogod.com/wiki/Flashchip_%28IoT_RTOS_SDK_0.9.9%29
*/
typedef struct {
uint32_t device_id;
uint32_t chip_size; /* in bytes */
uint32_t block_size; /* in bytes */
uint32_t sector_size; /* in bytes */
uint32_t page_size; /* in bytes */
uint32_t status_mask;
} sdk_flashchip_t;
extern sdk_flashchip_t sdk_flashchip;
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* FLASHCHIP_H */

200
cpu/esp8266/vendor/esp/phy_info.c vendored
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/* Routines to allow custom access to the Internal Espressif
SDK PHY datastructures.
Matches espressif/phy_internal.h
Part of esp-open-rtos. Copyright (C) 2016 Angus Gratton,
BSD Licensed as described in the file LICENSE.
*/
/*
Copyright (C) 2016 Angus Gratton
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef MODULE_ESP_SDK
#ifdef RIOT_VERSION
#include <stdio.h>
#include "c_types.h"
#include "esp/common_macros.h"
#include "esp/flashchip.h"
#include "esp/phy_info.h"
#include "spi_flash.h"
#include "sdk/rom.h"
#define sdk_spi_flash_read spi_flash_read
#define sdk_spi_flash_write spi_flash_write
#else
#include <espressif/phy_info.h>
#include <espressif/esp_common.h>
#include <common_macros.h>
#endif
#include <string.h>
static const sdk_phy_info_t IROM default_phy_info = {
._reserved00 = { 0x05, 0x00, 0x04, 0x02, 0x05 },
.version = 5,
._reserved06 = { 0x05, 0x02, 0x05, 0x00, 0x04, 0x05, 0x05, 0x04,
0x05, 0x05, 0x04,-0x02,-0x03,-0x01,-0x10,-0x10,
-0x10,-0x20,-0x20, -0x20},
.spur_freq_primary = 225,
.spur_freq_divisor = 10,
.spur_freq_en_h = 0xFF,
.spur_freq_en_l = 0xFF,
._reserved1e = { 0xf8, 0, 0xf8, 0xf8 },
.target_power = { 82, 78, 74, 68, 64, 56 },
.target_power_index_mcs = { 0, 0, 1, 1, 2, 3, 4, 5 },
.crystal_freq = CRYSTAL_FREQ_26M,
.sdio_config = SDIO_CONFIG_AUTO,
.bt_coexist_config = BT_COEXIST_CONFIG_NONE,
.bt_coexist_protocol = BT_COEXIST_PROTOCOL_WIFI_ONLY,
.dual_ant_config = DUAL_ANT_CONFIG_NONE,
._reserved34 = 0x02,
.crystal_sleep = CRYSTAL_SLEEP_OFF,
.spur_freq_2_primary = 225,
.spur_freq_2_divisor = 10,
.spur_freq_2_en_h = 0x00,
.spur_freq_2_en_l = 0x00,
.spur_freq_cfg_msb = 0x00,
.spur_freq_2_cfg_msb = 0x00,
.spur_freq_3_cfg = 0x0000,
.spur_freq_4_cfg = 0x0000,
._reserved4a = { 0x01, 0x93, 0x43, 0x00 },
.low_power_en = false,
.lp_atten_stage01 = LP_ATTEN_STAGE01_23DB,
.lp_atten_bb = 0,
.pwr_ind_11b_en = false,
.pwr_ind_11b_0 = 0,
.pwr_ind_11b_1 = 0,
/* Nominal 3.3V VCC. NOTE: This value is 0 in the
esp-open-rtos SDK default config sector, and may be unused
by that version of the SDK?
*/
.pa_vdd = 33,
/* Note: untested with the esp-open-rtos SDK default config sector, may be unused? */
.freq_correct_mode = FREQ_CORRECT_DISABLE,
.force_freq_offset = 0,
/* Note: is zero with the esp-open-rtos SDK default config sector, may be unused? */
.rf_cal_mode = RF_CAL_MODE_SAVED,
};
sdk_phy_info_t* default_phy_info_ref = (sdk_phy_info_t*)&default_phy_info;
sdk_phy_info_t* get_default_phy_info_ref(void)
{
return (sdk_phy_info_t*)&default_phy_info;
}
void get_default_phy_info(sdk_phy_info_t *info) __attribute__((weak, alias("get_sdk_default_phy_info")));
void get_sdk_default_phy_info(sdk_phy_info_t *info)
{
memcpy(info, &default_phy_info, sizeof(sdk_phy_info_t));
}
void read_saved_phy_info(sdk_phy_info_t *info)
{
sdk_spi_flash_read(sdk_flashchip.chip_size - sdk_flashchip.sector_size * 4, (uint32_t *)info, sizeof(sdk_phy_info_t));
}
void write_saved_phy_info(const sdk_phy_info_t *info)
{
sdk_spi_flash_write(sdk_flashchip.chip_size - sdk_flashchip.sector_size * 4, (uint32_t *)info, sizeof(sdk_phy_info_t));
}
void dump_phy_info(const sdk_phy_info_t *info, bool raw)
{
printf("version=%d\n", info->version);
printf("spur_freq = %.3f (%d/%d)\n",
(float)info->spur_freq_primary / info->spur_freq_divisor,
info->spur_freq_primary,
info->spur_freq_divisor);
printf("spur_freq_en = 0x%02x 0x%02x\n", info->spur_freq_en_h,
info->spur_freq_en_l);
printf("target_power\n");
for(int i = 0; i < 6; i++) {
printf(" %d: %.2fdB (raw 0x%02x)\n", i,
info->target_power[i]/4.0,
info->target_power[i]);
}
printf("target_power_index_mcs:");
for(int i = 0; i < 8; i++) {
printf(" %d%c", info->target_power_index_mcs[i],
i == 7 ? '\n' : ',');
}
printf("crystal_freq: %s (raw %d)\n",
(info->crystal_freq == CRYSTAL_FREQ_40M ? "40MHz" :
(info->crystal_freq == CRYSTAL_FREQ_26M ? "26MHz" :
(info->crystal_freq == CRYSTAL_FREQ_24M ? "24MHz" : "???"))),
info->crystal_freq);
printf("sdio_config: %d\n", info->sdio_config);
printf("bt_coexist config: %d protocol: 0x%02x\n",
info->bt_coexist_config, info->bt_coexist_protocol);
printf("dual_ant_config: %d\n", info->dual_ant_config);
printf("crystal_sleep: %d\n", info->crystal_sleep);
printf("spur_freq_2 = %.3f (%d/%d)\n",
(float)info->spur_freq_2_primary / info->spur_freq_2_divisor,
info->spur_freq_2_primary,
info->spur_freq_2_divisor);
printf("spur_freq_2_en = 0x%02x 0x%02x\n", info->spur_freq_2_en_h,
info->spur_freq_2_en_l);
printf("spur_freq_cfg_msb = 0x%02x\n", info->spur_freq_cfg_msb);
printf("spur_freq_2_)cfg_msb = 0x%02x\n", info->spur_freq_2_cfg_msb);
printf("spur_freq_3_cfg = 0x%04x\n", info->spur_freq_3_cfg);
printf("spur_freq_4_cfg = 0x%04x\n", info->spur_freq_4_cfg);
printf("low_power_en = %d\n", info->low_power_en);
printf("lp_atten_stage01 = 0x%02x\n", info->lp_atten_stage01);
printf("lp_atten_bb = %.2f (raw 0x%02x)\n", info->lp_atten_bb / 4.0,
info->lp_atten_bb);
printf("pa_vdd = %d\n", info->pa_vdd);
printf("freq_correct_mode = 0x%02x\n", info->freq_correct_mode);
printf("force_freq_offset = %d\n", info->force_freq_offset);
printf("rf_cal_mode = 0x%02x\n", info->rf_cal_mode);
if(raw) {
printf("Raw values:");
uint8_t *p = (uint8_t *)info;
for(unsigned int i = 0; i < sizeof(sdk_phy_info_t); i ++) {
if(i % 8 == 0) {
printf("\n0x%02x:", i);
}
printf(" %02x", p[i]);
}
printf("\n\n");
}
}
#endif

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cpu/esp8266/vendor/esp/phy_info.h vendored
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/** Internal Espressif SDK "PHY info" data structure
The data structure (sdk_phy_info_t) is used to configure the
ESP8266 PHY layer via the SDK. The fields here are not written
directly to hardware, the SDK code (mostly in libphy) parses this
structure and configures the hardware.
The structure loaded at reset time from a flash configuration
sector (see read_saved_phy_info()) (Espressif's SDK sources this
from a file "esp_init_data_default.bin"). If no valid structure is
found in the flash config sector then the SDK loads default values
(see get_default_phy_info()). It is possible to implement a custom
get_default_phy_info() to change the PHY default settings (see the
'version' field below).
@note It is possible that the SDK will quietly write a new
configuration sector to flash itself following internal
calibration, etc. However this does not seem to happen, you need to
flash it explicitly if you want it stored there.
@note Most of what is below is unconfirmed, except where a @note
says that it has been confirmed to work as expected. Please
consider submitting notes if you find behaviour here that works or
doesn't work as expected.
Information on the meaning/offset of fields comes from Espressif's
flash download tool, which uses an Excel spreadsheet (in the
init_data directory of the ZIP file) to configure and a Python
script to convert an esp_init_data_custom.bin file to flash:
http://bbs.espressif.com/viewtopic.php?f=5&t=433
Many fields remain undocumented (& disassembly of libphy suggests
that some documented fields supported undocumented values.)
A few additional notes about the phy_info fields can be found
in the ESP Arduino ESP8266 phy_init_data structure (however most of
that content is verbatim from Espressif's spreadsheet):
https://github.com/esp8266/Arduino/blob/master/cores/esp8266/core_esp8266_phy.c#L29
Part of esp-open-rtos. Copyright (C) 2016 Angus Gratton,
BSD Licensed as described in the file LICENSE.
*/
/*
Copyright (C) 2016 Angus Gratton
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef PHY_INFO_H
#define PHY_INFO_H
#ifndef DOXYGEN
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
/* CRYSTAL_FREQ_xx values as used by sdk_phy_info_t.crystal_freq */
#define CRYSTAL_FREQ_40M 0
#define CRYSTAL_FREQ_26M 1
#define CRYSTAL_FREQ_24M 2
/* SDIO_CONFIG_xx values as used by sdk_phy_info_t.sdio_config */
#define SDIO_CONFIG_AUTO 0 /* Uses pin strapping to determine */
#define SDIO_CONFIG_SDIOV1_1 /* Data output on negative edge */
#define SDIO_CONFIG_SDIOV2_0 /* data output on positive edge */
/* BT_COEXIST_CONFIG_xx values as used by sdk_phy_info_t.bt_coexist */
/* No bluetooth */
#define BT_COEXIST_CONFIG_NONE 0
/* Coexistence configuration A:
GPIO 0 - WLAN_ACTIVE
GPIO 14 - BT_ACTIVE
GPIO 13 - BT_PRIORITY
GPIO 3 - ANT_SEL_BT
*/
#define BT_COEXIST_CONFIG_A 1
/* No coexistence, but Bluetooth enabled?
Unsure how this works?
*/
#define BT_COEXIST_CONFIG_PRESENT 2
/* Coexistence configuration B:
GPIO 0 - WLAN_ACTIVE
GPIO 14 - BT_PRIORITY
GPIO 13 - BT_ACTIVE
GPIO 3 - ANT_SEL_BT
*/
#define BT_COEXIST_CONFIG_B 3
/* BT_COEXIST_PROTOCOL_xx values for coexistence protocol,
field sdk_phy_info_t.bt_coexist_protocol
*/
#define BT_COEXIST_PROTOCOL_WIFI_ONLY 0
#define BT_COEXIST_PROTOCOL_BT_ONLY 1
/* Coexistence is enabled, Bluetooth has its own antenna */
#define BT_COEXIST_PROTOCOL_FLAG_SEPARATE_ANT 2
/* Coexistence is enabled, Bluetooth shares WiFi antenna */
#define BT_COEXIST_PROTOCOL_FLAG_SHARE_ANT 4
/* Coexistence is enabled, use only BT_ACTIVE signal */
#define BT_COEXIST_PROTOCOL_FLAG_BT_ACTIVE_ONLY 0
/* Coexistence is enabled, use both BT_ACTIVE and BT_PRIORITY signals */
#define BT_COEXIST_PROTOCOL_FLAG_BT_ACTIVE_PRIORITY 1
/* DUAL_ANT_CONFIG_xx values for dual antenna config,
field sdk_phy_info_t.dual_ant_config
(Not really clear how this feature works, if at all.)
*/
#define DUAL_ANT_CONFIG_NONE 0
/* antenna diversity for WiFi, use GPIO0 + U0RXD (?) */
#define DUAL_ANT_CONFIG_DUAL 1
/* TX/RX switch for external PA & LNA: GPIO 0 high, GPIO 3 low during TX */
#define DUAL_ANT_CONFIG_TX_GPIO0_HIGH_GPIO3_LOW
/* TX/RX switch for external PA & LNA: GPIO 0 low, GPIO 3 high during TX */
#define DUAL_ANT_CONFIG_TX_GPIO0_LOW_GPIO3_HIGH
/* CRYSTAL_SLEEP_xx values used for sdk_phy_info_t.crystal_sleep
*/
#define CRYSTAL_SLEEP_OFF 0
#define CRYSTAL_SLEEP_ON 1
#define CRYSTAL_SLEEP_GPIO16 2
#define CRYSTAL_SLEEP_GPIO2 3
/* RF Stage 0 & 1 attenuation constants. Use for sdk_phy_info_t.lp_atten_stage01
@note These values have been tested and are confirmed to work as
expected by measuring RSSI w/ rt73 USB adapter in monitor mode
(some values also checked on spectrum analyzer) - provided
low_power_en is set then the signal is attenuated as per this
setting.
(It may look like LP_ATTEN_STAGE01_11_5DB is out of order, but
according to monitor mode captures this is the correct ordering of
these constants.)
Setting the numeric values in between these constants appears to
also attenuate the signal, but not necessarily by the amount you'd
expect.
*/
#define LP_ATTEN_STAGE01_0DB 0x0f /* 0dB */
#define LP_ATTEN_STAGE01_2_5DB 0x0e /* -2.5dB */
#define LP_ATTEN_STAGE01_6DB 0x0d /* -6dB */
#define LP_ATTEN_STAGE01_8_5DB 0x09 /* -8.5dB */
#define LP_ATTEN_STAGE01_11_5DB 0x0c /* -11.5dB */
#define LP_ATTEN_STAGE01_14DB 0x08 /* -14dB */
#define LP_ATTEN_STAGE01_17_5DB 0x04 /* -17.5dB */
#define LP_ATTEN_STAGE01_23DB 0x00 /* -23dB */
/* Constant for sdk_phy_info_t.pa_vdd */
#define PA_VDD_MEASURE_VCC 0xFF
/* Bitmask flags for sdk_phy_info_t.freq_correct_mode */
/* Set this flag to disable frequency offset correction */
#define FREQ_CORRECT_DISABLE 0
/* Set this flag to enable frequency offset correction */
#define FREQ_CORRECT_ENABLE BIT(0)
/* Set = Baseband PLL frequency is 160MHz (can only apply +ve offset)
* Unset = Baseband PLL frequency is 168MHz (can apply +ve/-ve offset */
#define FREQ_CORRECT_BB_160M BIT(1)
/* Set = use force_freq_offset field to correct, Unset = automatically
measure & correct offset
*/
#define FREQ_CORRECT_FORCE BIT(2)
/* RF_CAL_MODE_xx fields used for sdk_phy_info_t.rf_cal_mode
*/
/* Use saved RF CAL data from flash, only. RF init takes 2ms. */
#define RF_CAL_MODE_SAVED 0
/* Calibrate TX power control only, use saved RF CAL data for others.
RF init takes 20ms. */
#define RF_CAL_MODE_TXPOWER_ONLY 1
/* Unclear if/how this mode is different to 2? */
#define RF_CAL_MODE_SAVED_2 2
/* Run full RF CAL routine. RF init takes approx 200ms. */
#define RF_CAL_MODE_FULL 3
/* Data structure that maps to the phy_info configuration block */
typedef struct __attribute__((packed)) {
uint8_t _reserved00[0x05]; /* 0x00 - 0x04 */
/* This "version" field was set to 5 in the SDK phy_info,
and the original SDK startup code checks it is 5 and then loads
default PHY configuration otherwise.
esp-open-rtos will load phy_info from get_default_phy_info() if
the value stored in flash has a different value to the value
returned in get_default_phy_info(). This means you can
increment the version return by get_default_phy_info() (to any
value but 0xFF), and know that the new defaults will replace
any older stored values.
@notes It's not clear whether this is actually a version field
(the other 24 bytes here have equally arbitrary numbers in
them.) Changing the "version" to other values does not seem to
effect WiFi performance at all, neither does zeroing out the
first 5 reserved bytes in _reserved00. However zeroing bytes in
the _reserved06 region will break WiFi entirely.
*/
uint8_t version; /* 0x05 */
int8_t _reserved06[0x14]; /* 0x06 - 0x19 */
/* spur_freq = spur_freq_primary / spur_freq_divisor */
uint8_t spur_freq_primary; /* 0x1a */
uint8_t spur_freq_divisor; /* 0x1b */
/* Bitmask to enable spur_freq for each channel
Appears to be a big endian short word?
*/
uint8_t spur_freq_en_h; /* 0x1c */
uint8_t spur_freq_en_l; /* 0x1d */
uint8_t _reserved1e[4]; /* 0x1e - 0x21 */
/* Each value is a target power level.
Units are 1/4 dBm ie value 64 = 16dBm.
SDK defaults to using these transmit powers:
20.5dBm, 19.5dBm, 18.5dBm, 17dBm, 16dBm, 14dBm
@note Adjusting these values is confirmed to reduce
transmit power accordingly.
*/
uint8_t target_power[6]; /* 0x22 - 0x27 */
/* Maps 8 MCS (modulation & coding schemes) types for 802.11b, g &
* n to a target_power level index (0-5), set above.
This mapping of MCS slot to MCS type is derived from the
spreadsheet and also a table sent by Espressif, but is untested
and may be SDK version dependendent (especially any 802.11n
rates). However the general relationship is confirmed to hold
(higher MCS index = higher bit rate).
MCS 0: 1Mbps/2Mbps/5.5Mbps/11Mbps (802.11b) / 6Mbps/9Mbps (802.11g)
default target_power 0 (default 20.5dBm)
(see also pwr_ind_11b_en)
MCS 1: 12Mbps (802.11g)
default target_power 0 (default 20.5dBm)
MCS 2: 18Mbps (802.11g)
default target_power 1 (19.5dBm)
MCS 3: 24Mbps (802.11g)
default target_power 1 (19.5dBm)
MCS 4: 36Mbps (802.11g)
default target_power 2 (18.5dBm)
MCS 5: 48Mbps (802.11g)
default target_power 3 (17dBm)
MCS 6: 54Mbps (802.11g)
default target_power 4 (16dBm)
MCS 7: 65Mbps (802.11n) - unclear if ever used?
default target_power 5 (14dBm)
*/
uint8_t target_power_index_mcs[8]; /* 0x28 - 0x2f */
/* One of CRYSTAL_FREQ_40M / CRYSTAL_FREQ_26M / CRYSTAL_FREQ_24M
The crystal configured here is the input to the PLL setting
calculations which are used to derive the CPU & APB peripheral
clock frequency, and probably the WiFi PLLs (unconfirmed.)
*/
uint8_t crystal_freq; /* 0x30 */
uint8_t _unused31; /* 0x31: Possibly high byte of crystal freq? */
/* One of SDIO_CONFIG_AUTO, SDIO_CONFIG_SDIOV1_1, SDIO_CONFIG_SDIOV2_0 */
uint8_t sdio_config; /* 0x32 */
/* BT coexistence pin configuration.
One of BT_COEXIST_CONFIG_NONE, BT_COEXIST_CONFIG_A,
BT_COEXIST_CONFIG_PRESENT, BT_COEXIST_CONFIG_B
*/
uint8_t bt_coexist_config; /* 0x33 */
/* BT coexistence pin protocol.
If no coexistence:
Either BT_COEXIST_PROTOCOL_WIFI_ONLY, or
BT_COEXIST_PROTOCOL_BT_ONLY.
If coexistence:
Combine one of
BT_COEXIST_PROTOCOL_FLAG_SEPARATE_ANT or
BT_COEXIST_PROTOCOL_FLAG_SHARE_ANT
with one of
BT_COEXIST_PROTOCOL_FLAG_BT_ACTIVE_ONLY or
BT_COEXIST_PROTOCOL_FLAG_BT_ACTIVE_BT_PRIORITY
*/
uint8_t bt_coexist_protocol; /* 0x34 */
/* Dual antenna configuration
One of DUAL_ANT_CONFIG_NONE, DUAL_ANT_CONFIG_DUAL,
DUAL_ANT_CONFIG_TX_GPIO0_HIGH_GPIO3_LOW,
DUAL_ANT_CONFIG_TX_GPIO0_LOW_GPIO3_HIGH
*/
uint8_t dual_ant_config; /* 0x35 */
uint8_t _reserved34; /* 0x36 */
/* For sharing crystal clock with other devices:
one of CRYSTAL_SLEEP_OFF, CRYSTAL_SLEEP_ON,
CRYSTAL_SLEEP_GPIO16, CRYSTAL_SLEEP_GPIO2
*/
uint8_t crystal_sleep; /* 0x37 */
uint8_t _unused38[8];
/* spur_freq_2 = spur_freq_2_primary / spur_freq_2_divisor */
uint8_t spur_freq_2_primary; /* 0x40 */
uint8_t spur_freq_2_divisor; /* 0x41 */
/* Bitmask to enable spur_freq_2 for each channel?
Appears to be a big endian short word?
*/
uint8_t spur_freq_2_en_h; /* 0x42 */
uint8_t spur_freq_2_en_l; /* 0x43 */
/* Not really clear what these do */
uint8_t spur_freq_cfg_msb; /* 0x44 */
uint8_t spur_freq_2_cfg_msb; /* 0x45 */
uint16_t spur_freq_3_cfg; /* 0x46 - 0x47 */
uint16_t spur_freq_4_cfg; /* 0x48 - 0x49 */
uint8_t _reserved4a[4]; /* 0x4a - 0x4d */
uint8_t _unused78[15]; /* 0x4e - 0x5c */
/* Flag to enable low power mode */
uint8_t low_power_en; /* 0x5d */
/* Low Power attenuation of RF gain stages 0 & 1
Attenuates transmit power if/when low_power_en is set.
Use one of the constants LP_ATTEN_STAGE01_0DB,
LP_ATTEN_STAGE01_2_5DB, LP_ATTEN_STAGE01_6DB,
LP_ATTEN_STAGE01_8_5DB, LP_ATTEN_STAGE01_11_5DB,
LP_ATTEN_STAGE01_14DB, LP_ATTEN_STAGE01_17_5DB,
LP_ATTEN_STAGE01_23DB.
*/
uint8_t lp_atten_stage01; /* 0x5e */
/* Low Power(?) attenuation of baseband gain
Units are minus 1/4 dB, ie value 4 == -1dB.
Maximum value is 24 (0x18) == -6dB
*/
uint8_t lp_atten_bb; /* 0x5f */
/* I believe this means, when pwr_ind_11b_en == 0 then the 802.11g
MCS 0 level from target_power_index_mcs are used to
determine 802.11b transmit power level.
However, when pwr_ind_11b_en == 1 then the index values in
pwr_ind_11b_0 & pwr_ind_11b_1 are used for 802.11b instead.
This is all unconfirmed, if you can confirm then please update
this comment.
*/
uint8_t pwr_ind_11b_en; /* 0x60 */
/* 802.11b low data rate power index (0~5).
Sets the power level index for operation at 1 & 2Mbps
*/
uint8_t pwr_ind_11b_0; /* 0x61 */
/* 802.11b high data rate power index (0~5)
Sets the power level index for operation at 5.5 & 11Mbps
*/
uint8_t pwr_ind_11b_1; /* 0x62 */
uint8_t _unused63[8]; /* 0x63 - 0x6a */
/* Set the voltage of PA_VDD, which appears to be an internal analog
reference voltage(?)
This field is called vdd33_const in the Arduino phy fields,
and relates to usage of the TOUT pin (ADC pin).
Set to PA_VDD_MEASURE_VCC (0xFF) and leave TOUT (ADC) pin
floating in order to use the ADC to measure the 3.3V input
voltage.
Set to value in the range 18-36 (1.8V to 3.6V) to set a
reference voltage(?) when using TOUT pin as an ADC input. I
think this is the reference voltage used to scale the 0-1V
which is allowed on the pin, in order to get an accurate
reading. So it should be set to a value that matches system
VCC... I think!
*/
uint8_t pa_vdd; /* 0x6b */
/* Disable RF calibration cycle for this many times */
uint8_t disable_rfcal_count; /* 0x6c */
uint8_t _unused6d[3];
/* Flags for frequency correction
A bitmask combination of any of: FREQ_CORRECT_DISABLE,
FREQ_CORRECT_ENABLE, FREQ_CORRECT_BB_160M, FREQ_CORRECT_FORCE
*/
uint8_t freq_correct_mode; /* 0x70 */
/* Force frequency offset adjustment (instead of auto measuring)
units are 1 = 8kHz, full range +/- 1016kHz.
Only used if FREQ_CORRECT_ENABLE and FREQ_CORRECT_FORCE are
set in freq_correct_mode.
Unclear whether setting FREQ_CORRECT_BB_160M (which allows only positive offsets) changes the usable range.
*/
int8_t force_freq_offset; /* 0x71 */
/* Use stored data in flash for RF calibration.
This field was previously called rf_cal_use_flash.
Acceptable values one of RF_CAL_MODE_SAVED, RF_CAL_MODE_TXPOWER_ONLY, RF_CAL_MODE_SAVED_2, RF_CAL_MODE_FULL.
*/
uint8_t rf_cal_mode; /* 0x72 */
uint8_t _unused73[13];
} sdk_phy_info_t;
/* Some sanity check static assertions. These can probably be
removed after this structure has been better tested.
*/
_Static_assert(sizeof(sdk_phy_info_t) == 128, "sdk_phy_info_t is wrong size!");
_Static_assert(offsetof(sdk_phy_info_t, version) == 5, "version at wrong offset");
_Static_assert(offsetof(sdk_phy_info_t, target_power) == 34, "target_power_qdb at wrong offset");
_Static_assert(offsetof(sdk_phy_info_t, bt_coexist_protocol) == 52, "bt_coexist_protocol at wrong offset");
_Static_assert(offsetof(sdk_phy_info_t, spur_freq_2_primary) == 64, "spur_freq_2_primary at wrong offset");
_Static_assert(offsetof(sdk_phy_info_t, lp_atten_stage01) == 94, "lp_atten_stage01 at wrong offset");
_Static_assert(offsetof(sdk_phy_info_t, pa_vdd) == 107, "pa_vdd aka vdd33_const at wrong offset");
_Static_assert(offsetof(sdk_phy_info_t, rf_cal_mode) == 114, "rf_cal_use_flash at wrong offset!");
/* Read the default PHY info into the supplied structure.
This function is weak-aliased to get_sdk_default_phy_info() so you
can replace it with your own if you want to vary the default values
- suggested way to do this is to call get_sdk_default_phy_info()
and then only update the fields you care about.
The default PHY info is used at startup whenever the version field
in the default sdk_phy_info_t does not match the version field
stored in flash. So you can increment the version field to force a
reset to defaults, regardless of what values are in flash.
*/
void get_default_phy_info(sdk_phy_info_t *info);
/* Read the "SDK default" PHY info as used by the Espressif SDK */
void get_sdk_default_phy_info(sdk_phy_info_t *info);
/* Read the PHY info currently stored in the SPI flash SDK configuration sector.
This PHY info is updated by the SDK following RF calibration, etc.
Note that the saved data may be corrupt - read the 'version' field to verify.
*/
void read_saved_phy_info(sdk_phy_info_t *info);
/* Update the saved PHY info in the SPI flash. A reset is necessary to use these values.
Note that the SDK may clobber these values, so it's recommended you reset ASAP after updating them.
*/
void write_saved_phy_info(const sdk_phy_info_t *info);
/* Dump known fields in the phy info structure to stdout,
if 'raw' flag is set then the raw hex values are also dumped.
*/
void dump_phy_info(const sdk_phy_info_t *info, bool raw);
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* PHY_INFO_H */

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cpu/esp8266/vendor/esp/rom.h vendored
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/* "Boot ROM" function signatures
Note that a lot of the ROM functions used in the IoT SDK aren't
referenced from the Espressif RTOS SDK, and are probably incompatible.
*/
/*
Copyright (c) 2015, SuperHouse Automation Pty Ltd
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef ROM_H
#define ROM_H
#include "esp/types.h"
#include "flashchip.h"
#ifdef __cplusplus
extern "C" {
#endif
void Cache_Read_Disable(void);
/* http://esp8266-re.foogod.com/wiki/Cache_Read_Enable
Note: when compiling non-OTA we use the ROM version of this
function, but for OTA we use the version in extras/rboot-ota that
maps the correct flash page for OTA support.
*/
void Cache_Read_Enable(uint32_t odd_even, uint32_t mb_count, uint32_t no_idea);
/* Low-level SPI flash read/write routines */
int Enable_QMode(sdk_flashchip_t *chip);
int Disable_QMode(sdk_flashchip_t *chip);
int SPI_page_program(sdk_flashchip_t *chip, uint32_t dest_addr, uint32_t *src_addr, uint32_t size);
int SPI_read_data(sdk_flashchip_t *chip, uint32_t src_addr, uint32_t *dest_addr, uint32_t size);
int SPI_write_enable(sdk_flashchip_t *chip);
int SPI_sector_erase(sdk_flashchip_t *chip, uint32_t addr);
int SPI_read_status(sdk_flashchip_t *chip, uint32_t *status);
int SPI_write_status(sdk_flashchip_t *chip, uint32_t status);
int Wait_SPI_Idle(sdk_flashchip_t *chip);
#ifdef __cplusplus
}
#endif
#endif /* ROM_H */

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cpu/esp8266/vendor/esp/rtcmem_regs.h vendored
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/* esp/rtcmem_regs.h
*
* ESP8266 RTC semi-persistent memory register definitions
*
* Not compatible with ESP SDK register access code.
*/
/*
Copyright (c) 2015, SuperHouse Automation Pty Ltd
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef RTCMEM_REGS_H
#define RTCMEM_REGS_H
#include "esp/types.h"
#include "common_macros.h"
#ifdef __cplusplus
extern "C" {
#endif
/* The RTC memory is a range of 256 words (1 KB) of general-purpose memory
* within the Real Time Clock peripheral. Because it's part of the RTC, it
* continues to be powered (and retains its contents) even when the ESP8266 is
* in its deepest sleep mode (and other RAM is lost). It can therefore be
* useful for keeping data which must be persisted through sleep or a reset.
*
* Note, however, that it is not "battery backed", or flash memory, and thus
* will not keep its contents if power is removed entirely.
*/
// We could just define these as 'volatile uint32_t *', but doing things this
// way means that the RTCMEM* defines will include array size information, so
// the C compiler can do bounds-checking for static arguments.
typedef volatile uint32_t rtcmem_array64_t[64];
typedef volatile uint32_t rtcmem_array128_t[128];
typedef volatile uint32_t rtcmem_array256_t[256];
#define RTCMEM_BASE 0x60001000
/* RTCMEM is an array covering the entire semi-persistent memory range */
#define RTCMEM (*(rtcmem_array256_t *)(RTCMEM_BASE))
/* RTCMEM_BACKUP / RTCMEM_SYSTEM / RTCMEM_USER are the same range, divided up
* into chunks by application/use, as defined by Espressif */
#define RTCMEM_BACKUP (*(rtcmem_array64_t *)(RTCMEM_BASE))
#define RTCMEM_SYSTEM (*(rtcmem_array64_t *)(RTCMEM_BASE + 0x100))
#define RTCMEM_USER (*(rtcmem_array128_t *)(RTCMEM_BASE + 0x200))
#ifdef __cplusplus
}
#endif
#endif /* RTCMEM_REGS_H */

271
cpu/esp8266/vendor/esp/spi_regs.h vendored
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/** esp/spi.h
*
* Configuration of SPI registers.
*
* Part of esp-open-rtos
* Copyright (C) 2015 Superhouse Automation Pty Ltd
* BSD Licensed as described in the file LICENSE
*/
/*
Copyright (c) 2015, SuperHouse Automation Pty Ltd
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef SPI_REGS_H
#define SPI_REGS_H
#ifndef DOXYGEN
#ifdef __cplusplus
extern "C" {
#endif
#include "esp/types.h"
#include "common_macros.h"
/* Register definitions for the SPI peripherals on the ESP8266.
*
* There are twp SPI devices built into the ESP8266:
* SPI(0) is at 0x60000200
* SPI(1) is at 0x60000100
* (note that the device number order is reversed in memory)
*
* Each device is allocated a block of 64 32-bit registers (256 bytes of
* address space) to communicate with application code.
*/
#define SPI_BASE 0x60000200
#define SPI(i) (*(struct SPI_REGS *)(0x60000200 - (i)*0x100))
#define SPI0_BASE SPI_BASE
#define SPI1_BASE (SPI_BASE - 0x100)
struct SPI_REGS {
uint32_t volatile CMD; // 0x00
uint32_t volatile ADDR; // 0x04
uint32_t volatile CTRL0; // 0x08
uint32_t volatile CTRL1; // 0x0c
uint32_t volatile RSTATUS; // 0x10
uint32_t volatile CTRL2; // 0x14
uint32_t volatile CLOCK; // 0x18
uint32_t volatile USER0; // 0x1c
uint32_t volatile USER1; // 0x20
uint32_t volatile USER2; // 0x24
uint32_t volatile WSTATUS; // 0x28
uint32_t volatile PIN; // 0x2c
uint32_t volatile SLAVE0; // 0x30
uint32_t volatile SLAVE1; // 0x34
uint32_t volatile SLAVE2; // 0x38
uint32_t volatile SLAVE3; // 0x3c
uint32_t volatile W[16]; // 0x40 - 0x7c
uint32_t volatile _unused[28]; // 0x80 - 0xec
uint32_t volatile EXT0; // 0xf0
uint32_t volatile EXT1; // 0xf4
uint32_t volatile EXT2; // 0xf8
uint32_t volatile EXT3; // 0xfc
};
_Static_assert(sizeof(struct SPI_REGS) == 0x100, "SPI_REGS is the wrong size");
/* Details for CMD register */
#define SPI_CMD_READ BIT(31)
#define SPI_CMD_WRITE_ENABLE BIT(30)
#define SPI_CMD_WRITE_DISABLE BIT(29)
#define SPI_CMD_READ_ID BIT(28)
#define SPI_CMD_READ_SR BIT(27)
#define SPI_CMD_WRITE_SR BIT(26)
#define SPI_CMD_PP BIT(25)
#define SPI_CMD_SE BIT(24)
#define SPI_CMD_BE BIT(23)
#define SPI_CMD_CE BIT(22)
#define SPI_CMD_DP BIT(21)
#define SPI_CMD_RES BIT(20)
#define SPI_CMD_HPM BIT(19)
#define SPI_CMD_USR BIT(18)
/* Details for CTRL0 register */
#define SPI_CTRL0_WR_BIT_ORDER BIT(26)
#define SPI_CTRL0_RD_BIT_ORDER BIT(25)
#define SPI_CTRL0_QIO_MODE BIT(24)
#define SPI_CTRL0_DIO_MODE BIT(23)
#define SPI_CTRL0_QOUT_MODE BIT(20)
#define SPI_CTRL0_DOUT_MODE BIT(14)
#define SPI_CTRL0_FASTRD_MODE BIT(13)
#define SPI_CTRL0_CLOCK_EQU_SYS_CLOCK BIT(12)
#define SPI_CTRL0_CLOCK_NUM_M 0x0000000F
#define SPI_CTRL0_CLOCK_NUM_S 8
#define SPI_CTRL0_CLOCK_HIGH_M 0x0000000F
#define SPI_CTRL0_CLOCK_HIGH_S 4
#define SPI_CTRL0_CLOCK_LOW_M 0x0000000F
#define SPI_CTRL0_CLOCK_LOW_S 0
/* Mask for the CLOCK_NUM/CLOCK_HIGH/CLOCK_LOW combined, in case one wants
* to set them all as a single value.
*/
#define SPI_CTRL0_CLOCK_M 0x00000FFF
#define SPI_CTRL0_CLOCK_S 0
/* Details for CTRL2 register */
#define SPI_CTRL2_CS_DELAY_NUM_M 0x0000000F
#define SPI_CTRL2_CS_DELAY_NUM_S 28
#define SPI_CTRL2_CS_DELAY_MODE_M 0x00000003
#define SPI_CTRL2_CS_DELAY_MODE_S 26
#define SPI_CTRL2_MOSI_DELAY_NUM_M 0x00000007
#define SPI_CTRL2_MOSI_DELAY_NUM_S 23
#define SPI_CTRL2_MOSI_DELAY_MODE_M 0x00000003
#define SPI_CTRL2_MOSI_DELAY_MODE_S 21
#define SPI_CTRL2_MISO_DELAY_NUM_M 0x00000007
#define SPI_CTRL2_MISO_DELAY_NUM_S 18
#define SPI_CTRL2_MISO_DELAY_MODE_M 0x00000003
#define SPI_CTRL2_MISO_DELAY_MODE_S 16
/* Details for CLOCK register */
#define SPI_CLOCK_EQU_SYS_CLOCK BIT(31)
#define SPI_CLOCK_DIV_PRE_M 0x00001FFF
#define SPI_CLOCK_DIV_PRE_S 18
#define SPI_CLOCK_COUNT_NUM_M 0x0000003F
#define SPI_CLOCK_COUNT_NUM_S 12
#define SPI_CLOCK_COUNT_HIGH_M 0x0000003F
#define SPI_CLOCK_COUNT_HIGH_S 6
#define SPI_CLOCK_COUNT_LOW_M 0x0000003F
#define SPI_CLOCK_COUNT_LOW_S 0
/* Mask for the COUNT_NUM/COUNT_HIGH/COUNT_LOW combined, in case one wants
* to set them all as a single value.
*/
#define SPI_CTRL0_COUNT_M 0x0003FFFF
#define SPI_CTRL0_COUNT_S 0
/* Details for USER0 register */
#define SPI_USER0_COMMAND BIT(31)
#define SPI_USER0_ADDR BIT(30)
#define SPI_USER0_DUMMY BIT(29)
#define SPI_USER0_MISO BIT(28)
#define SPI_USER0_MOSI BIT(27)
#define SPI_USER0_MOSI_HIGHPART BIT(25)
#define SPI_USER0_MISO_HIGHPART BIT(24)
#define SPI_USER0_SIO BIT(16)
#define SPI_USER0_FWRITE_QIO BIT(15)
#define SPI_USER0_FWRITE_DIO BIT(14)
#define SPI_USER0_FWRITE_QUAD BIT(13)
#define SPI_USER0_FWRITE_DUAL BIT(12)
#define SPI_USER0_WR_BYTE_ORDER BIT(11)
#define SPI_USER0_RD_BYTE_ORDER BIT(10)
#define SPI_USER0_CLOCK_OUT_EDGE BIT(7)
#define SPI_USER0_CLOCK_IN_EDGE BIT(6)
#define SPI_USER0_CS_SETUP BIT(5)
#define SPI_USER0_CS_HOLD BIT(4)
#define SPI_USER0_FLASH_MODE BIT(2)
#define SPI_USER0_DUPLEX BIT(0)
/* Details for USER1 register */
#define SPI_USER1_ADDR_BITLEN_M 0x0000003F
#define SPI_USER1_ADDR_BITLEN_S 26
#define SPI_USER1_MOSI_BITLEN_M 0x000001FF
#define SPI_USER1_MOSI_BITLEN_S 17
#define SPI_USER1_MISO_BITLEN_M 0x000001FF
#define SPI_USER1_MISO_BITLEN_S 8
#define SPI_USER1_DUMMY_CYCLELEN_M 0x000000FF
#define SPI_USER1_DUMMY_CYCLELEN_S 0
/* Details for USER2 register */
#define SPI_USER2_COMMAND_BITLEN_M 0x0000000F
#define SPI_USER2_COMMAND_BITLEN_S 28
#define SPI_USER2_COMMAND_VALUE_M 0x0000FFFF
#define SPI_USER2_COMMAND_VALUE_S 0
/* Details for PIN register */
#define SPI_PIN_IDLE_EDGE BIT(29) ///< CPOL
#define SPI_PIN_CS2_DISABLE BIT(2)
#define SPI_PIN_CS1_DISABLE BIT(1)
#define SPI_PIN_CS0_DISABLE BIT(0)
/* Details for SLAVE0 register */
#define SPI_SLAVE0_SYNC_RESET BIT(31)
#define SPI_SLAVE0_MODE BIT(30)
#define SPI_SLAVE0_WR_RD_BUF_EN BIT(29)
#define SPI_SLAVE0_WR_RD_STA_EN BIT(28)
#define SPI_SLAVE0_CMD_DEFINE BIT(27)
#define SPI_SLAVE0_TRANS_COUNT_M 0x0000000F
#define SPI_SLAVE0_TRANS_COUNT_S 23
#define SPI_SLAVE0_TRANS_DONE_EN BIT(9)
#define SPI_SLAVE0_WR_STA_DONE_EN BIT(8)
#define SPI_SLAVE0_RD_STA_DONE_EN BIT(7)
#define SPI_SLAVE0_WR_BUF_DONE_EN BIT(6)
#define SPI_SLAVE0_RD_BUF_DONE_EN BIT(5)
#define SPI_SLAVE0_INT_EN_M 0x0000001f
#define SPI_SLAVE0_INT_EN_S 5
#define SPI_SLAVE0_TRANS_DONE BIT(4)
#define SPI_SLAVE0_WR_STA_DONE BIT(3)
#define SPI_SLAVE0_RD_STA_DONE BIT(2)
#define SPI_SLAVE0_WR_BUF_DONE BIT(1)
#define SPI_SLAVE0_RD_BUF_DONE BIT(0)
/* Details for SLAVE1 register */
#define SPI_SLAVE1_STATUS_BITLEN_M 0x0000001F
#define SPI_SLAVE1_STATUS_BITLEN_S 27
#define SPI_SLAVE1_BUF_BITLEN_M 0x000001FF
#define SPI_SLAVE1_BUF_BITLEN_S 16
#define SPI_SLAVE1_RD_ADDR_BITLEN_M 0x0000003F
#define SPI_SLAVE1_RD_ADDR_BITLEN_S 10
#define SPI_SLAVE1_WR_ADDR_BITLEN_M 0x0000003F
#define SPI_SLAVE1_WR_ADDR_BITLEN_S 4
#define SPI_SLAVE1_WRSTA_DUMMY_ENABLE BIT(3)
#define SPI_SLAVE1_RDSTA_DUMMY_ENABLE BIT(2)
#define SPI_SLAVE1_WRBUF_DUMMY_ENABLE BIT(1)
#define SPI_SLAVE1_RDBUF_DUMMY_ENABLE BIT(0)
/* Details for SLAVE2 register */
#define SPI_SLAVE2_WRBUF_DUMMY_CYCLELEN_M 0x000000FF
#define SPI_SLAVE2_WRBUF_DUMMY_CYCLELEN_S 24
#define SPI_SLAVE2_RDBUF_DUMMY_CYCLELEN_M 0x000000FF
#define SPI_SLAVE2_RDBUF_DUMMY_CYCLELEN_S 16
#define SPI_SLAVE2_WRSTR_DUMMY_CYCLELEN_M 0x000000FF
#define SPI_SLAVE2_WRSTR_DUMMY_CYCLELEN_S 8
#define SPI_SLAVE2_RDSTR_DUMMY_CYCLELEN_M 0x000000FF
#define SPI_SLAVE2_RDSTR_DUMMY_CYCLELEN_S 0
/* Details for SLAVE3 register */
#define SPI_SLAVE3_WRSTA_CMD_VALUE_M 0x000000FF
#define SPI_SLAVE3_WRSTA_CMD_VALUE_S 24
#define SPI_SLAVE3_RDSTA_CMD_VALUE_M 0x000000FF
#define SPI_SLAVE3_RDSTA_CMD_VALUE_S 16
#define SPI_SLAVE3_WRBUF_CMD_VALUE_M 0x000000FF
#define SPI_SLAVE3_WRBUF_CMD_VALUE_S 8
#define SPI_SLAVE3_RDBUF_CMD_VALUE_M 0x000000FF
#define SPI_SLAVE3_RDBUF_CMD_VALUE_S 0
/* Details for EXT3 register */
#define SPI_EXT3_INT_HOLD_ENABLE_M 0x00000003
#define SPI_EXT3_INT_HOLD_ENABLE_S 0
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* SPI_REGS_H */

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/**
* The MIT License (MIT)
*
* Copyright (c) 2016 sheinz (https://github.com/sheinz)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifdef RIOT_VERSION
#include "esp/spiflash.h"
#include "esp/flashchip.h"
#include "esp/rom.h"
#include "esp/spi_regs.h"
#include "esp/FreeRTOS.h"
#else
#include "include/spiflash.h"
#include "include/flashchip.h"
#include "include/esp/rom.h"
#include "include/esp/spi_regs.h"
#include <FreeRTOS.h>
#endif
#include <string.h>
/**
* Note about Wait_SPI_Idle.
*
* Each write/erase flash operation sets BUSY bit in flash status register.
* If attempt to access flash while BUSY bit is set operation will fail.
* Function Wait_SPI_Idle loops until this bit is not cleared.
*
* The approach in the following code is that each write function that is
* accessible from the outside should leave flash in Idle state.
* The read operations doesn't set BUSY bit in a flash. So they do not wait.
* They relay that previous operation is completely finished.
*
* This approach is different from ESP8266 bootrom where Wait_SPI_Idle is
* called where it needed and not.
*/
#define SPI_WRITE_MAX_SIZE 64
// 64 bytes read causes hang
// http://bbs.espressif.com/viewtopic.php?f=6&t=2439
#define SPI_READ_MAX_SIZE 60
/**
* Low level SPI flash write. Write block of data up to 64 bytes.
*/
static inline void IRAM spi_write_data(sdk_flashchip_t *chip, uint32_t addr,
uint8_t *buf, uint32_t size)
{
uint32_t words = size >> 2;
if (size & 0b11) {
words++;
}
Wait_SPI_Idle(chip); // wait for previous write to finish
SPI(0).ADDR = (addr & 0x00FFFFFF) | (size << 24);
memcpy((void*)SPI(0).W, buf, words<<2);
__asm__ volatile("memw");
SPI_write_enable(chip);
SPI(0).CMD = SPI_CMD_PP;
while (SPI(0).CMD) {}
}
/**
* Write a page of flash. Data block should not cross page boundary.
*/
static bool IRAM spi_write_page(sdk_flashchip_t *flashchip, uint32_t dest_addr,
uint8_t *buf, uint32_t size)
{
// check if block to write doesn't cross page boundary
if (flashchip->page_size < size + (dest_addr % flashchip->page_size)) {
return false;
}
if (size < 1) {
return true;
}
while (size >= SPI_WRITE_MAX_SIZE) {
spi_write_data(flashchip, dest_addr, buf, SPI_WRITE_MAX_SIZE);
size -= SPI_WRITE_MAX_SIZE;
dest_addr += SPI_WRITE_MAX_SIZE;
buf += SPI_WRITE_MAX_SIZE;
if (size < 1) {
return true;
}
}
spi_write_data(flashchip, dest_addr, buf, size);
return true;
}
/**
* Split block of data into pages and write pages.
*/
static bool IRAM spi_write(uint32_t addr, uint8_t *dst, uint32_t size)
{
if (sdk_flashchip.chip_size < (addr + size)) {
return false;
}
uint32_t write_bytes_to_page = sdk_flashchip.page_size -
(addr % sdk_flashchip.page_size); // TODO: place for optimization
if (size < write_bytes_to_page) {
if (!spi_write_page(&sdk_flashchip, addr, dst, size)) {
return false;
}
} else {
if (!spi_write_page(&sdk_flashchip, addr, dst, write_bytes_to_page)) {
return false;
}
uint32_t offset = write_bytes_to_page;
uint32_t pages_to_write = (size - offset) / sdk_flashchip.page_size;
for (uint32_t i = 0; i < pages_to_write; i++) {
if (!spi_write_page(&sdk_flashchip, addr + offset,
dst + offset, sdk_flashchip.page_size)) {
return false;
}
offset += sdk_flashchip.page_size;
}
if (!spi_write_page(&sdk_flashchip, addr + offset,
dst + offset, size - offset)) {
return false;
}
}
return true;
}
bool IRAM spiflash_write(uint32_t addr, uint8_t *buf, uint32_t size)
{
bool result = false;
if (buf) {
vPortEnterCritical();
Cache_Read_Disable();
result = spi_write(addr, buf, size);
// make sure all write operations is finished before exiting
Wait_SPI_Idle(&sdk_flashchip);
Cache_Read_Enable(0, 0, 1);
vPortExitCritical();
}
return result;
}
/**
* Read SPI flash up to 64 bytes.
*/
static inline void IRAM read_block(sdk_flashchip_t *chip, uint32_t addr,
uint8_t *buf, uint32_t size)
{
SPI(0).ADDR = (addr & 0x00FFFFFF) | (size << 24);
SPI(0).CMD = SPI_CMD_READ;
while (SPI(0).CMD) {};
__asm__ volatile("memw");
memcpy(buf, (const void*)SPI(0).W, size);
}
/**
* Read SPI flash data. Data region doesn't need to be page aligned.
*/
static inline bool IRAM read_data(sdk_flashchip_t *flashchip, uint32_t addr,
uint8_t *dst, uint32_t size)
{
if (size < 1) {
return true;
}
if ((addr + size) > flashchip->chip_size) {
return false;
}
while (size >= SPI_READ_MAX_SIZE) {
read_block(flashchip, addr, dst, SPI_READ_MAX_SIZE);
dst += SPI_READ_MAX_SIZE;
size -= SPI_READ_MAX_SIZE;
addr += SPI_READ_MAX_SIZE;
}
if (size > 0) {
read_block(flashchip, addr, dst, size);
}
return true;
}
bool IRAM spiflash_read(uint32_t dest_addr, uint8_t *buf, uint32_t size)
{
bool result = false;
if (buf) {
vPortEnterCritical();
Cache_Read_Disable();
result = read_data(&sdk_flashchip, dest_addr, buf, size);
Cache_Read_Enable(0, 0, 1);
vPortExitCritical();
}
return result;
}
bool IRAM spiflash_erase_sector(uint32_t addr)
{
if ((addr + sdk_flashchip.sector_size) > sdk_flashchip.chip_size) {
return false;
}
if (addr & 0xFFF) {
return false;
}
vPortEnterCritical();
Cache_Read_Disable();
SPI_write_enable(&sdk_flashchip);
SPI(0).ADDR = addr & 0x00FFFFFF;
SPI(0).CMD = SPI_CMD_SE;
while (SPI(0).CMD) {};
Wait_SPI_Idle(&sdk_flashchip);
Cache_Read_Enable(0, 0, 1);
vPortExitCritical();
return true;
}

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/**
* The MIT License (MIT)
*
* Copyright (c) 2016 sheinz (https://github.com/sheinz)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef SPIFLASH_H
#define SPIFLASH_H
#include <stdint.h>
#include <stdbool.h>
#include "common_macros.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SPI_FLASH_SECTOR_SIZE 4096
/**
* Read data from SPI flash.
*
* @param addr Address to read from. Can be not aligned.
* @param buf Buffer to read to. Doesn't have to be aligned.
* @param size Size of data to read. Buffer size must be >= than data size.
*
* @return true if success, otherwise false
*/
bool IRAM spiflash_read(uint32_t addr, uint8_t *buf, uint32_t size);
/**
* Write data to SPI flash.
*
* @param addr Address to write to. Can be not aligned.
* @param buf Buffer of data to write to flash. Doesn't have to be aligned.
* @param size Size of data to write. Buffer size must be >= than data size.
*
* @return true if success, otherwise false
*/
bool IRAM spiflash_write(uint32_t addr, uint8_t *buf, uint32_t size);
/**
* Erase a sector.
*
* @param addr Address of sector to erase. Must be sector aligned.
*
* @return true if success, otherwise false
*/
bool IRAM spiflash_erase_sector(uint32_t addr);
#ifdef __cplusplus
}
#endif
#endif /* SPIFLASH_H */

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/* esp/wdev_regs.h
*
* ESP8266 register definitions for the "wdev" region (0x3FF2xxx)
*
* In the DPORT memory space, alongside DPORT regs. However mostly
* concerned with the WiFi hardware interface.
*
* Not compatible with ESP SDK register access code.
*/
/*
Copyright (c) 2015, SuperHouse Automation Pty Ltd
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef WDEV_REGS_H
#define WDEV_REGS_H
#ifndef DOXYGEN
#include "esp/types.h"
#include "common_macros.h"
#ifdef __cplusplus
extern "C" {
#endif
#define WDEV_BASE 0x3FF20000
#define WDEV (*(struct WDEV_REGS *)(WDEV_BASE))
/* Note: This memory region is not currently well understood. Pretty much all
* of the definitions here are from reverse-engineering the Espressif SDK code,
* many are just educated guesses, and almost certainly some are misleading or
* wrong. If you can improve on any of this, please contribute!
*/
struct WDEV_REGS {
uint32_t volatile _unknown0[768]; // 0x0000 - 0x0bfc
uint32_t volatile SYS_TIME; // 0x0c00
uint32_t volatile _unknown1[144]; // 0x0c04 - 0x0e40
uint32_t volatile HWRNG; // 0xe44 HW RNG, see http://esp8266-re.foogod.com/wiki/Random_Number_Generator
} __attribute__ (( packed ));
_Static_assert(sizeof(struct WDEV_REGS) == 0xe48, "WDEV_REGS is the wrong size");
/* Extra paranoid check about the HWRNG address, as if this becomes
wrong there will be no obvious symptoms apart from a lack of
entropy.
*/
_Static_assert(&WDEV.HWRNG == (void*)0x3FF20E44, "HWRNG register is at wrong address");
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* WDEV_REGS_H */

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The files in this directory are either from the [ESP8266_NONOS_SDK](https://github.com/espressif/ESP8266_NONOS_SDK.git) or from the [ESP_RTOS_SDK](https://github.com/espressif/ESP8266_RTOS_SDK.git) for ESP8266. All of these files are copyright of Espressif Systems (Shanghai) Pte., Ltd. Please note the copyright notice in these files.

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/*
* ESPRESSIF MIT License
*
* Copyright (c) 2016 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef C_TYPES_H
#define C_TYPES_H
/* Following header guards are necessary to avoid conflicts with original */
/* header in SDK where _C_TYPES_H_ is used */
#ifndef _C_TYPES_H_
#define _C_TYPES_H_
#ifndef DOXYGEN
#ifndef _DTLS_GLOBAL_H_
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef signed char sint8_t;
typedef signed short sint16_t;
typedef signed long sint32_t;
typedef signed long long sint64_t;
typedef unsigned long long u_int64_t;
typedef float real32_t;
typedef double real64_t;
typedef unsigned char uint8;
typedef unsigned char u8;
typedef signed char sint8;
typedef signed char int8;
typedef signed char s8;
typedef unsigned short uint16;
typedef unsigned short u16;
typedef signed short sint16;
typedef signed short s16;
typedef unsigned int uint32;
typedef unsigned int u_int;
typedef unsigned int u32;
typedef signed int sint32;
typedef signed int s32;
typedef int int32;
typedef signed long long sint64;
typedef unsigned long long uint64;
typedef unsigned long long u64;
typedef float real32;
typedef double real64;
#define __le16 u16
typedef unsigned int size_t;
/* #define __packed __attribute__((packed)) */
#define LOCAL static
#ifndef NULL
#define NULL (void *)0
#endif /* NULL */
/* probably should not put STATUS here */
typedef enum {
OK = 0,
FAIL,
PENDING,
BUSY,
CANCEL,
} STATUS;
#ifndef BIT
#define BIT(nr) (1UL << (nr))
#endif
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
#define DMEM_ATTR __attribute__((section(".bss")))
#define SHMEM_ATTR
#ifdef ICACHE_FLASH
#define ICACHE_FLASH_ATTR __attribute__((section(".irom0.text")))
#define ICACHE_RODATA_ATTR __attribute__((section(".irom.text")))
#else
#define ICACHE_FLASH_ATTR
#define ICACHE_RODATA_ATTR
#endif /* ICACHE_FLASH */
#define STORE_ATTR __attribute__((aligned(4)))
#ifndef __cplusplus
#define BOOL bool
#ifndef true
#define true (1)
#endif
#ifndef false
#define false (0)
#endif
#ifndef TRUE
#define TRUE true
#endif
#ifndef FALSE
#define FALSE false
#endif
#endif /* !__cplusplus */
#ifdef __cplusplus
}
#endif
#endif /* _DTLS_GLOBAL_H_ */
#endif /* DOXYGEN */
#endif /* _C_TYPES_H_ */
#endif /* C_TYPES_H */

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/*
* ESPRESSIF MIT License
*
* Copyright (c) 2016 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef EAGLE_SOC_H
#define EAGLE_SOC_H
#ifndef DOXYGEN
#ifdef __cplusplus
extern "C" {
#endif
//Register Bits{{
#define BIT31 0x80000000
#define BIT30 0x40000000
#define BIT29 0x20000000
#define BIT28 0x10000000
#define BIT27 0x08000000
#define BIT26 0x04000000
#define BIT25 0x02000000
#define BIT24 0x01000000
#define BIT23 0x00800000
#define BIT22 0x00400000
#define BIT21 0x00200000
#define BIT20 0x00100000
#define BIT19 0x00080000
#define BIT18 0x00040000
#define BIT17 0x00020000
#define BIT16 0x00010000
#define BIT15 0x00008000
#define BIT14 0x00004000
#define BIT13 0x00002000
#define BIT12 0x00001000
#define BIT11 0x00000800
#define BIT10 0x00000400
#define BIT9 0x00000200
#define BIT8 0x00000100
#define BIT7 0x00000080
#define BIT6 0x00000040
#define BIT5 0x00000020
#define BIT4 0x00000010
#define BIT3 0x00000008
#define BIT2 0x00000004
#define BIT1 0x00000002
#define BIT0 0x00000001
//}}
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|((value)<<(shift)) ))
//}}
//Periheral Clock {{
#define APB_CLK_FREQ 80*1000000 //unit: Hz
#define UART_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (APB_CLK_FREQ>>8) //divided by 256
//}}
//Peripheral device base address define{{
#define PERIPHS_DPORT_BASEADDR 0x3ff00000
#define PERIPHS_GPIO_BASEADDR 0x60000300
#define PERIPHS_TIMER_BASEDDR 0x60000600
#define PERIPHS_RTC_BASEADDR 0x60000700
#define PERIPHS_IO_MUX 0x60000800
//}}
//Interrupt remap control registers define{{
#define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR+0x04)
#define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
#define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
//}}
//GPIO reg {{
#define GPIO_REG_READ(reg) READ_PERI_REG(PERIPHS_GPIO_BASEADDR + reg)
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + reg, val)
#define GPIO_OUT_ADDRESS 0x00
#define GPIO_OUT_W1TS_ADDRESS 0x04
#define GPIO_OUT_W1TC_ADDRESS 0x08
#define GPIO_ENABLE_ADDRESS 0x0c
#define GPIO_ENABLE_W1TS_ADDRESS 0x10
#define GPIO_ENABLE_W1TC_ADDRESS 0x14
#define GPIO_OUT_W1TC_DATA_MASK 0x0000ffff
#define GPIO_IN_ADDRESS 0x18
#define GPIO_STATUS_ADDRESS 0x1c
#define GPIO_STATUS_W1TS_ADDRESS 0x20
#define GPIO_STATUS_W1TC_ADDRESS 0x24
#define GPIO_STATUS_INTERRUPT_MASK 0x0000ffff
#define GPIO_RTC_CALIB_SYNC PERIPHS_GPIO_BASEADDR+0x6c
#define RTC_CALIB_START BIT31 //first write to zero, then to one to start
#define RTC_PERIOD_NUM_MASK 0x3ff //max 8ms
#define GPIO_RTC_CALIB_VALUE PERIPHS_GPIO_BASEADDR+0x70
#define RTC_CALIB_RDY_S 31 //after measure, flag to one, when start from zero to one, turn to zero
#define RTC_CALIB_VALUE_MASK 0xfffff
#define GPIO_PIN0_ADDRESS 0x28
#define GPIO_ID_PIN0 0
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15)
#define GPIO_ID_NONE 0xffffffff
#define GPIO_PIN_COUNT 16
#define GPIO_PIN_CONFIG_MSB 12
#define GPIO_PIN_CONFIG_LSB 11
#define GPIO_PIN_CONFIG_MASK 0x00001800
#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
#define GPIO_WAKEUP_ENABLE 1
#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE)
#define GPIO_PIN_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
#define GPIO_PIN_INT_TYPE_MASK 0x380
#define GPIO_PIN_INT_TYPE_MSB 9
#define GPIO_PIN_INT_TYPE_LSB 7
#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
#define GPIO_PAD_DRIVER_ENABLE 1
#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE)
#define GPIO_PIN_PAD_DRIVER_MSB 2
#define GPIO_PIN_PAD_DRIVER_LSB 2
#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
#define GPIO_AS_PIN_SOURCE 0
#define SIGMA_AS_PIN_SOURCE (~GPIO_AS_PIN_SOURCE)
#define GPIO_PIN_SOURCE_MSB 0
#define GPIO_PIN_SOURCE_LSB 0
#define GPIO_PIN_SOURCE_MASK 0x00000001
#define GPIO_PIN_SOURCE_GET(x) (((x) & GPIO_PIN_SOURCE_MASK) >> GPIO_PIN_SOURCE_LSB)
#define GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK)
// }}
// TIMER reg {{
#define RTC_REG_READ(addr) READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr)
#define RTC_REG_WRITE(addr, val) WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val)
#define RTC_CLR_REG_MASK(reg, mask) CLEAR_PERI_REG_MASK(PERIPHS_TIMER_BASEDDR +reg, mask)
/* Returns the current time according to the timer timer. */
#define NOW() RTC_REG_READ(FRC2_COUNT_ADDRESS)
//load initial_value to timer1
#define FRC1_LOAD_ADDRESS 0x00
//timer1's counter value(count from initial_value to 0)
#define FRC1_COUNT_ADDRESS 0x04
#define FRC1_CTRL_ADDRESS 0x08
//clear timer1's interrupt when write this address
#define FRC1_INT_ADDRESS 0x0c
#define FRC1_INT_CLR_MASK 0x00000001
//timer2's counter value(count from initial_value to 0)
#define FRC2_COUNT_ADDRESS 0x24
// }}
//RTC reg {{
#define REG_RTC_BASE PERIPHS_RTC_BASEADDR
#define RTC_STORE0 (REG_RTC_BASE + 0x030)
#define RTC_STORE1 (REG_RTC_BASE + 0x034)
#define RTC_STORE2 (REG_RTC_BASE + 0x038)
#define RTC_STORE3 (REG_RTC_BASE + 0x03C)
#define RTC_GPIO_OUT (REG_RTC_BASE + 0x068)
#define RTC_GPIO_ENABLE (REG_RTC_BASE + 0x074)
#define RTC_GPIO_IN_DATA (REG_RTC_BASE + 0x08C)
#define RTC_GPIO_CONF (REG_RTC_BASE + 0x090)
#define PAD_XPD_DCDC_CONF (REG_RTC_BASE + 0x0A0)
//}}
//PIN Mux reg {{
#define PERIPHS_IO_MUX_FUNC 0x13
#define PERIPHS_IO_MUX_FUNC_S 4
#define PERIPHS_IO_MUX_PULLUP BIT7
#define PERIPHS_IO_MUX_PULLUP2 BIT6
#define PERIPHS_IO_MUX_SLEEP_PULLUP BIT3
#define PERIPHS_IO_MUX_SLEEP_PULLUP2 BIT2
#define PERIPHS_IO_MUX_SLEEP_OE BIT1
#define PERIPHS_IO_MUX_OE BIT0
#define PERIPHS_IO_MUX_CONF_U (PERIPHS_IO_MUX + 0x00)
#define SPI0_CLK_EQU_SYS_CLK BIT8
#define SPI1_CLK_EQU_SYS_CLK BIT9
#define PERIPHS_IO_MUX_MTDI_U (PERIPHS_IO_MUX + 0x04)
#define FUNC_GPIO12 3
#define PERIPHS_IO_MUX_MTCK_U (PERIPHS_IO_MUX + 0x08)
#define FUNC_GPIO13 3
#define PERIPHS_IO_MUX_MTMS_U (PERIPHS_IO_MUX + 0x0C)
#define FUNC_GPIO14 3
#define PERIPHS_IO_MUX_MTDO_U (PERIPHS_IO_MUX + 0x10)
#define FUNC_GPIO15 3
#define FUNC_U0RTS 4
#define PERIPHS_IO_MUX_U0RXD_U (PERIPHS_IO_MUX + 0x14)
#define FUNC_GPIO3 3
#define PERIPHS_IO_MUX_U0TXD_U (PERIPHS_IO_MUX + 0x18)
#define FUNC_U0TXD 0
#define FUNC_GPIO1 3
#define PERIPHS_IO_MUX_SD_CLK_U (PERIPHS_IO_MUX + 0x1c)
#define FUNC_SDCLK 0
#define FUNC_SPICLK 1
#define PERIPHS_IO_MUX_SD_DATA0_U (PERIPHS_IO_MUX + 0x20)
#define FUNC_SDDATA0 0
#define FUNC_SPIQ 1
#define FUNC_U1TXD 4
#define PERIPHS_IO_MUX_SD_DATA1_U (PERIPHS_IO_MUX + 0x24)
#define FUNC_SDDATA1 0
#define FUNC_SPID 1
#define FUNC_U1RXD 4
#define FUNC_SDDATA1_U1RXD 7
#define PERIPHS_IO_MUX_SD_DATA2_U (PERIPHS_IO_MUX + 0x28)
#define FUNC_SDDATA2 0
#define FUNC_SPIHD 1
#define FUNC_GPIO9 3
#define PERIPHS_IO_MUX_SD_DATA3_U (PERIPHS_IO_MUX + 0x2c)
#define FUNC_SDDATA3 0
#define FUNC_SPIWP 1
#define FUNC_GPIO10 3
#define PERIPHS_IO_MUX_SD_CMD_U (PERIPHS_IO_MUX + 0x30)
#define FUNC_SDCMD 0
#define FUNC_SPICS0 1
#define PERIPHS_IO_MUX_GPIO0_U (PERIPHS_IO_MUX + 0x34)
#define FUNC_GPIO0 0
#define PERIPHS_IO_MUX_GPIO2_U (PERIPHS_IO_MUX + 0x38)
#define FUNC_GPIO2 0
#define FUNC_U1TXD_BK 2
#define FUNC_U0TXD_BK 4
#define PERIPHS_IO_MUX_GPIO4_U (PERIPHS_IO_MUX + 0x3C)
#define FUNC_GPIO4 0
#define PERIPHS_IO_MUX_GPIO5_U (PERIPHS_IO_MUX + 0x40)
#define FUNC_GPIO5 0
#define PIN_PULLUP_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP)
#define PIN_PULLUP_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) do { \
WRITE_PERI_REG(PIN_NAME, \
(READ_PERI_REG(PIN_NAME) \
& (~(PERIPHS_IO_MUX_FUNC<<PERIPHS_IO_MUX_FUNC_S))) \
|( (((FUNC&BIT2)<<2)|(FUNC&0x3))<<PERIPHS_IO_MUX_FUNC_S) ); \
} while (0)
//}}
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* EAGLE_SOC_H */

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cpu/esp8266/vendor/espressif/ets_sys.h vendored
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/*
* ESPRESSIF MIT License
*
* Copyright (c) 2016 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef ETS_SYS_H
#define ETS_SYS_H
/* Following header guards are necessary to avoid conflicts with original */
/* header in SDK where _ETS_SYS_H is used */
#ifndef _ETS_SYS_H
#define _ETS_SYS_H
#ifndef DOXYGEN
#include "c_types.h"
#include "eagle_soc.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t ETSSignal;
typedef uint32_t ETSParam;
typedef struct ETSEventTag ETSEvent;
struct ETSEventTag {
ETSSignal sig;
ETSParam par;
};
typedef void (*ETSTask)(ETSEvent *e);
/* timer related */
typedef uint32_t ETSHandle;
typedef void ETSTimerFunc(void *timer_arg);
typedef struct _ETSTIMER_ {
struct _ETSTIMER_ *timer_next;
uint32_t timer_expire;
uint32_t timer_period;
ETSTimerFunc *timer_func;
void *timer_arg;
} ETSTimer;
/* interrupt related */
#define ETS_SDIO_INUM 1
#define ETS_SPI_INUM 2
#define ETS_GPIO_INUM 4
#define ETS_UART_INUM 5
#define ETS_UART1_INUM 5
#define ETS_FRC_TIMER1_INUM 9 /* use edge*/
typedef void (* ets_isr_t)(void *);
void ets_intr_lock(void);
void ets_intr_unlock(void);
void ets_isr_attach(int i, ets_isr_t func, void *arg);
void NmiTimSetFunc(void (*func)(void));
#define ETS_INTR_LOCK() \
ets_intr_lock()
#define ETS_INTR_UNLOCK() \
ets_intr_unlock()
#define ETS_FRC_TIMER1_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_FRC_TIMER1_INUM, (func), (void *)(arg))
#define ETS_FRC_TIMER1_NMI_INTR_ATTACH(func) \
NmiTimSetFunc(func)
#define ETS_SDIO_INTR_ATTACH(func, arg)\
ets_isr_attach(ETS_SDIO_INUM, (func), (void *)(arg))
#define ETS_GPIO_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_GPIO_INUM, (func), (void *)(arg))
#define ETS_UART_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_UART_INUM, (func), (void *)(arg))
#define ETS_SPI_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_SPI_INUM, (func), (void *)(arg))
#define ETS_INTR_ENABLE(inum) \
ets_isr_unmask((1<<inum))
#define ETS_INTR_DISABLE(inum) \
ets_isr_mask((1<<inum))
#define ETS_UART_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_UART_INUM)
#define ETS_UART_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_UART_INUM)
#define ETS_FRC1_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_FRC_TIMER1_INUM)
#define ETS_FRC1_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_FRC_TIMER1_INUM)
#define ETS_GPIO_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_GPIO_INUM)
#define ETS_GPIO_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_GPIO_INUM)
#define ETS_SPI_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_SPI_INUM)
#define ETS_SPI_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_SPI_INUM)
#define ETS_SDIO_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_SDIO_INUM)
#define ETS_SDIO_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_SDIO_INUM)
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* _ETS_SYS_H */
#endif /* ETS_SYS_H */

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/*
* ESPRESSIF MIT License
*
* Copyright (c) 2016 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef GPIO_H
#define GPIO_H
#ifndef DOXYGEN
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_ADDRESS + i*4)
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
typedef enum {
GPIO_PIN_INTR_DISABLE = 0,
GPIO_PIN_INTR_POSEDGE = 1,
GPIO_PIN_INTR_NEGEDGE = 2,
GPIO_PIN_INTR_ANYEDGE = 3,
GPIO_PIN_INTR_LOLEVEL = 4,
GPIO_PIN_INTR_HILEVEL = 5
} GPIO_INT_TYPE;
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
gpio_output_set((bit_value)<<gpio_no, ((~(bit_value))&0x01)<<gpio_no, 1<<gpio_no,0)
#define GPIO_DIS_OUTPUT(gpio_no) gpio_output_set(0,0,0, 1<<gpio_no)
#define GPIO_INPUT_GET(gpio_no) ((gpio_input_get()>>gpio_no)&BIT0)
/* GPIO interrupt handler, registered through gpio_intr_handler_register */
typedef void (* gpio_intr_handler_fn_t)(uint32 intr_mask, void *arg);
/*
* Initialize GPIO. This includes reading the GPIO Configuration DataSet
* to initialize "output enables" and pin configurations for each gpio pin.
* Must be called once during startup.
*/
// conflicts with RIOT's gpio.h // void gpio_init(void);
/*
* Change GPIO pin output by setting, clearing, or disabling pins.
* In general, it is expected that a bit will be set in at most one
* of these masks. If a bit is clear in all masks, the output state
* remains unchanged.
*
* There is no particular ordering guaranteed; so if the order of
* writes is significant, calling code should divide a single call
* into multiple calls.
*/
void gpio_output_set(uint32 set_mask,
uint32 clear_mask,
uint32 enable_mask,
uint32 disable_mask);
/*
* Sample the value of GPIO input pins and returns a bitmask.
*/
uint32 gpio_input_get(void);
/*
* Set the specified GPIO register to the specified value.
* This is a very general and powerful interface that is not
* expected to be used during normal operation. It is intended
* mainly for debug, or for unusual requirements.
*/
void gpio_register_set(uint32 reg_id, uint32 value);
/* Get the current value of the specified GPIO register. */
uint32 gpio_register_get(uint32 reg_id);
/*
* Register an application-specific interrupt handler for GPIO pin
* interrupts. Once the interrupt handler is called, it will not
* be called again until after a call to gpio_intr_ack. Any GPIO
* interrupts that occur during the interim are masked.
*
* The application-specific handler is called with a mask of
* pending GPIO interrupts. After processing pin interrupts, the
* application-specific handler may wish to use gpio_intr_pending
* to check for any additional pending interrupts before it returns.
*/
void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg);
/* Determine which GPIO interrupts are pending. */
uint32 gpio_intr_pending(void);
/*
* Acknowledge GPIO interrupts.
* Intended to be called from the gpio_intr_handler_fn.
*/
void gpio_intr_ack(uint32 ack_mask);
void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state);
void gpio_pin_wakeup_disable(void);
void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state);
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* GPIO_H */

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103
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/*
* ESPRESSIF MIT License
*
* Copyright (c) 2016 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef OSAPI_H
#define OSAPI_H
#ifndef DOXYGEN
#include <string.h>
#include "os_type.h"
#include "user_config.h"
#ifdef __cplusplus
extern "C" {
#endif
void ets_bzero(void *s, size_t n);
void ets_delay_us(uint16_t us);
void ets_install_putc1(void (*p)(char c));
#define os_bzero ets_bzero
#define os_delay_us ets_delay_us
#define os_install_putc1 ets_install_putc1
int ets_memcmp(const void *str1, const void *str2, unsigned int nbyte);
void *ets_memcpy(void *dest, const void *src, unsigned int nbyte);
void *ets_memmove(void *dest, const void *src, unsigned int nbyte);
void *ets_memset(void *dest, int val, unsigned int nbyte);
int ets_strcmp(const char *s1, const char *s2);
char *ets_strcpy(char *s1, const char *s2);
int ets_strlen(const char *s);
int ets_strncmp(const char *s1, const char *s2, unsigned int n);
char *ets_strncpy(char *s1, const char *s2, unsigned int n);
char *ets_strstr(const char *s1, const char *s2);
#define os_memcmp ets_memcmp
#define os_memcpy ets_memcpy
#define os_memmove ets_memmove
#define os_memset ets_memset
#define os_strcat strcat
#define os_strchr strchr
#define os_strcmp ets_strcmp
#define os_strcpy ets_strcpy
#define os_strlen ets_strlen
#define os_strncmp ets_strncmp
#define os_strncpy ets_strncpy
#define os_strstr ets_strstr
void ets_timer_arm_new(os_timer_t *ptimer, uint32_t time, bool repeat_flag, bool ms_flag);
void ets_timer_disarm(os_timer_t *ptimer);
void ets_timer_setfn(os_timer_t *ptimer, os_timer_func_t *pfunction, void *parg);
#ifdef USE_US_TIMER
#define os_timer_arm_us(a, b, c) ets_timer_arm_new(a, b, c, 0)
#endif
#define os_timer_arm(a, b, c) ets_timer_arm_new(a, b, c, 1)
#define os_timer_disarm ets_timer_disarm
#define os_timer_setfn ets_timer_setfn
int ets_sprintf(char *str, const char *format, ...) __attribute__ ((format (printf, 2, 3)));
int os_printf_plus(const char *format, ...) __attribute__ ((format (printf, 1, 2)));
#define os_sprintf ets_sprintf
#ifdef USE_OPTIMIZE_PRINTF
#define os_printf(fmt, ...) do { \
static const char flash_str[] ICACHE_RODATA_ATTR STORE_ATTR = fmt; \
os_printf_plus(flash_str, ##__VA_ARGS__); \
} while(0)
#else
#define os_printf os_printf_plus
#endif
unsigned long os_random(void);
int os_get_random(unsigned char *buf, size_t len);
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* OSAPI_H */

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/*
* ESPRESSIF MIT License
*
* Copyright (c) 2016 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SPI_FLASH_H
#define SPI_FLASH_H
#ifndef DOXYGEN
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SPI_FLASH_RESULT_OK,
SPI_FLASH_RESULT_ERR,
SPI_FLASH_RESULT_TIMEOUT
} SpiFlashOpResult;
typedef struct{
uint32 deviceId;
uint32 chip_size; // chip size in byte
uint32 block_size;
uint32 sector_size;
uint32 page_size;
uint32 status_mask;
} SpiFlashChip;
#define SPI_FLASH_SEC_SIZE 4096
uint32 spi_flash_get_id(void);
SpiFlashOpResult spi_flash_erase_sector(uint16 sec);
SpiFlashOpResult spi_flash_write(uint32 des_addr, uint32 *src_addr, uint32 size);
SpiFlashOpResult spi_flash_read(uint32 src_addr, uint32 *des_addr, uint32 size);
typedef SpiFlashOpResult (* user_spi_flash_read)(
SpiFlashChip *spi,
uint32 src_addr,
uint32 *des_addr,
uint32 size);
void spi_flash_set_read_func(user_spi_flash_read read);
bool spi_flash_erase_protect_enable(void);
bool spi_flash_erase_protect_disable(void);
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* SPI_FLASH_H */

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/*
* ESPRESSIF MIT License
*
* Copyright (c) 2016 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
*
* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
* it is free of charge, to any person obtaining a copy of this software and associated
* documentation files (the "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
* to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef USER_INTERFACE_H
#define USER_INTERFACE_H
#ifndef DOXYGEN
#include "os_type.h"
#ifdef LWIP_OPEN_SRC
#include "lwip/ip_addr.h"
#else
#include "ip_addr.h"
#endif
#include "queue.h"
#include "user_config.h"
#include "spi_flash.h"
#include "gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifndef MAC2STR
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
#endif
enum rst_reason {
REASON_DEFAULT_RST = 0,
REASON_WDT_RST = 1,
REASON_EXCEPTION_RST = 2,
REASON_SOFT_WDT_RST = 3,
REASON_SOFT_RESTART = 4,
REASON_DEEP_SLEEP_AWAKE = 5,
REASON_EXT_SYS_RST = 6
};
struct rst_info{
uint32 reason;
uint32 exccause;
uint32 epc1;
uint32 epc2;
uint32 epc3;
uint32 excvaddr;
uint32 depc;
};
struct rst_info* system_get_rst_info(void);
#define UPGRADE_FW_BIN1 0x00
#define UPGRADE_FW_BIN2 0x01
void system_restore(void);
void system_restart(void);
bool system_deep_sleep_set_option(uint8 option);
bool system_deep_sleep(uint64 time_in_us);
bool system_deep_sleep_instant(uint64 time_in_us);
uint8 system_upgrade_userbin_check(void);
void system_upgrade_reboot(void);
uint8 system_upgrade_flag_check(void);
void system_upgrade_flag_set(uint8 flag);
void system_timer_reinit(void);
uint32 system_get_time(void);
/* user task's prio must be 0/1/2 !!!*/
enum {
USER_TASK_PRIO_0 = 0,
USER_TASK_PRIO_1,
USER_TASK_PRIO_2,
USER_TASK_PRIO_MAX
};
bool system_os_task(os_task_t task, uint8 prio, os_event_t *queue, uint8 qlen);
bool system_os_post(uint8 prio, os_signal_t sig, os_param_t par);
void system_print_meminfo(void);
uint32 system_get_free_heap_size(void);
void system_set_os_print(uint8 onoff);
uint8 system_get_os_print(void);
uint64 system_mktime(uint32 year, uint32 mon, uint32 day, uint32 hour, uint32 min, uint32 sec);
uint32 system_get_chip_id(void);
typedef void (* init_done_cb_t)(void);
void system_init_done_cb(init_done_cb_t cb);
uint32 system_rtc_clock_cali_proc(void);
uint32 system_get_rtc_time(void);
bool system_rtc_mem_read(uint8 src_addr, void *des_addr, uint16 load_size);
bool system_rtc_mem_write(uint8 des_addr, const void *src_addr, uint16 save_size);
void system_uart_swap(void);
void system_uart_de_swap(void);
uint16 system_adc_read(void);
void system_adc_read_fast(uint16 *adc_addr, uint16 adc_num, uint8 adc_clk_div);
uint16 system_get_vdd33(void);
const char *system_get_sdk_version(void);
#define SYS_BOOT_ENHANCE_MODE 0
#define SYS_BOOT_NORMAL_MODE 1
#define SYS_BOOT_NORMAL_BIN 0
#define SYS_BOOT_TEST_BIN 1
uint8 system_get_boot_version(void);
uint32 system_get_userbin_addr(void);
uint8 system_get_boot_mode(void);
bool system_restart_enhance(uint8 bin_type, uint32 bin_addr);
#define SYS_CPU_80MHZ 80
#define SYS_CPU_160MHZ 160
bool system_update_cpu_freq(uint8 freq);
uint8 system_get_cpu_freq(void);
enum flash_size_map {
FLASH_SIZE_4M_MAP_256_256 = 0, /**< Flash size : 4Mbits. Map : 256KBytes + 256KBytes */
FLASH_SIZE_2M, /**< Flash size : 2Mbits. Map : 256KBytes */
FLASH_SIZE_8M_MAP_512_512, /**< Flash size : 8Mbits. Map : 512KBytes + 512KBytes */
FLASH_SIZE_16M_MAP_512_512, /**< Flash size : 16Mbits. Map : 512KBytes + 512KBytes */
FLASH_SIZE_32M_MAP_512_512, /**< Flash size : 32Mbits. Map : 512KBytes + 512KBytes */
FLASH_SIZE_16M_MAP_1024_1024, /**< Flash size : 16Mbits. Map : 1024KBytes + 1024KBytes */
FLASH_SIZE_32M_MAP_1024_1024, /**< Flash size : 32Mbits. Map : 1024KBytes + 1024KBytes */
FLASH_SIZE_32M_MAP_2048_2048, /**< attention: don't support now ,just compatible for nodemcu;
Flash size : 32Mbits. Map : 2048KBytes + 2048KBytes */
FLASH_SIZE_64M_MAP_1024_1024, /**< Flash size : 64Mbits. Map : 1024KBytes + 1024KBytes */
FLASH_SIZE_128M_MAP_1024_1024 /**< Flash size : 128Mbits. Map : 1024KBytes + 1024KBytes */
};
enum flash_size_map system_get_flash_size_map(void);
void system_phy_set_max_tpw(uint8 max_tpw);
void system_phy_set_tpw_via_vdd33(uint16 vdd33);
void system_phy_set_rfoption(uint8 option);
void system_phy_set_powerup_option(uint8 option);
void system_phy_freq_trace_enable(bool enable);
bool system_param_save_with_protect(uint16 start_sec, void *param, uint16 len);
bool system_param_load(uint16 start_sec, uint16 offset, void *param, uint16 len);
void system_soft_wdt_stop(void);
void system_soft_wdt_restart(void);
void system_soft_wdt_feed(void);
void system_show_malloc(void);
#define NULL_MODE 0x00
#define STATION_MODE 0x01
#define SOFTAP_MODE 0x02
#define STATIONAP_MODE 0x03
typedef enum _auth_mode {
AUTH_OPEN = 0,
AUTH_WEP,
AUTH_WPA_PSK,
AUTH_WPA2_PSK,
AUTH_WPA_WPA2_PSK,
AUTH_MAX
} AUTH_MODE;
uint8 wifi_get_opmode(void);
uint8 wifi_get_opmode_default(void);
bool wifi_set_opmode(uint8 opmode);
bool wifi_set_opmode_current(uint8 opmode);
uint8 wifi_get_broadcast_if(void);
bool wifi_set_broadcast_if(uint8 interface);
struct bss_info {
STAILQ_ENTRY(bss_info) next;
uint8 bssid[6];
uint8 ssid[32];
uint8 ssid_len;
uint8 channel;
sint8 rssi;
AUTH_MODE authmode;
uint8 is_hidden;
sint16 freq_offset;
sint16 freqcal_val;
uint8 *esp_mesh_ie;
uint8 simple_pair;
};
typedef struct _scaninfo {
STAILQ_HEAD(, bss_info) *pbss;
struct espconn *pespconn;
uint8 totalpage;
uint8 pagenum;
uint8 page_sn;
uint8 data_cnt;
} scaninfo;
typedef void (* scan_done_cb_t)(void *arg, STATUS status);
struct station_config {
uint8 ssid[32];
uint8 password[64];
uint8 bssid_set; // Note: If bssid_set is 1, station will just connect to the router
// with both ssid[] and bssid[] matched. Please check about this.
uint8 bssid[6];
};
bool wifi_station_get_config(struct station_config *config);
bool wifi_station_get_config_default(struct station_config *config);
bool wifi_station_set_config(struct station_config *config);
bool wifi_station_set_config_current(struct station_config *config);
bool wifi_station_connect(void);
bool wifi_station_disconnect(void);
sint8 wifi_station_get_rssi(void);
struct scan_config {
uint8 *ssid; // Note: ssid == NULL, don't filter ssid.
uint8 *bssid; // Note: bssid == NULL, don't filter bssid.
uint8 channel; // Note: channel == 0, scan all channels, otherwise scan set channel.
uint8 show_hidden; // Note: show_hidden == 1, can get hidden ssid routers' info.
};
bool wifi_station_scan(struct scan_config *config, scan_done_cb_t cb);
uint8 wifi_station_get_auto_connect(void);
bool wifi_station_set_auto_connect(uint8 set);
bool wifi_station_set_reconnect_policy(bool set);
enum {
STATION_IDLE = 0,
STATION_CONNECTING,
STATION_WRONG_PASSWORD,
STATION_NO_AP_FOUND,
STATION_CONNECT_FAIL,
STATION_GOT_IP
};
enum dhcp_status {
DHCP_STOPPED,
DHCP_STARTED
};
uint8 wifi_station_get_connect_status(void);
uint8 wifi_station_get_current_ap_id(void);
bool wifi_station_ap_change(uint8 current_ap_id);
bool wifi_station_ap_number_set(uint8 ap_number);
uint8 wifi_station_get_ap_info(struct station_config config[]);
bool wifi_station_dhcpc_start(void);
bool wifi_station_dhcpc_stop(void);
enum dhcp_status wifi_station_dhcpc_status(void);
bool wifi_station_dhcpc_set_maxtry(uint8 num);
char* wifi_station_get_hostname(void);
bool wifi_station_set_hostname(char *name);
int wifi_station_set_cert_key(uint8 *client_cert, int client_cert_len,
uint8 *private_key, int private_key_len,
uint8 *private_key_passwd, int private_key_passwd_len);
void wifi_station_clear_cert_key(void);
int wifi_station_set_username(uint8 *username, int len);
void wifi_station_clear_username(void);
struct softap_config {
uint8 ssid[32];
uint8 password[64];
uint8 ssid_len; // Note: Recommend to set it according to your ssid
uint8 channel; // Note: support 1 ~ 13
AUTH_MODE authmode; // Note: Don't support AUTH_WEP in softAP mode.
uint8 ssid_hidden; // Note: default 0
uint8 max_connection; // Note: default 4, max 4
uint16 beacon_interval; // Note: support 100 ~ 60000 ms, default 100
};
bool wifi_softap_get_config(struct softap_config *config);
bool wifi_softap_get_config_default(struct softap_config *config);
bool wifi_softap_set_config(struct softap_config *config);
bool wifi_softap_set_config_current(struct softap_config *config);
struct station_info {
STAILQ_ENTRY(station_info) next;
uint8 bssid[6];
struct ip_addr ip;
};
struct dhcps_lease {
bool enable;
struct ip_addr start_ip;
struct ip_addr end_ip;
};
enum dhcps_offer_option{
OFFER_START = 0x00,
OFFER_ROUTER = 0x01,
OFFER_END
};
uint8 wifi_softap_get_station_num(void);
struct station_info * wifi_softap_get_station_info(void);
void wifi_softap_free_station_info(void);
bool wifi_softap_dhcps_start(void);
bool wifi_softap_dhcps_stop(void);
bool wifi_softap_set_dhcps_lease(struct dhcps_lease *please);
bool wifi_softap_get_dhcps_lease(struct dhcps_lease *please);
uint32 wifi_softap_get_dhcps_lease_time(void);
bool wifi_softap_set_dhcps_lease_time(uint32 minute);
bool wifi_softap_reset_dhcps_lease_time(void);
enum dhcp_status wifi_softap_dhcps_status(void);
bool wifi_softap_set_dhcps_offer_option(uint8 level, void* optarg);
#define STATION_IF 0x00
#define SOFTAP_IF 0x01
bool wifi_get_ip_info(uint8 if_index, struct ip_info *info);
bool wifi_set_ip_info(uint8 if_index, struct ip_info *info);
bool wifi_get_macaddr(uint8 if_index, uint8 *macaddr);
bool wifi_set_macaddr(uint8 if_index, uint8 *macaddr);
uint8 wifi_get_channel(void);
bool wifi_set_channel(uint8 channel);
void wifi_status_led_install(uint8 gpio_id, uint32 gpio_name, uint8 gpio_func);
void wifi_status_led_uninstall(void);
/** Get the absolute difference between 2 u32_t values (correcting overflows)
* 'a' is expected to be 'higher' (without overflow) than 'b'. */
#define ESP_U32_DIFF(a, b) (((a) >= (b)) ? ((a) - (b)) : (((a) + ((b) ^ 0xFFFFFFFF) + 1)))
void wifi_promiscuous_enable(uint8 promiscuous);
typedef void (* wifi_promiscuous_cb_t)(uint8 *buf, uint16 len);
void wifi_set_promiscuous_rx_cb(wifi_promiscuous_cb_t cb);
void wifi_promiscuous_set_mac(const uint8_t *address);
enum phy_mode {
PHY_MODE_11B = 1,
PHY_MODE_11G = 2,
PHY_MODE_11N = 3
};
enum phy_mode wifi_get_phy_mode(void);
bool wifi_set_phy_mode(enum phy_mode mode);
enum sleep_type {
NONE_SLEEP_T = 0,
LIGHT_SLEEP_T,
MODEM_SLEEP_T
};
bool wifi_set_sleep_type(enum sleep_type type);
enum sleep_type wifi_get_sleep_type(void);
void wifi_fpm_open(void);
void wifi_fpm_close(void);
void wifi_fpm_do_wakeup(void);
sint8 wifi_fpm_do_sleep(uint32 sleep_time_in_us);
void wifi_fpm_set_sleep_type(enum sleep_type type);
enum sleep_type wifi_fpm_get_sleep_type(void);
typedef void (*fpm_wakeup_cb)(void);
void wifi_fpm_set_wakeup_cb(fpm_wakeup_cb cb);
void wifi_fpm_auto_sleep_set_in_null_mode(uint8 req);
enum {
EVENT_STAMODE_CONNECTED = 0,
EVENT_STAMODE_DISCONNECTED,
EVENT_STAMODE_AUTHMODE_CHANGE,
EVENT_STAMODE_GOT_IP,
EVENT_STAMODE_DHCP_TIMEOUT,
EVENT_SOFTAPMODE_STACONNECTED,
EVENT_SOFTAPMODE_STADISCONNECTED,
EVENT_SOFTAPMODE_PROBEREQRECVED,
EVENT_OPMODE_CHANGED,
EVENT_MAX
};
enum {
REASON_UNSPECIFIED = 1,
REASON_AUTH_EXPIRE = 2,
REASON_AUTH_LEAVE = 3,
REASON_ASSOC_EXPIRE = 4,
REASON_ASSOC_TOOMANY = 5,
REASON_NOT_AUTHED = 6,
REASON_NOT_ASSOCED = 7,
REASON_ASSOC_LEAVE = 8,
REASON_ASSOC_NOT_AUTHED = 9,
REASON_DISASSOC_PWRCAP_BAD = 10, /* 11h */
REASON_DISASSOC_SUPCHAN_BAD = 11, /* 11h */
REASON_IE_INVALID = 13, /* 11i */
REASON_MIC_FAILURE = 14, /* 11i */
REASON_4WAY_HANDSHAKE_TIMEOUT = 15, /* 11i */
REASON_GROUP_KEY_UPDATE_TIMEOUT = 16, /* 11i */
REASON_IE_IN_4WAY_DIFFERS = 17, /* 11i */
REASON_GROUP_CIPHER_INVALID = 18, /* 11i */
REASON_PAIRWISE_CIPHER_INVALID = 19, /* 11i */
REASON_AKMP_INVALID = 20, /* 11i */
REASON_UNSUPP_RSN_IE_VERSION = 21, /* 11i */
REASON_INVALID_RSN_IE_CAP = 22, /* 11i */
REASON_802_1X_AUTH_FAILED = 23, /* 11i */
REASON_CIPHER_SUITE_REJECTED = 24, /* 11i */
REASON_BEACON_TIMEOUT = 200,
REASON_NO_AP_FOUND = 201,
REASON_AUTH_FAIL = 202,
REASON_ASSOC_FAIL = 203,
REASON_HANDSHAKE_TIMEOUT = 204,
};
typedef struct {
uint8 ssid[32];
uint8 ssid_len;
uint8 bssid[6];
uint8 channel;
} Event_StaMode_Connected_t;
typedef struct {
uint8 ssid[32];
uint8 ssid_len;
uint8 bssid[6];
uint8 reason;
} Event_StaMode_Disconnected_t;
typedef struct {
uint8 old_mode;
uint8 new_mode;
} Event_StaMode_AuthMode_Change_t;
typedef struct {
struct ip_addr ip;
struct ip_addr mask;
struct ip_addr gw;
} Event_StaMode_Got_IP_t;
typedef struct {
uint8 mac[6];
uint8 aid;
} Event_SoftAPMode_StaConnected_t;
typedef struct {
uint8 mac[6];
uint8 aid;
} Event_SoftAPMode_StaDisconnected_t;
typedef struct {
int rssi;
uint8 mac[6];
} Event_SoftAPMode_ProbeReqRecved_t;
typedef struct {
uint8 old_opmode;
uint8 new_opmode;
} Event_OpMode_Change_t;
typedef union {
Event_StaMode_Connected_t connected;
Event_StaMode_Disconnected_t disconnected;
Event_StaMode_AuthMode_Change_t auth_change;
Event_StaMode_Got_IP_t got_ip;
Event_SoftAPMode_StaConnected_t sta_connected;
Event_SoftAPMode_StaDisconnected_t sta_disconnected;
Event_SoftAPMode_ProbeReqRecved_t ap_probereqrecved;
Event_OpMode_Change_t opmode_changed;
} Event_Info_u;
typedef struct _esp_event {
uint32 event;
Event_Info_u event_info;
} System_Event_t;
typedef void (* wifi_event_handler_cb_t)(System_Event_t *event);
void wifi_set_event_handler_cb(wifi_event_handler_cb_t cb);
typedef enum wps_type {
WPS_TYPE_DISABLE = 0,
WPS_TYPE_PBC,
WPS_TYPE_PIN,
WPS_TYPE_DISPLAY,
WPS_TYPE_MAX,
} WPS_TYPE_t;
enum wps_cb_status {
WPS_CB_ST_SUCCESS = 0,
WPS_CB_ST_FAILED,
WPS_CB_ST_TIMEOUT,
WPS_CB_ST_WEP,
};
bool wifi_wps_enable(WPS_TYPE_t wps_type);
bool wifi_wps_disable(void);
bool wifi_wps_start(void);
typedef void (*wps_st_cb_t)(int status);
bool wifi_set_wps_cb(wps_st_cb_t cb);
typedef void (*freedom_outside_cb_t)(uint8 status);
int wifi_register_send_pkt_freedom_cb(freedom_outside_cb_t cb);
void wifi_unregister_send_pkt_freedom_cb(void);
int wifi_send_pkt_freedom(uint8 *buf, int len, bool sys_seq);
int wifi_rfid_locp_recv_open(void);
void wifi_rfid_locp_recv_close(void);
typedef void (*rfid_locp_cb_t)(uint8 *frm, int len, int rssi);
int wifi_register_rfid_locp_recv_cb(rfid_locp_cb_t cb);
void wifi_unregister_rfid_locp_recv_cb(void);
enum FIXED_RATE {
PHY_RATE_48 = 0x8,
PHY_RATE_24 = 0x9,
PHY_RATE_12 = 0xA,
PHY_RATE_6 = 0xB,
PHY_RATE_54 = 0xC,
PHY_RATE_36 = 0xD,
PHY_RATE_18 = 0xE,
PHY_RATE_9 = 0xF,
};
#define FIXED_RATE_MASK_NONE 0x00
#define FIXED_RATE_MASK_STA 0x01
#define FIXED_RATE_MASK_AP 0x02
#define FIXED_RATE_MASK_ALL 0x03
int wifi_set_user_fixed_rate(uint8 enable_mask, uint8 rate);
int wifi_get_user_fixed_rate(uint8 *enable_mask, uint8 *rate);
enum support_rate {
RATE_11B5M = 0,
RATE_11B11M = 1,
RATE_11B1M = 2,
RATE_11B2M = 3,
RATE_11G6M = 4,
RATE_11G12M = 5,
RATE_11G24M = 6,
RATE_11G48M = 7,
RATE_11G54M = 8,
RATE_11G9M = 9,
RATE_11G18M = 10,
RATE_11G36M = 11,
};
int wifi_set_user_sup_rate(uint8 min, uint8 max);
enum RATE_11B_ID {
RATE_11B_B11M = 0,
RATE_11B_B5M = 1,
RATE_11B_B2M = 2,
RATE_11B_B1M = 3,
};
enum RATE_11G_ID {
RATE_11G_G54M = 0,
RATE_11G_G48M = 1,
RATE_11G_G36M = 2,
RATE_11G_G24M = 3,
RATE_11G_G18M = 4,
RATE_11G_G12M = 5,
RATE_11G_G9M = 6,
RATE_11G_G6M = 7,
RATE_11G_B5M = 8,
RATE_11G_B2M = 9,
RATE_11G_B1M = 10
};
enum RATE_11N_ID {
RATE_11N_MCS7S = 0,
RATE_11N_MCS7 = 1,
RATE_11N_MCS6 = 2,
RATE_11N_MCS5 = 3,
RATE_11N_MCS4 = 4,
RATE_11N_MCS3 = 5,
RATE_11N_MCS2 = 6,
RATE_11N_MCS1 = 7,
RATE_11N_MCS0 = 8,
RATE_11N_B5M = 9,
RATE_11N_B2M = 10,
RATE_11N_B1M = 11
};
#define RC_LIMIT_11B 0
#define RC_LIMIT_11G 1
#define RC_LIMIT_11N 2
#define RC_LIMIT_P2P_11G 3
#define RC_LIMIT_P2P_11N 4
#define RC_LIMIT_NUM 5
#define LIMIT_RATE_MASK_NONE 0x00
#define LIMIT_RATE_MASK_STA 0x01
#define LIMIT_RATE_MASK_AP 0x02
#define LIMIT_RATE_MASK_ALL 0x03
bool wifi_set_user_rate_limit(uint8 mode, uint8 ifidx, uint8 max, uint8 min);
uint8 wifi_get_user_limit_rate_mask(void);
bool wifi_set_user_limit_rate_mask(uint8 enable_mask);
enum {
USER_IE_BEACON = 0,
USER_IE_PROBE_REQ,
USER_IE_PROBE_RESP,
USER_IE_ASSOC_REQ,
USER_IE_ASSOC_RESP,
USER_IE_MAX
};
typedef void (*user_ie_manufacturer_recv_cb_t)(uint8 type, const uint8 sa[6], const uint8 m_oui[3], uint8 *ie, uint8 ie_len, int rssi);
bool wifi_set_user_ie(bool enable, uint8 *m_oui, uint8 type, uint8 *user_ie, uint8 len);
int wifi_register_user_ie_manufacturer_recv_cb(user_ie_manufacturer_recv_cb_t cb);
void wifi_unregister_user_ie_manufacturer_recv_cb(void);
void wifi_enable_gpio_wakeup(uint32 i, GPIO_INT_TYPE intr_status);
void wifi_disable_gpio_wakeup(void);
void uart_div_modify(uint8 uart_no, uint32 DivLatchValue);
#ifdef __cplusplus
}
#endif
#endif // DOXYGEN
#endif /* USER_INTERFACE_H */