From 49c8c419bf636cca7b6f4926d0c32df2246a6b2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?K=C3=A9vin=20Roussel?= Date: Tue, 1 Oct 2013 15:21:54 +0200 Subject: [PATCH] Updated the MSP430 hwtimer implementation, to cope with the lack of consistency of of TI with the TimerX register names. --- cpu/cc430/hwtimer_cc430.c | 6 ++-- cpu/msp430-common/hwtimer_cpu.c | 49 +++++++++++++++++++++------------ cpu/msp430x16x/hwtimer_msp430.c | 20 +++++++------- 3 files changed, 44 insertions(+), 31 deletions(-) diff --git a/cpu/cc430/hwtimer_cc430.c b/cpu/cc430/hwtimer_cc430.c index ba2cf41b07..8a42180c21 100644 --- a/cpu/cc430/hwtimer_cc430.c +++ b/cpu/cc430/hwtimer_cc430.c @@ -10,7 +10,7 @@ static uint32_t ticks = 0; extern void (*int_handler)(int); -extern void TA0_unset(short timer); +extern void timer_unset(short timer); void timerA_init(void) { @@ -34,7 +34,7 @@ interrupt(TIMER0_A0_VECTOR) __attribute__((naked)) timer0_a0_isr(void) { __enter_isr(); - TA0_unset(0); + timer_unset(0); int_handler(0); __exit_isr(); } @@ -51,7 +51,7 @@ interrupt(TIMER0_A1_VECTOR) __attribute__((naked)) timer0_a1_5_isr(void) } else { timer = (taiv / 2); - TA0_unset(timer); + timer_unset(timer); int_handler(timer); } diff --git a/cpu/msp430-common/hwtimer_cpu.c b/cpu/msp430-common/hwtimer_cpu.c index 4b748b9753..b0d7ba9d7b 100644 --- a/cpu/msp430-common/hwtimer_cpu.c +++ b/cpu/msp430-common/hwtimer_cpu.c @@ -25,43 +25,56 @@ extern void timerA_init(void); uint16_t overflow_interrupt[ARCH_MAXTIMERS+1]; uint16_t timer_round; -static void TA0_disable_interrupt(short timer) +#ifdef CC430 + /* CC430 have "TimerA0", "TimerA1" and so on... */ + #define CNT_CTRL_BASE_REG (TA0CCTL0) + #define CNT_COMP_BASE_REG (TA0CCR0) + #define TIMER_VAL_REG (TA0R) +#else + /* ... while other MSP430 MCUs have "TimerA", "TimerB". + Cheers for TI and its consistency! */ + #define CNT_CTRL_BASE_REG (TACCTL0) + #define CNT_COMP_BASE_REG (TACCR0) + #define TIMER_VAL_REG (TAR) +#endif + +static void timer_disable_interrupt(short timer) { - volatile unsigned int *ptr = &TA0CCTL0 + (timer); + volatile unsigned int *ptr = &CNT_CTRL_BASE_REG + (timer); *ptr &= ~(CCIFG); *ptr &= ~(CCIE); } -static void TA0_enable_interrupt(short timer) +static void timer_enable_interrupt(short timer) { - volatile unsigned int *ptr = &TA0CCTL0 + (timer); + volatile unsigned int *ptr = &CNT_CTRL_BASE_REG + (timer); *ptr |= CCIE; *ptr &= ~(CCIFG); } -static void TA0_set_nostart(unsigned long value, short timer) +static void timer_set_nostart(unsigned long value, short timer) { - volatile unsigned int *ptr = &TA0CCR0 + (timer); + volatile unsigned int *ptr = &CNT_COMP_BASE_REG + (timer); *ptr = value; } -static void TA0_set(unsigned long value, short timer) +static void timer_set(unsigned long value, short timer) { DEBUG("Setting timer %u to %lu\n", timer, value); - TA0_set_nostart(value, timer); - TA0_enable_interrupt(timer); + timer_set_nostart(value, timer); + timer_enable_interrupt(timer); } -void TA0_unset(short timer) +void timer_unset(short timer) { - volatile unsigned int *ptr = &TA0CCR0 + (timer); - TA0_disable_interrupt(timer); + volatile unsigned int *ptr = &CNT_COMP_BASE_REG + (timer); + timer_disable_interrupt(timer); *ptr = 0; } unsigned long hwtimer_arch_now() { - return ((uint32_t)timer_round << 16)+TA0R; + return ((uint32_t)timer_round << 16)+TIMER_VAL_REG; } void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) @@ -69,20 +82,20 @@ void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) (void) fcpu; timerA_init(); int_handler = handler; - TA0_enable_interrupt(0); + timer_enable_interrupt(0); } void hwtimer_arch_enable_interrupt(void) { for (int i = 0; i < ARCH_MAXTIMERS; i++) { - TA0_enable_interrupt(i); + timer_enable_interrupt(i); } } void hwtimer_arch_disable_interrupt(void) { for (int i = 0; i < ARCH_MAXTIMERS; i++) { - TA0_disable_interrupt(i); + timer_disable_interrupt(i); } } @@ -96,10 +109,10 @@ void hwtimer_arch_set_absolute(unsigned long value, short timer) { uint16_t small_value = value % 0xFFFF; overflow_interrupt[timer] = (uint16_t)(value >> 16); - TA0_set(small_value,timer); + timer_set(small_value,timer); } void hwtimer_arch_unset(short timer) { - TA0_unset(timer); + timer_unset(timer); } diff --git a/cpu/msp430x16x/hwtimer_msp430.c b/cpu/msp430x16x/hwtimer_msp430.c index 3a4a3a91ce..b431397d38 100644 --- a/cpu/msp430x16x/hwtimer_msp430.c +++ b/cpu/msp430x16x/hwtimer_msp430.c @@ -6,7 +6,7 @@ static uint32_t ticks = 0; extern void (*int_handler)(int); -extern void TA0_unset(short timer); +extern void timer_unset(short timer); extern uint16_t overflow_interrupt[ARCH_MAXTIMERS+1]; extern uint16_t timer_round; @@ -16,19 +16,19 @@ void timerA_init(void) volatile unsigned int *ctl; ticks = 0; // Set tick counter value to 0 timer_round = 0; // Set to round 0 - TA0CTL = TASSEL_1 + TACLR; // Clear the timer counter, set ACLK - TA0CTL &= ~TAIFG; // Clear the IFG - TA0CTL &= ~TAIE; // Clear the IFG + TACTL = TASSEL_1 + TACLR; // Clear the timer counter, set ACLK + TACTL &= ~TAIFG; // Clear the IFG + TACTL &= ~TAIE; // Clear the IFG for (int i = 0; i < ARCH_MAXTIMERS; i++) { - ccr = &TA0CCR0 + (i); - ctl = &TA0CCTL0 + (i); + ccr = &TACCR0 + (i); + ctl = &TACCTL0 + (i); *ccr = 0; *ctl &= ~(CCIFG); *ctl &= ~(CCIE); } - TA0CTL |= MC_2; + TACTL |= MC_2; } interrupt(TIMERA0_VECTOR) __attribute__((naked)) timer_isr_ccr0(void) @@ -43,15 +43,15 @@ interrupt(TIMERA1_VECTOR) __attribute__((naked)) timer_isr(void) { __enter_isr(); - short taiv = TA0IV; + short taiv = TAIV; - if (taiv & TAIFG) { + if (taiv & TAIV_TAIFG) { } else { short timer = (taiv/2); if(overflow_interrupt[timer] == timer_round) { - TA0_unset(timer); + timer_unset(timer); int_handler(timer); } }