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Merge pull request #15349 from kaspar030/work_around_sam3_timer_issue

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cpu/sam3/periph/timer: fix trigger of cleared timer
This commit is contained in:
Koen Zandberg 2020-10-30 15:15:18 +01:00 committed by GitHub
commit 4c289f49b0
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2 changed files with 15 additions and 2 deletions
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9
cpu/sam3/include/periph_cpu.h
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@ -66,9 +66,14 @@ typedef uint32_t gpio_t;
#define TIMER_MAX_VAL (0xffffffff) #define TIMER_MAX_VAL (0xffffffff)
/** /**
* @brief We use 3 channels for each defined timer * @brief We use one channel for each defined timer
*
* While the peripheral provides three channels, the current interrupt
* flag handling leads to a race condition where calling timer_clear() on one
* channel can disable a pending flag for other channels.
* Until resolved, limit the peripheral to only one channel.
*/ */
#define TIMER_CHANNEL_NUMOF (3) #define TIMER_CHANNEL_NUMOF (1)
/** /**
* @brief The RTT width is fixed to 32-bit * @brief The RTT width is fixed to 32-bit

8
cpu/sam3/periph/timer.c
View File

@ -128,6 +128,14 @@ int timer_set_absolute(tim_t tim, int channel, unsigned int value)
return -1; return -1;
} }
(&dev(tim)->TC_CHANNEL[0].TC_RA)[channel] = value; (&dev(tim)->TC_CHANNEL[0].TC_RA)[channel] = value;
/* read TC status register to clear any possibly pending
* ISR flag (that has not been served yet).
* timer_clear() disables the interrupt, but does not clear the flags.
* if we don't clear them here, re-enabling the interrupt below
* can trigger for the previously disabled timer. */
(void)dev(tim)->TC_CHANNEL[0].TC_SR;
dev(tim)->TC_CHANNEL[0].TC_IER = (TC_IER_CPAS << channel); dev(tim)->TC_CHANNEL[0].TC_IER = (TC_IER_CPAS << channel);
return 0; return 0;