Merge pull request #14131 from aabadie/pr/cpu/stmclk_cleanup
cpu/stm32: move stmclk in its own module, remove useless ifdefs
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4f295a439b
@ -1,5 +1,5 @@
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MODULE = cpu
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DIRS = $(RIOTCPU)/cortexm_common periph vectors
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DIRS = $(RIOTCPU)/cortexm_common periph stmclk vectors
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include $(RIOTBASE)/Makefile.base
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@ -1,8 +1,8 @@
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# All stm32 families provide pm support
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USEMODULE += pm_layered
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# include stm32 common periph drivers
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USEMODULE += periph stm32_vectors
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# include stm32 common periph drivers, clock configurations and vectors
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USEMODULE += periph stm32_clk stm32_vectors
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ifneq (,$(filter periph_usbdev,$(FEATURES_USED)))
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USEMODULE += xtimer
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14
cpu/stm32/stmclk/Makefile
Normal file
14
cpu/stm32/stmclk/Makefile
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@ -0,0 +1,14 @@
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MODULE = stm32_clk
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SRC = stmclk_common.c
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_CPU_FAM_SHORT = $(subst stm32,,$(CPU_FAM))
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ifneq (,$(filter f%,$(_CPU_FAM_SHORT)))
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SRC += stmclk_fx.c
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else ifneq (,$(filter $(_CPU_FAM_SHORT),l0 l1))
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SRC += stmclk_l0l1.c
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else ifneq (,$(filter $(_CPU_FAM_SHORT),l4 wb))
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SRC += stmclk_l4wb.c
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endif
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include $(RIOTBASE)/Makefile.base
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@ -12,17 +12,13 @@
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration
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* @brief Implementation of STM32 clock configuration for F0/F1/F2/F3/F4/F7 families
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
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defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
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defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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@ -252,8 +248,3 @@ void stmclk_init_sysclk(void)
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irq_restore(is);
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}
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#else
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typedef int dont_be_pedantic;
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#endif /* defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) ||
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* defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) ||
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* defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) */
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@ -13,7 +13,7 @@
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration
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* @brief Implementation of STM32 clock configuration for L0 and L1 families
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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@ -26,8 +26,6 @@
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#include "periph_conf.h"
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#include "periph/init.h"
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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/* Check the source to be used for the PLL */
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#if defined(CLOCK_HSI) && defined(CLOCK_HSE)
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#error "Only provide one of two CLOCK_HSI/CLOCK_HSE"
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@ -115,5 +113,3 @@ void stmclk_init_sysclk(void)
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
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}
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#endif /* defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) */
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@ -13,7 +13,7 @@
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration
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* @brief Implementation of STM32 clock configuration for L4 and WB families
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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@ -27,8 +27,6 @@
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#include "stmclk.h"
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#include "periph_conf.h"
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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@ -200,4 +198,3 @@ void stmclk_init_sysclk(void)
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#endif /* CLOCK_LSE */
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#endif /* MODULE_PERIPH_RTT */
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}
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#endif
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