diff --git a/cpu/stm32/include/vendor/stm32f722xx.h b/cpu/stm32/include/vendor/stm32f722xx.h
index bdea2fb88e..4d226e5e6a 100644
--- a/cpu/stm32/include/vendor/stm32f722xx.h
+++ b/cpu/stm32/include/vendor/stm32f722xx.h
@@ -2,41 +2,23 @@
******************************************************************************
* @file stm32f722xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral’s registers hardware
+ * - Macros to access peripheral�s registers hardware
*
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2016 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -179,6 +161,7 @@ typedef enum
#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
+
#include
/** @addtogroup Peripheral_registers_structures
@@ -825,12 +808,11 @@ typedef struct
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
uint32_t Reserved6; /*!< Reserved 050h */
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
- __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
+ uint32_t Reserved7; /*!< Reserved 058h */
__IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
- __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
- uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
+ uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
- __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */
} USB_OTG_GlobalTypeDef;
@@ -930,148 +912,148 @@ typedef struct
/** @addtogroup Peripheral_memory_map
* @{
*/
-#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
-#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over ITCM */
-#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over AXI */
-#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */
-#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
-#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
-#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
-#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
-#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
-#define SRAM1_BASE 0x20010000U /*!< Base address of : 176KB RAM1 accessible over AXI/AHB */
-#define SRAM2_BASE 0x2003C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
-#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
-#define FLASH_OTP_BASE 0x1FF07800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
-#define FLASH_OTP_END 0x1FF07A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
+#define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over ITCM */
+#define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over AXI */
+#define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 64KB system data RAM accessible over DTCM */
+#define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */
+#define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */
+#define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */
+#define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */
+#define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */
+#define SRAM1_BASE 0x20010000UL /*!< Base address of : 176KB RAM1 accessible over AXI/AHB */
+#define SRAM2_BASE 0x2003C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
+#define FLASH_END 0x0807FFFFUL /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FF07800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FF07A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
/* Legacy define */
#define FLASH_BASE FLASHAXI_BASE
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
/*!< APB1 peripherals */
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
-#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
/*!< APB2 peripherals */
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
-#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
-#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
-#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
-#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
-#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
-#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
+#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
/*!< AHB1 peripherals */
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
-#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
-#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
+#define UID_BASE 0x1FF07A10UL /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FF07A22UL /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FF07BF0UL /*!< Package size register base address */
/* Legacy define */
#define PACKAGESIZE_BASE PACKAGE_BASE
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
/*!< AHB2 peripherals */
-#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
/* Debug MCU registers base address */
-#define DBGMCU_BASE 0xE0042000U
+#define DBGMCU_BASE 0xE0042000UL
/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE 0x40040000U
-#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
+#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
-#define USB_OTG_GLOBAL_BASE 0x000U
-#define USB_OTG_DEVICE_BASE 0x800U
-#define USB_OTG_IN_ENDPOINT_BASE 0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
-#define USB_OTG_EP_REG_SIZE 0x20U
-#define USB_OTG_HOST_BASE 0x400U
-#define USB_OTG_HOST_PORT_BASE 0x440U
-#define USB_OTG_HOST_CHANNEL_BASE 0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
-#define USB_OTG_PCGCCTL_BASE 0xE00U
-#define USB_OTG_FIFO_BASE 0x1000U
-#define USB_OTG_FIFO_SIZE 0x1000U
+#define USB_OTG_GLOBAL_BASE 0x0000UL
+#define USB_OTG_DEVICE_BASE 0x0800UL
+#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL
+#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL
+#define USB_OTG_EP_REG_SIZE 0x0020UL
+#define USB_OTG_HOST_BASE 0x0400UL
+#define USB_OTG_HOST_PORT_BASE 0x0440UL
+#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL
+#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL
+#define USB_OTG_PCGCCTL_BASE 0x0E00UL
+#define USB_OTG_FIFO_BASE 0x1000UL
+#define USB_OTG_FIFO_SIZE 0x1000UL
/**
* @}
@@ -1194,457 +1176,461 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
+#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!© COPYRIGHT(c) 2016 STMicroelectronics
+ * © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -826,12 +808,11 @@ typedef struct
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
uint32_t Reserved6; /*!< Reserved 050h */
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
- __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
+ uint32_t Reserved7; /*!< Reserved 058h */
__IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
- __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
- uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
+ uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
- __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */
} USB_OTG_GlobalTypeDef;
/**
@@ -945,149 +926,149 @@ typedef struct
/** @addtogroup Peripheral_memory_map
* @{
*/
-#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
-#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over ITCM */
-#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over AXI */
-#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */
-#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
-#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
-#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
-#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
-#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
-#define SRAM1_BASE 0x20010000U /*!< Base address of : 176KB RAM1 accessible over AXI/AHB */
-#define SRAM2_BASE 0x2003C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
-#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
-#define FLASH_OTP_BASE 0x1FF07800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
-#define FLASH_OTP_END 0x1FF07A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
+#define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over ITCM */
+#define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 512 KB) embedded FLASH memory accessible over AXI */
+#define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 64KB system data RAM accessible over DTCM */
+#define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */
+#define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */
+#define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */
+#define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */
+#define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */
+#define SRAM1_BASE 0x20010000UL /*!< Base address of : 176KB RAM1 accessible over AXI/AHB */
+#define SRAM2_BASE 0x2003C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
+#define FLASH_END 0x0807FFFFUL /*!< FLASH end address */
+#define FLASH_OTP_BASE 0x1FF07800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
+#define FLASH_OTP_END 0x1FF07A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
/* Legacy define */
#define FLASH_BASE FLASHAXI_BASE
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
/*!< APB1 peripherals */
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
-#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
-#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
-#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
/*!< APB2 peripherals */
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
-#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
-#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
-#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
-#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
-#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
-#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
-#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
-#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
-#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
+#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
/*!< AHB1 peripherals */
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
-#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
-#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
-#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
-#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
-#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
+#define UID_BASE 0x1FF07A10UL /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE 0x1FF07A22UL /*!< FLASH Size register base address */
+#define PACKAGE_BASE 0x1FF07BF0UL /*!< Package size register base address */
/* Legacy define */
#define PACKAGESIZE_BASE PACKAGE_BASE
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
/*!< AHB2 peripherals */
-#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
/*!< FMC Bankx registers base address */
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
/* Debug MCU registers base address */
-#define DBGMCU_BASE 0xE0042000U
+#define DBGMCU_BASE 0xE0042000UL
/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE 0x40040000U
-#define USB_OTG_FS_PERIPH_BASE 0x50000000U
-#define USB_HS_PHYC_CONTROLLER_BASE 0x40017C00U
+#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
+#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
+#define USB_HS_PHYC_CONTROLLER_BASE 0x40017C00UL
-#define USB_OTG_GLOBAL_BASE 0x000U
-#define USB_OTG_DEVICE_BASE 0x800U
-#define USB_OTG_IN_ENDPOINT_BASE 0x900U
-#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
-#define USB_OTG_EP_REG_SIZE 0x20U
-#define USB_OTG_HOST_BASE 0x400U
-#define USB_OTG_HOST_PORT_BASE 0x440U
-#define USB_OTG_HOST_CHANNEL_BASE 0x500U
-#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
-#define USB_OTG_PCGCCTL_BASE 0xE00U
-#define USB_OTG_FIFO_BASE 0x1000U
-#define USB_OTG_FIFO_SIZE 0x1000U
+#define USB_OTG_GLOBAL_BASE 0x0000UL
+#define USB_OTG_DEVICE_BASE 0x0800UL
+#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL
+#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL
+#define USB_OTG_EP_REG_SIZE 0x0020UL
+#define USB_OTG_HOST_BASE 0x0400UL
+#define USB_OTG_HOST_PORT_BASE 0x0440UL
+#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL
+#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL
+#define USB_OTG_PCGCCTL_BASE 0x0E00UL
+#define USB_OTG_FIFO_BASE 0x1000UL
+#define USB_OTG_FIFO_SIZE 0x1000UL
/**
* @}
@@ -1211,457 +1192,461 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
+#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!