From 4f96cdbfcd6e4c40b80474988bcbc12e8fcab5f6 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Tue, 26 May 2020 09:18:07 +0200 Subject: [PATCH] cpu/stm32: update stm32f334 vendor header --- cpu/stm32/include/vendor/stm32f334x8.h | 18233 ++++++++++++++++------- 1 file changed, 12865 insertions(+), 5368 deletions(-) diff --git a/cpu/stm32/include/vendor/stm32f334x8.h b/cpu/stm32/include/vendor/stm32f334x8.h index eb3de40be0..352f8e0b2e 100644 --- a/cpu/stm32/include/vendor/stm32f334x8.h +++ b/cpu/stm32/include/vendor/stm32f334x8.h @@ -2,9 +2,7 @@ ****************************************************************************** * @file stm32f334x8.h * @author MCD Application Team - * @version V1.1.0 - * @date 12-Sept-2014 - * @brief CMSIS STM32F334x4/STM32F334x6/STM32F334x8 Devices Peripheral Access Layer Header File. + * @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals @@ -14,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -49,8 +31,8 @@ * @{ */ -#ifndef STM32F334x8_H -#define STM32F334x8_H +#ifndef __STM32F334x8_H +#define __STM32F334x8_H #ifdef __cplusplus extern "C" { @@ -63,28 +45,29 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices do not provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices use 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices provide an FPU */ +#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0U /*!< STM32F334x8 devices do not provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32F334x8 devices use 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< STM32F334x8 devices provide an FPU */ /** * @} */ - + /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** - * @brief STM32F334x4/STM32F334x6/STM32F334x8 device Interrupt Number Definition, according to the selected device + * @brief STM32F334x8 devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum { /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ @@ -112,8 +95,8 @@ typedef enum DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ - CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */ - CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */ + CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */ + CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ @@ -130,11 +113,11 @@ typedef enum USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ - TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ + TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/ TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */ - COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */ - COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */ + COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */ + COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */ HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */ HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */ @@ -142,7 +125,7 @@ typedef enum HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */ HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */ HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -274,11 +257,15 @@ typedef struct /** * @brief Analog Comparators */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; typedef struct { - __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ -} COMP_TypeDef; + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; /** * @brief CRC calculation unit @@ -344,8 +331,8 @@ typedef struct typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** @@ -354,20 +341,20 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ + __IO uint32_t IMR; /*!