Merge pull request #14782 from benpicco/cpu/sam0_common-full

cpu/sam0_common: add all parts to Kconfig

cpu/sam0_common/Makefile.features

@@ -1,3 +1,5 @@
+CPU_FAM := $(shell echo $(CPU_MODEL) | cut -c -6)
+
 FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_dma
 FEATURES_PROVIDED += periph_flashpage

cpu/sam0_common/dist/kconfig_gen.sh

@@ -0,0 +1,35 @@
+#!/bin/bash
+#
+# Generate Kconfig file for all parts of a sam0 family
+# based on the available vendor files.
+
+if [ -z "$1" ]
+then
+    echo "usage: $0 <family>"
+    exit 1
+fi
+
+FAM=$1
+FAM_UC=$(echo $FAM | tr a-z A-Z)
+
+VENDOR_FILES=$(dirname $0)/../include/vendor/$FAM/*/$FAM?*.h
+
+{
+echo '## CPU Models'
+for i in $VENDOR_FILES; do
+    MODEL_LC=$(basename $i .h)
+    MODEL_UC=$(echo $MODEL_LC | tr a-z A-Z)
+
+    echo "config CPU_MODEL_$MODEL_UC"
+    echo "    bool"
+    echo "    select CPU_FAM_$FAM_UC"
+    echo ""
+done
+
+echo 'config CPU_MODEL'
+for i in $VENDOR_FILES; do
+    MODEL_LC=$(basename $i .h)
+    MODEL_UC=$(echo $MODEL_LC | tr a-z A-Z)
+    printf '    default "%s" if CPU_MODEL_%s\n' $MODEL_LC $MODEL_UC
+done
+} > Kconfig.$FAM

cpu/sam0_common/include/cpu_conf.h

@@ -78,7 +78,7 @@ extern "C" {
 #define CPU_IRQ_NUMOF                   PERIPH_COUNT_IRQn
 #define CPU_FLASH_BASE                  FLASH_ADDR
 
-#ifdef CPU_SAML1X
+#ifdef CPU_COMMON_SAML1X
 #define CPU_FLASH_RWWEE_BASE            DATAFLASH_ADDR
 #else
 #define CPU_FLASH_RWWEE_BASE            NVMCTRL_RWW_EEPROM_ADDR

cpu/sam0_common/include/periph_cpu_common.h

@@ -623,9 +623,9 @@ static inline uint8_t sercom_id(const void *sercom)
 static inline void sercom_clk_en(void *sercom)
 {
     const uint8_t id = sercom_id(sercom);
-#if defined(CPU_FAM_SAMD21)
+#if defined(CPU_COMMON_SAMD21)
     PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << id);
-#elif defined (CPU_FAM_SAMD5X)
+#elif defined (CPU_COMMON_SAMD5X)
     if (id < 2) {
         MCLK->APBAMASK.reg |= (1 << (id + 12));
     } else if (id < 4) {
@@ -637,11 +637,11 @@ static inline void sercom_clk_en(void *sercom)
     if (id < 5) {
         MCLK->APBCMASK.reg |= (MCLK_APBCMASK_SERCOM0 << id);
     }
-#if defined(CPU_FAM_SAML21)
+#if defined(CPU_COMMON_SAML21)
     else {
         MCLK->APBDMASK.reg |= (MCLK_APBDMASK_SERCOM5);
     }
-#endif /* CPU_FAM_SAML21 */
+#endif /* CPU_COMMON_SAML21 */
 #endif
 }
 
@@ -653,9 +653,9 @@ static inline void sercom_clk_en(void *sercom)
 static inline void sercom_clk_dis(void *sercom)
 {
     const uint8_t id = sercom_id(sercom);
-#if defined(CPU_FAM_SAMD21)
+#if defined(CPU_COMMON_SAMD21)
     PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << id);
-#elif defined (CPU_FAM_SAMD5X)
+#elif defined (CPU_COMMON_SAMD5X)
     if (id < 2) {
         MCLK->APBAMASK.reg &= ~(1 << (id + 12));
     } else if (id < 4) {
@@ -667,15 +667,15 @@ static inline void sercom_clk_dis(void *sercom)
     if (id < 5) {
         MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << id);
     }
-#if defined (CPU_FAM_SAML21)
+#if defined (CPU_COMMON_SAML21)
     else {
         MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_SERCOM5);
     }
-#endif /* CPU_FAM_SAML21 */
+#endif /* CPU_COMMON_SAML21 */
 #endif
 }
 
-#ifdef CPU_FAM_SAMD5X
+#ifdef CPU_COMMON_SAMD5X
 static inline uint8_t _sercom_gclk_id_core(uint8_t sercom_id) {
     if (sercom_id < 2)
         return sercom_id + 7;
@@ -696,21 +696,21 @@ static inline void sercom_set_gen(void *sercom, uint8_t gclk)
 {
     const uint8_t id = sercom_id(sercom);
     sam0_gclk_enable(gclk);
-#if defined(CPU_FAM_SAMD21)
+#if defined(CPU_COMMON_SAMD21)
     GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(gclk) |
                          (SERCOM0_GCLK_ID_CORE + id));
     while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
-#elif defined(CPU_FAM_SAMD5X)
+#elif defined(CPU_COMMON_SAMD5X)
     GCLK->PCHCTRL[_sercom_gclk_id_core(id)].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
 #else
     if (id < 5) {
         GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + id].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
     }
-#if defined(CPU_FAM_SAML21)
+#if defined(CPU_COMMON_SAML21)
     else {
         GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
     }
-#endif /* CPU_FAM_SAML21 */
+#endif /* CPU_COMMON_SAML21 */
 #endif
 }
 
@@ -821,7 +821,7 @@ typedef struct {
 /**
  * @brief Move the DMA descriptors to the LP SRAM. Required on the SAML21
  */
-#if defined(CPU_FAM_SAML21) || defined(DOXYGEN)
+#if defined(CPU_COMMON_SAML21) || defined(DOXYGEN)
 #define DMA_DESCRIPTOR_IN_LPSRAM
 #endif
 

cpu/sam0_common/periph/adc.c

@@ -76,11 +76,13 @@ static inline void _wait_syncbusy(void)
 static void _adc_poweroff(void)
 {
     _wait_syncbusy();
+
     /* Disable */
     ADC_DEV->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
     _wait_syncbusy();
+
     /* Disable bandgap */
-#ifdef CPU_SAMD21
+#ifdef SYSCTRL_VREF_BGOUTEN
     if (ADC_REF_DEFAULT == ADC_REFCTRL_REFSEL_INT1V) {
         SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
     }
@@ -95,12 +97,14 @@ static void _setup_clock(void)
 {
     /* Enable gclk in case we are the only user */
     sam0_gclk_enable(ADC_GCLK_SRC);
-#ifdef CPU_SAMD21
+
+#ifdef PM_APBCMASK_ADC
     /* Power On */
     PM->APBCMASK.reg |= PM_APBCMASK_ADC;
     /* GCLK Setup */
-    GCLK->CLKCTRL.reg = (uint32_t)(GCLK_CLKCTRL_CLKEN
+    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
-            | GCLK_CLKCTRL_GEN(ADC_GCLK_SRC) | (GCLK_CLKCTRL_ID(ADC_GCLK_ID)));
+                      | GCLK_CLKCTRL_GEN(ADC_GCLK_SRC)
+                      | GCLK_CLKCTRL_ID(ADC_GCLK_ID);
     /* Configure prescaler */
     ADC_DEV->CTRLB.reg = ADC_PRESCALER;
 #else
@@ -143,7 +147,7 @@ static void _setup_clock(void)
 
 static void _setup_calibration(void)
 {
-#ifdef CPU_SAMD21
+#ifdef ADC_CALIB_BIAS_CAL
     /* Load the fixed device calibration constants */
     ADC_DEV->CALIB.reg =
         ADC_CALIB_BIAS_CAL((*(uint32_t*)ADC_FUSES_BIASCAL_ADDR >>
@@ -186,12 +190,15 @@ static int _adc_configure(adc_res_t res)
           (res == ADC_RES_12BIT))){
         return -1;
     }
+
     _adc_poweroff();
+
     if (ADC_DEV->CTRLA.reg & ADC_CTRLA_SWRST ||
         ADC_DEV->CTRLA.reg & ADC_CTRLA_ENABLE ) {
         DEBUG("adc: not ready\n");
         return -1;
     }
+
     _setup_clock();
     _setup_calibration();
 
@@ -211,7 +218,7 @@ static int _adc_configure(adc_res_t res)
     /* Disable all interrupts */
     ADC_DEV->INTENCLR.reg = 0xFF;
 
-#ifdef CPU_SAMD21
+#ifdef SYSCTRL_VREF_BGOUTEN
     /* Enable bandgap if VREF is internal 1V */
     if (ADC_REF_DEFAULT == ADC_REFCTRL_REFSEL_INT1V) {
         SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
@@ -235,10 +242,12 @@ int adc_init(adc_t line)
         DEBUG("adc: line arg not applicable\n");
         return -1;
     }
+
     _prep();
     gpio_init(adc_channels[line].pin, GPIO_IN);
     gpio_init_mux(adc_channels[line].pin, GPIO_MUX_B);
     _done();
+
     return 0;
 }
 
@@ -248,22 +257,30 @@ int32_t adc_sample(adc_t line, adc_res_t res)
         DEBUG("adc: line arg not applicable\n");
         return -1;
     }
+
     _prep();
+
     if (_adc_configure(res) != 0) {
         _done();
         DEBUG("adc: configuration failed\n");
         return -1;
     }
-    ADC_DEV->INPUTCTRL.reg = ADC_GAIN_FACTOR_DEFAULT |
+
-                         adc_channels[line].muxpos | ADC_NEG_INPUT;
+    ADC_DEV->INPUTCTRL.reg = ADC_GAIN_FACTOR_DEFAULT
+                           | adc_channels[line].muxpos
+                           | ADC_NEG_INPUT;
     _wait_syncbusy();
 
     /* Start the conversion */
     ADC_DEV->SWTRIG.reg = ADC_SWTRIG_START;
+
     /* Wait for the result */
     while (!(ADC_DEV->INTFLAG.reg & ADC_INTFLAG_RESRDY)) {}
+
     int result = ADC_DEV->RESULT.reg;
+
     _adc_poweroff();
     _done();
+
     return result;
 }

cpu/sam0_common/periph/cpuid.c

@@ -25,7 +25,7 @@
 
 #include "periph/cpuid.h"
 
-#ifdef CPU_SAMD5X
+#ifdef CPU_COMMON_SAMD5X
 #define WORD0               (*(volatile uint32_t *)0x008061FC)
 #define WORD1               (*(volatile uint32_t *)0x00806010)
 #define WORD2               (*(volatile uint32_t *)0x00806014)

cpu/sam0_common/periph/dma.c

@@ -81,7 +81,7 @@ void dma_init(void)
     NVIC_EnableIRQ(DMAC_1_IRQn);
     NVIC_EnableIRQ(DMAC_2_IRQn);
     NVIC_EnableIRQ(DMAC_3_IRQn);
-#elif defined(CPU_FAM_SAMD5X)
+#elif defined(CPU_COMMON_SAMD5X)
     NVIC_EnableIRQ(DMAC_0_IRQn);
     NVIC_EnableIRQ(DMAC_1_IRQn);
     NVIC_EnableIRQ(DMAC_2_IRQn);

cpu/sam0_common/periph/flashpage.c

@@ -139,7 +139,7 @@ static void _erase_page(void* page, void (*cmd_erase)(void))
     /* ADDR drives the hardware (16-bit) address to the NVM when a command is executed using CMDEX.
      * 8-bit addresses must be shifted one bit to the right before writing to this register.
      */
-#if defined(CPU_SAMD21) || defined(CPU_SAML21)
+#if defined(CPU_COMMON_SAMD21) || defined(CPU_COMMON_SAML21)
     page_addr >>= 1;
 #endif
 

cpu/sam0_common/periph/gpio.c

@@ -49,7 +49,7 @@
 /**
  * @brief   Number of external interrupt lines
  */
-#ifdef CPU_SAML1X
+#ifdef CPU_COMMON_SAML1X
 #define NUMOF_IRQS                  (8U)
 #else
 #define NUMOF_IRQS                  (16U)
@@ -180,7 +180,7 @@ void gpio_write(gpio_t pin, int value)
 
 #ifdef MODULE_PERIPH_GPIO_IRQ
 
-#ifdef CPU_FAM_SAMD21
+#ifdef CPU_COMMON_SAMD21
 #define EIC_SYNC() while (_EIC->STATUS.bit.SYNCBUSY)
 #else
 #define EIC_SYNC() while (_EIC->SYNCBUSY.bit.ENABLE)
@@ -212,14 +212,14 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
     /* configure pin as input and set MUX to peripheral function A */
     gpio_init(pin, mode);
     gpio_init_mux(pin, GPIO_MUX_A);
-#ifdef CPU_FAM_SAMD21
+#ifdef CPU_COMMON_SAMD21
     /* enable clocks for the EIC module */
     PM->APBAMASK.reg |= PM_APBAMASK_EIC;
     GCLK->CLKCTRL.reg = EIC_GCLK_ID
                       | GCLK_CLKCTRL_CLKEN
                       | GCLK_CLKCTRL_GEN(CONFIG_SAM0_GCLK_GPIO);
     while (GCLK->STATUS.bit.SYNCBUSY) {}
-#else /* CPU_FAM_SAML21 */
+#else /* CPU_COMMON_SAML21 */
     /* enable clocks for the EIC module */
     MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
     GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(CONFIG_SAM0_GCLK_GPIO);
@@ -231,10 +231,10 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
     _EIC->CONFIG[exti >> 3].reg &= ~(0xf << ((exti & 0x7) * 4));
     _EIC->CONFIG[exti >> 3].reg |=  (flank << ((exti & 0x7) * 4));
     /* enable the global EIC interrupt */
-#ifdef CPU_SAML1X
+#ifdef CPU_COMMON_SAML1X
     /* EXTI[4..7] are binded to EIC_OTHER_IRQn */
     NVIC_EnableIRQ((exti > 3 )? EIC_OTHER_IRQn : (EIC_0_IRQn + exti));
-#elif defined(CPU_SAMD5X)
+#elif defined(CPU_COMMON_SAMD5X)
     NVIC_EnableIRQ(EIC_0_IRQn + exti);
 #else
     NVIC_EnableIRQ(EIC_IRQn);
@@ -242,12 +242,12 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
     /* clear interrupt flag and enable the interrupt line and line wakeup */
     _EIC->INTFLAG.reg = (1 << exti);
     _EIC->INTENSET.reg = (1 << exti);
-#ifdef CPU_FAM_SAMD21
+#ifdef CPU_COMMON_SAMD21
     _EIC->WAKEUP.reg |= (1 << exti);
     /* enable the EIC module*/
     _EIC->CTRL.reg = EIC_CTRL_ENABLE;
     EIC_SYNC();
-#else /* CPU_FAM_SAML21 */
+#else /* CPU_COMMON_SAML21 */
     /* enable the EIC module*/
     _EIC->CTRLA.reg = EIC_CTRLA_ENABLE;
     EIC_SYNC();
@@ -256,7 +256,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
 }
 
 inline static void reenable_eic(gpio_eic_clock_t clock) {
-#if defined(CPU_SAMD21)
+#if defined(CPU_COMMON_SAMD21)
     if (clock == _EIC_CLOCK_SLOW) {
         GCLK->CLKCTRL.reg = EIC_GCLK_ID
                           | GCLK_CLKCTRL_CLKEN
@@ -339,7 +339,7 @@ void gpio_irq_disable(gpio_t pin)
     _EIC->INTENCLR.reg = (1 << exti);
 }
 
-#if defined(CPU_SAML1X)
+#if defined(CPU_COMMON_SAML1X)
 void isr_eic_other(void)
 #else
 void isr_eic(void)
@@ -360,7 +360,7 @@ void isr_eic(void)
     cortexm_isr_end();
 }
 
-#if defined(CPU_SAML1X) || defined(CPU_SAMD5X)
+#if defined(CPU_COMMON_SAML1X) || defined(CPU_COMMON_SAMD5X)
 
 #define ISR_EICn(n)             \
 void isr_eic ## n (void)        \
@@ -374,7 +374,7 @@ ISR_EICn(0)
 ISR_EICn(1)
 ISR_EICn(2)
 ISR_EICn(3)
-#if defined(CPU_SAMD5X)
+#if defined(CPU_COMMON_SAMD5X)
 ISR_EICn(4)
 ISR_EICn(5)
 ISR_EICn(6)
@@ -389,8 +389,8 @@ ISR_EICn(13)
 ISR_EICn(14)
 ISR_EICn(15)
 #endif /* NUMOF_IRQS > 8 */
-#endif /* CPU_SAMD5X */
+#endif /* CPU_COMMON_SAMD5X */
-#endif /* CPU_SAML1X || CPU_SAMD5X */
+#endif /* CPU_COMMON_SAML1X || CPU_COMMON_SAMD5X */
 
 #else /* MODULE_PERIPH_GPIO_IRQ */
 

cpu/sam0_common/periph/i2c.c

@@ -45,7 +45,7 @@
 #define BUSSTATE_OWNER SERCOM_I2CM_STATUS_BUSSTATE(2)
 #define BUSSTATE_BUSY SERCOM_I2CM_STATUS_BUSSTATE(3)
 
-#if defined(CPU_SAML21) || defined(CPU_SAML1X) || defined(CPU_SAMD5X)
+#if defined(CPU_COMMON_SAML21) || defined(CPU_COMMON_SAML1X) || defined(CPU_COMMON_SAMD5X)
 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER SERCOM_I2CM_CTRLA_MODE(5)
 #endif
 

cpu/sam0_common/periph/rtc_rtt.c

@@ -131,7 +131,7 @@ static inline void _rtt_reset(void)
 #endif
 }
 
-#ifdef CPU_SAMD21
+#ifdef CPU_COMMON_SAMD21
 static void _rtc_clock_setup(void)
 {
     /* Use 1024 Hz GCLK */
@@ -150,7 +150,7 @@ static void _rtt_clock_setup(void)
     while (GCLK->STATUS.bit.SYNCBUSY) {}
 }
 
-#else /* CPU_SAMD21 - Clock Setup */
+#else /* CPU_COMMON_SAMD21 - Clock Setup */
 
 static void _rtc_clock_setup(void)
 {
@@ -192,7 +192,7 @@ static void _rtt_clock_setup(void)
 #error "No clock source for RTT selected. "
 #endif
 }
-#endif /* !CPU_SAMD21 - Clock Setup */
+#endif /* !CPU_COMMON_SAMD21 - Clock Setup */
 
 static void _rtc_init(void)
 {

cpu/sam0_common/periph/spi.c

@@ -233,14 +233,14 @@ static void _blocking_transfer(spi_t bus, const void *out, void *in, size_t len)
 
 static void _dma_execute(spi_t bus)
 {
-#if defined(CPU_FAM_SAMD21)
+#if defined(CPU_COMMON_SAMD21)
     pm_block(SAMD21_PM_IDLE_1);
 #endif
     dma_start(_dma_state[bus].rx_dma);
     dma_start(_dma_state[bus].tx_dma);
 
     dma_wait(_dma_state[bus].rx_dma);
-#if defined(CPU_FAM_SAMD21)
+#if defined(CPU_COMMON_SAMD21)
     pm_unblock(SAMD21_PM_IDLE_1);
 #endif
 }

cpu/sam0_common/periph/uart.c

@@ -32,7 +32,7 @@
 #define ENABLE_DEBUG (0)
 #include "debug.h"
 
-#if defined (CPU_SAML1X) || defined (CPU_SAMD5X)
+#if defined (CPU_COMMON_SAML1X) || defined (CPU_COMMON_SAMD5X)
 #define UART_HAS_TX_ISR
 #endif
 

cpu/sam0_common/periph/usbdev.c

@@ -242,7 +242,7 @@ static inline void _poweron(sam0_common_usb_t *dev)
     PM->APBBMASK.reg |= PM_APBBMASK_USB;
 #endif
 
-#if defined(CPU_FAM_SAMD21)
+#if defined(CPU_COMMON_SAMD21)
     GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
                       | GCLK_CLKCTRL_GEN(dev->config->gclk_src)
                       | GCLK_CLKCTRL_ID(USB_GCLK_ID);
@@ -294,14 +294,14 @@ static usbdev_ep_t *_usbdev_new_ep(usbdev_t *dev, usb_ep_type_t type,
 
 static void _block_pm(void)
 {
-#if defined(CPU_FAM_SAMD21)
+#if defined(CPU_COMMON_SAMD21)
     pm_block(SAMD21_PM_IDLE_1);
 #endif
 }
 
 static void _unblock_pm(void)
 {
-#if defined(CPU_FAM_SAMD21)
+#if defined(CPU_COMMON_SAMD21)
     pm_unblock(SAMD21_PM_IDLE_1);
 #endif
 }
@@ -363,7 +363,7 @@ static void _usbdev_init(usbdev_t *dev)
     _block_pm();
     usbdev->usbdev.cb(&usbdev->usbdev, USBDEV_EVENT_HOST_CONNECT);
     /* Interrupt configuration */
-#ifdef CPU_FAM_SAMD5X
+#ifdef CPU_COMMON_SAMD5X
     NVIC_EnableIRQ(USB_0_IRQn);
     NVIC_EnableIRQ(USB_1_IRQn);
     NVIC_EnableIRQ(USB_2_IRQn);

cpu/sam0_common/periph/wdt.c

@@ -45,7 +45,7 @@
 static inline void _set_enable(bool on)
 {
 /* work around strange watchdog behaviour if IDLE2 is used on samd21 */
-#ifdef CPU_FAM_SAMD21
+#ifdef CPU_COMMON_SAMD21
     if (on) {
         pm_block(1);
     }
@@ -80,7 +80,7 @@ static uint32_t ms_to_per(uint32_t ms)
     return 29 - __builtin_clz(cycles - 1);
 }
 
-#ifdef CPU_SAMD21
+#ifdef CPU_COMMON_SAMD21
 static void _wdt_clock_setup(void)
 {
     /* Connect to GCLK3 (~1.024 kHz) */

cpu/samd21/Kconfig

@@ -5,33 +5,20 @@
 # directory for more details.
 #
 
-config CPU_FAM_SAMD21
+config CPU_COMMON_SAMD21
     bool
     select CPU_COMMON_SAM0
     select CPU_CORE_CORTEX_M0PLUS
     select HAS_CPU_SAMD21
     select HAS_PUF_SRAM
 
-## CPU Models
+config CPU_FAM_SAMD21
-config CPU_MODEL_SAMD21E18A
     bool
-    select CPU_FAM_SAMD21
+    select CPU_COMMON_SAMD21
 
-config CPU_MODEL_SAMD21G18A
+config CPU_FAM_SAMR21
     bool
-    select CPU_FAM_SAMD21
+    select CPU_COMMON_SAMD21
-
-config CPU_MODEL_SAMD21J18A
-    bool
-    select CPU_FAM_SAMD21
-
-config CPU_MODEL_SAMR21E18A
-    bool
-    select CPU_FAM_SAMD21
-
-config CPU_MODEL_SAMR21G18A
-    bool
-    select CPU_FAM_SAMD21
 
 ## Definition of specific features
 config HAS_CPU_SAMD21
@@ -42,15 +29,12 @@ config HAS_CPU_SAMD21
 ## Common CPU symbols
 config CPU_FAM
     default "samd21" if CPU_FAM_SAMD21
-
+    default "samr21" if CPU_FAM_SAMR21
-config CPU_MODEL
-    default "samd21e18a" if CPU_MODEL_SAMD21E18A
-    default "samd21g18a" if CPU_MODEL_SAMD21G18A
-    default "samd21j18a" if CPU_MODEL_SAMD21J18A
-    default "samr21e18a" if CPU_MODEL_SAMR21E18A
-    default "samr21g18a" if CPU_MODEL_SAMR21G18A
 
 config CPU
-    default "samd21"
+    default "samd21" if CPU_COMMON_SAMD21
+
+source "$(RIOTCPU)/samd21/Kconfig.samd21"
+source "$(RIOTCPU)/samd21/Kconfig.samr21"
 
 source "$(RIOTCPU)/sam0_common/Kconfig"

cpu/samd21/Kconfig.samd21

@@ -0,0 +1,172 @@
+## CPU Models
+config CPU_MODEL_SAMD21E15A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E16A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E17A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E18A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G15A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G16A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G17A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G17AU
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G18A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G18AU
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21J15A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21J16A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21J17A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21J18A
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E15BU
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E16BU
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E15B
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E15CU
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E15L
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E16B
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E16CU
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E16L
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G15B
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G15L
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G16B
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G16L
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21J15B
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21J16B
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E17D
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E17DU
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21E17L
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G17D
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21G17L
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL_SAMD21J17D
+    bool
+    select CPU_FAM_SAMD21
+
+config CPU_MODEL
+    default "samd21e15a" if CPU_MODEL_SAMD21E15A
+    default "samd21e16a" if CPU_MODEL_SAMD21E16A
+    default "samd21e17a" if CPU_MODEL_SAMD21E17A
+    default "samd21e18a" if CPU_MODEL_SAMD21E18A
+    default "samd21g15a" if CPU_MODEL_SAMD21G15A
+    default "samd21g16a" if CPU_MODEL_SAMD21G16A
+    default "samd21g17a" if CPU_MODEL_SAMD21G17A
+    default "samd21g17au" if CPU_MODEL_SAMD21G17AU
+    default "samd21g18a" if CPU_MODEL_SAMD21G18A
+    default "samd21g18au" if CPU_MODEL_SAMD21G18AU
+    default "samd21j15a" if CPU_MODEL_SAMD21J15A
+    default "samd21j16a" if CPU_MODEL_SAMD21J16A
+    default "samd21j17a" if CPU_MODEL_SAMD21J17A
+    default "samd21j18a" if CPU_MODEL_SAMD21J18A
+    default "samd21e15bu" if CPU_MODEL_SAMD21E15BU
+    default "samd21e16bu" if CPU_MODEL_SAMD21E16BU
+    default "samd21e15b" if CPU_MODEL_SAMD21E15B
+    default "samd21e15cu" if CPU_MODEL_SAMD21E15CU
+    default "samd21e15l" if CPU_MODEL_SAMD21E15L
+    default "samd21e16b" if CPU_MODEL_SAMD21E16B
+    default "samd21e16cu" if CPU_MODEL_SAMD21E16CU
+    default "samd21e16l" if CPU_MODEL_SAMD21E16L
+    default "samd21g15b" if CPU_MODEL_SAMD21G15B
+    default "samd21g15l" if CPU_MODEL_SAMD21G15L
+    default "samd21g16b" if CPU_MODEL_SAMD21G16B
+    default "samd21g16l" if CPU_MODEL_SAMD21G16L
+    default "samd21j15b" if CPU_MODEL_SAMD21J15B
+    default "samd21j16b" if CPU_MODEL_SAMD21J16B
+    default "samd21e17d" if CPU_MODEL_SAMD21E17D
+    default "samd21e17du" if CPU_MODEL_SAMD21E17DU
+    default "samd21e17l" if CPU_MODEL_SAMD21E17L
+    default "samd21g17d" if CPU_MODEL_SAMD21G17D
+    default "samd21g17l" if CPU_MODEL_SAMD21G17L
+    default "samd21j17d" if CPU_MODEL_SAMD21J17D

cpu/samd21/Kconfig.samr21

@@ -0,0 +1,37 @@
+## CPU Models
+config CPU_MODEL_SAMR21E16A
+    bool
+    select CPU_FAM_SAMR21
+
+config CPU_MODEL_SAMR21E17A
+    bool
+    select CPU_FAM_SAMR21
+
+config CPU_MODEL_SAMR21E18A
+    bool
+    select CPU_FAM_SAMR21
+
+config CPU_MODEL_SAMR21E19A
+    bool
+    select CPU_FAM_SAMR21
+
+config CPU_MODEL_SAMR21G16A
+    bool
+    select CPU_FAM_SAMR21
+
+config CPU_MODEL_SAMR21G17A
+    bool
+    select CPU_FAM_SAMR21
+
+config CPU_MODEL_SAMR21G18A
+    bool
+    select CPU_FAM_SAMR21
+
+config CPU_MODEL
+    default "samr21e16a" if CPU_MODEL_SAMR21E16A
+    default "samr21e17a" if CPU_MODEL_SAMR21E17A
+    default "samr21e18a" if CPU_MODEL_SAMR21E18A
+    default "samr21e19a" if CPU_MODEL_SAMR21E19A
+    default "samr21g16a" if CPU_MODEL_SAMR21G16A
+    default "samr21g17a" if CPU_MODEL_SAMR21G17A
+    default "samr21g18a" if CPU_MODEL_SAMR21G18A

cpu/samd21/Makefile.features

@@ -1,5 +1,4 @@
 CPU_CORE = cortex-m0plus
-CPU_FAM  = samd21
 
 FEATURES_PROVIDED += puf_sram
 

cpu/samd21/Makefile.include

@@ -14,5 +14,7 @@ ifneq (,$(filter samr21%,$(CPU_MODEL)))
   CFLAGS += -DCPU_SAMR21
 endif
 
+CFLAGS += -DCPU_COMMON_SAMD21
+
 include $(RIOTCPU)/sam0_common/Makefile.include
 include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/samd5x/Kconfig

@@ -5,7 +5,7 @@
 # directory for more details.
 #
 
-config CPU_FAM_SAMD5X
+config CPU_COMMON_SAMD5X
     bool
     select CPU_COMMON_SAM0
     select CPU_CORE_CORTEX_M4F
@@ -14,25 +14,29 @@ config CPU_FAM_SAMD5X
     select HAS_CPU_SAMD5X
     select HAS_PERIPH_HWRNG
 
-## CPU Models
+config CPU_FAM_SAMD51
-config CPU_MODEL_SAME54P20A
     bool
-    select CPU_FAM_SAMD5X
+    select CPU_COMMON_SAMD5X
+
+config CPU_FAM_SAME54
+    bool
+    select CPU_COMMON_SAMD5X
 
 ## Declaration of specific features
 config HAS_CPU_SAMD5X
     bool
     help
-        Indicates that a 'samd5x' cpu is being used.
+        Indicates that a SAMD5x/SAME5x cpu is being used.
 
 ## CPU common symbols
 config CPU_FAM
-    default "samd5x" if CPU_FAM_SAMD5X
+    default "samd51" if CPU_FAM_SAMD51
-
+    default "same54" if CPU_FAM_SAME54
-config CPU_MODEL
-    default "same54p20a" if CPU_MODEL_SAME54P20A
 
 config CPU
-    default "samd5x" if CPU_FAM_SAMD5X
+    default "samd5x" if CPU_COMMON_SAMD5X
+
+source "$(RIOTCPU)/samd5x/Kconfig.samd51"
+source "$(RIOTCPU)/samd5x/Kconfig.same54"
 
 source "$(RIOTCPU)/sam0_common/Kconfig"

cpu/samd5x/Kconfig.samd51

@@ -0,0 +1,47 @@
+## CPU Models
+config CPU_MODEL_SAMD51G18A
+    bool
+    select CPU_FAM_SAMD51
+
+config CPU_MODEL_SAMD51G19A
+    bool
+    select CPU_FAM_SAMD51
+
+config CPU_MODEL_SAMD51J18A
+    bool
+    select CPU_FAM_SAMD51
+
+config CPU_MODEL_SAMD51J19A
+    bool
+    select CPU_FAM_SAMD51
+
+config CPU_MODEL_SAMD51J20A
+    bool
+    select CPU_FAM_SAMD51
+
+config CPU_MODEL_SAMD51N19A
+    bool
+    select CPU_FAM_SAMD51
+
+config CPU_MODEL_SAMD51N20A
+    bool
+    select CPU_FAM_SAMD51
+
+config CPU_MODEL_SAMD51P19A
+    bool
+    select CPU_FAM_SAMD51
+
+config CPU_MODEL_SAMD51P20A
+    bool
+    select CPU_FAM_SAMD51
+
+config CPU_MODEL
+    default "samd51g18a" if CPU_MODEL_SAMD51G18A
+    default "samd51g19a" if CPU_MODEL_SAMD51G19A
+    default "samd51j18a" if CPU_MODEL_SAMD51J18A
+    default "samd51j19a" if CPU_MODEL_SAMD51J19A
+    default "samd51j20a" if CPU_MODEL_SAMD51J20A
+    default "samd51n19a" if CPU_MODEL_SAMD51N19A
+    default "samd51n20a" if CPU_MODEL_SAMD51N20A
+    default "samd51p19a" if CPU_MODEL_SAMD51P19A
+    default "samd51p20a" if CPU_MODEL_SAMD51P20A

cpu/samd5x/Kconfig.same54

@@ -0,0 +1,22 @@
+## CPU Models
+config CPU_MODEL_SAME54N19A
+    bool
+    select CPU_FAM_SAME54
+
+config CPU_MODEL_SAME54N20A
+    bool
+    select CPU_FAM_SAME54
+
+config CPU_MODEL_SAME54P19A
+    bool
+    select CPU_FAM_SAME54
+
+config CPU_MODEL_SAME54P20A
+    bool
+    select CPU_FAM_SAME54
+
+config CPU_MODEL
+    default "same54n19a" if CPU_MODEL_SAME54N19A
+    default "same54n20a" if CPU_MODEL_SAME54N20A
+    default "same54p19a" if CPU_MODEL_SAME54P19A
+    default "same54p20a" if CPU_MODEL_SAME54P20A

cpu/samd5x/Makefile.features

@@ -1,5 +1,4 @@
 CPU_CORE = cortex-m4f
-CPU_FAM  = samd5x
 
 FEATURES_PROVIDED += periph_hwrng
 FEATURES_PROVIDED += backup_ram

cpu/samd5x/Makefile.include

@@ -5,6 +5,8 @@ ifneq (,$(filter same54%,$(CPU_MODEL)))
   CFLAGS += -DCPU_SAME54
 endif
 
+CFLAGS += -DCPU_COMMON_SAMD5X
+
 # Slot size is determined by "((total_flash_size - RIOTBOOT_LEN) / 2)".
 # If RIOTBOOT_LEN uses an uneven number of flashpages, the remainder of the
 # flash cannot be divided by two slots while staying FLASHPAGE_SIZE aligned.

cpu/saml1x/Kconfig

@@ -20,15 +20,6 @@ config CPU_FAM_SAML11
     bool
     select CPU_COMMON_SAML1X
 
-## CPU Models
-config CPU_MODEL_SAML10E16A
-    bool
-    select CPU_FAM_SAML10
-
-config CPU_MODEL_SAML11E16A
-    bool
-    select CPU_FAM_SAML11
-
 ## Declaration of specific features
 config HAS_CPU_SAML1X
     bool
@@ -40,11 +31,10 @@ config CPU_FAM
     default "saml10" if CPU_FAM_SAML10
     default "saml11" if CPU_FAM_SAML11
 
-config CPU_MODEL
-    default "saml10e16a" if CPU_MODEL_SAML10E16A
-    default "saml11e16a" if CPU_MODEL_SAML11E16A
-
 config CPU
     default "saml1x" if CPU_COMMON_SAML1X
 
+source "$(RIOTCPU)/saml1x/Kconfig.saml10"
+source "$(RIOTCPU)/saml1x/Kconfig.saml11"
+
 source "$(RIOTCPU)/sam0_common/Kconfig"

cpu/saml1x/Kconfig.saml10

@@ -0,0 +1,32 @@
+## CPU Models
+config CPU_MODEL_SAML10D14A
+    bool
+    select CPU_FAM_SAML10
+
+config CPU_MODEL_SAML10D15A
+    bool
+    select CPU_FAM_SAML10
+
+config CPU_MODEL_SAML10D16A
+    bool
+    select CPU_FAM_SAML10
+
+config CPU_MODEL_SAML10E14A
+    bool
+    select CPU_FAM_SAML10
+
+config CPU_MODEL_SAML10E15A
+    bool
+    select CPU_FAM_SAML10
+
+config CPU_MODEL_SAML10E16A
+    bool
+    select CPU_FAM_SAML10
+
+config CPU_MODEL
+    default "saml10d14a" if CPU_MODEL_SAML10D14A
+    default "saml10d15a" if CPU_MODEL_SAML10D15A
+    default "saml10d16a" if CPU_MODEL_SAML10D16A
+    default "saml10e14a" if CPU_MODEL_SAML10E14A
+    default "saml10e15a" if CPU_MODEL_SAML10E15A
+    default "saml10e16a" if CPU_MODEL_SAML10E16A

cpu/saml1x/Kconfig.saml11

@@ -0,0 +1,32 @@
+## CPU Models
+config CPU_MODEL_SAML11D14A
+    bool
+    select CPU_FAM_SAML11
+
+config CPU_MODEL_SAML11D15A
+    bool
+    select CPU_FAM_SAML11
+
+config CPU_MODEL_SAML11D16A
+    bool
+    select CPU_FAM_SAML11
+
+config CPU_MODEL_SAML11E14A
+    bool
+    select CPU_FAM_SAML11
+
+config CPU_MODEL_SAML11E15A
+    bool
+    select CPU_FAM_SAML11
+
+config CPU_MODEL_SAML11E16A
+    bool
+    select CPU_FAM_SAML11
+
+config CPU_MODEL
+    default "saml11d14a" if CPU_MODEL_SAML11D14A
+    default "saml11d15a" if CPU_MODEL_SAML11D15A
+    default "saml11d16a" if CPU_MODEL_SAML11D16A
+    default "saml11e14a" if CPU_MODEL_SAML11E14A
+    default "saml11e15a" if CPU_MODEL_SAML11E15A
+    default "saml11e16a" if CPU_MODEL_SAML11E16A

cpu/saml1x/Makefile.features

@@ -1,13 +1,5 @@
 CPU_CORE = cortex-m23
 
-ifneq (,$(filter saml10%,$(CPU_MODEL)))
-  CPU_FAM = saml10
-else ifneq (,$(filter saml11%,$(CPU_MODEL)))
-  CPU_FAM = saml11
-else
-  $(error Unknown saml1x CPU Model: $(CPU_MODEL))
-endif
-
 # TODO: The cortex-m23 MPU is not ported
 # FEATURES_PROVIDED += cortexm_mpu
 

cpu/saml1x/Makefile.include

@@ -5,5 +5,7 @@ ifneq (,$(filter saml11%,$(CPU_MODEL)))
   CFLAGS += -DCPU_SAML11
 endif
 
+CFLAGS += -DCPU_COMMON_SAML1X
+
 include $(RIOTCPU)/sam0_common/Makefile.include
 include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/saml21/Kconfig

@@ -5,31 +5,25 @@
 # directory for more details.
 #
 
-config CPU_FAM_SAML21
+config CPU_COMMON_SAML21
     bool
     select CPU_COMMON_SAM0
     select CPU_CORE_CORTEX_M0PLUS
     select HAS_BACKUP_RAM
     select HAS_CPU_SAML21
 
-## CPU Models
+config CPU_FAM_SAML21
-config CPU_MODEL_SAML21J18A
     bool
-    select CPU_FAM_SAML21
+    select CPU_COMMON_SAML21
     select HAS_PERIPH_HWRNG
 
-config CPU_MODEL_SAML21J18B
+config CPU_FAM_SAMR30
     bool
-    select CPU_FAM_SAML21
+    select CPU_COMMON_SAML21
-    select HAS_PERIPH_HWRNG
 
-config CPU_MODEL_SAMR30G18A
+config CPU_FAM_SAMR34
     bool
-    select CPU_FAM_SAML21
+    select CPU_COMMON_SAML21
-
-config CPU_MODEL_SAMR34J18B
-    bool
-    select CPU_FAM_SAML21
     select HAS_PERIPH_HWRNG
 
 ## Declaration of specific features
@@ -41,14 +35,14 @@ config HAS_CPU_SAML21
 ## Common CPU symbols
 config CPU_FAM
     default "saml21" if CPU_FAM_SAML21
-
+    default "samr30" if CPU_FAM_SAMR30
-config CPU_MODEL
+    default "samr34" if CPU_FAM_SAMR34
-    default "saml21j18a" if CPU_MODEL_SAML21J18A
-    default "saml21j18b" if CPU_MODEL_SAML21J18B
-    default "samr30g18a" if CPU_MODEL_SAMR30G18A
-    default "samr34j18b" if CPU_MODEL_SAMR34J18B
 
 config CPU
-    default "saml21" if CPU_FAM_SAML21
+    default "saml21" if CPU_COMMON_SAML21
+
+source "$(RIOTCPU)/saml21/Kconfig.saml21"
+source "$(RIOTCPU)/saml21/Kconfig.samr30"
+source "$(RIOTCPU)/saml21/Kconfig.samr34"
 
 source "$(RIOTCPU)/sam0_common/Kconfig"

cpu/saml21/Kconfig.saml21

@@ -0,0 +1,77 @@
+## CPU Models
+config CPU_MODEL_SAML21E15B
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21E16B
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21E17B
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21E18B
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21G16B
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21G17B
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21G18B
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21J16B
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21J17B
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21J17BU
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21J18B
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21J18BU
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21E18A
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21G18A
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL_SAML21J18A
+    bool
+    select CPU_FAM_SAML21
+
+config CPU_MODEL
+    default "saml21e15b" if CPU_MODEL_SAML21E15B
+    default "saml21e16b" if CPU_MODEL_SAML21E16B
+    default "saml21e17b" if CPU_MODEL_SAML21E17B
+    default "saml21e18b" if CPU_MODEL_SAML21E18B
+    default "saml21g16b" if CPU_MODEL_SAML21G16B
+    default "saml21g17b" if CPU_MODEL_SAML21G17B
+    default "saml21g18b" if CPU_MODEL_SAML21G18B
+    default "saml21j16b" if CPU_MODEL_SAML21J16B
+    default "saml21j17b" if CPU_MODEL_SAML21J17B
+    default "saml21j17bu" if CPU_MODEL_SAML21J17BU
+    default "saml21j18b" if CPU_MODEL_SAML21J18B
+    default "saml21j18bu" if CPU_MODEL_SAML21J18BU
+    default "saml21e18a" if CPU_MODEL_SAML21E18A
+    default "saml21g18a" if CPU_MODEL_SAML21G18A
+    default "saml21j18a" if CPU_MODEL_SAML21J18A

cpu/saml21/Kconfig.samr30

@@ -0,0 +1,12 @@
+## CPU Models
+config CPU_MODEL_SAMR30E18A
+    bool
+    select CPU_FAM_SAMR30
+
+config CPU_MODEL_SAMR30G18A
+    bool
+    select CPU_FAM_SAMR30
+
+config CPU_MODEL
+    default "samr30e18a" if CPU_MODEL_SAMR30E18A
+    default "samr30g18a" if CPU_MODEL_SAMR30G18A

cpu/saml21/Kconfig.samr34

@@ -0,0 +1,17 @@
+## CPU Models
+config CPU_MODEL_SAMR34J16B
+    bool
+    select CPU_FAM_SAMR34
+
+config CPU_MODEL_SAMR34J17B
+    bool
+    select CPU_FAM_SAMR34
+
+config CPU_MODEL_SAMR34J18B
+    bool
+    select CPU_FAM_SAMR34
+
+config CPU_MODEL
+    default "samr34j16b" if CPU_MODEL_SAMR34J16B
+    default "samr34j17b" if CPU_MODEL_SAMR34J17B
+    default "samr34j18b" if CPU_MODEL_SAMR34J18B

cpu/saml21/Makefile.features

@@ -1,5 +1,4 @@
 CPU_CORE = cortex-m0plus
-CPU_FAM  = saml21
 
 # The SAMR30 line of MCUs does not contain a TRNG
 CPU_MODELS_WITHOUT_HWRNG += samr30%

cpu/saml21/Makefile.include

@@ -11,6 +11,8 @@ ifneq (,$(filter samr34%,$(CPU_MODEL)))
   CFLAGS += -DCPU_SAMR34
 endif
 
+CFLAGS += -DCPU_COMMON_SAML21
+
 ifneq (,$(filter saml21j18b saml21j18a samr30g18a samr34j18b,$(CPU_MODEL)))
   BACKUP_RAM_ADDR = 0x30000000
   BACKUP_RAM_LEN  = 0x2000