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cpu/stm32/periph_eth: Optimize / fix flush

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- Added missing wait for TX flush
- Grouped access to the same registers of the Ethernet PHY to reduce accesses.
  (The compiler won't optimize accesses to `volatile`, as defined in the C
  standard.)
This commit is contained in:
Marian Buschsieweke 2020-07-24 11:44:08 +02:00
parent a5dbec33d9
commit 53375f04bf
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GPG Key ID: 61F64C6599B1539F
1 changed files with 7 additions and 5 deletions
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12
cpu/stm32/periph/eth.c
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@ -210,13 +210,15 @@ int stm32_eth_init(void)
NVIC_EnableIRQ(ETH_IRQn); NVIC_EnableIRQ(ETH_IRQn);
ETH->DMAIER |= ETH_DMAIER_NISE | ETH_DMAIER_TIE | ETH_DMAIER_RIE; ETH->DMAIER |= ETH_DMAIER_NISE | ETH_DMAIER_TIE | ETH_DMAIER_RIE;
/* enable */ /* enable transmitter and receiver */
ETH->MACCR |= ETH_MACCR_TE; ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
/* flush transmit FIFO */
ETH->DMAOMR |= ETH_DMAOMR_FTF; ETH->DMAOMR |= ETH_DMAOMR_FTF;
ETH->MACCR |= ETH_MACCR_RE; /* wait for FIFO flushing to complete */
while (ETH->DMAOMR & ETH_DMAOMR_FTF) { }
ETH->DMAOMR |= ETH_DMAOMR_ST; /* enable DMA TX and RX */
ETH->DMAOMR |= ETH_DMAOMR_SR; ETH->DMAOMR |= ETH_DMAOMR_ST | ETH_DMAOMR_SR;
/* configure speed, do it at the end so the PHY had time to /* configure speed, do it at the end so the PHY had time to
* reset */ * reset */