diff --git a/boards/common/stm32/dist/stm32mp1.cfg b/boards/common/stm32/dist/stm32mp1.cfg new file mode 100644 index 0000000000..8c0f0579db --- /dev/null +++ b/boards/common/stm32/dist/stm32mp1.cfg @@ -0,0 +1,3 @@ +source [find target/stm32mp15x.cfg] +reset_config srst_only +$_CHIPNAME.cm4 configure -rtos auto diff --git a/boards/common/stm32/include/cfg_timer_tim2.h b/boards/common/stm32/include/cfg_timer_tim2.h index 35a440371e..dee761f2fd 100644 --- a/boards/common/stm32/include/cfg_timer_tim2.h +++ b/boards/common/stm32/include/cfg_timer_tim2.h @@ -40,6 +40,8 @@ static const timer_conf_t timer_config[] = { #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ defined(CPU_FAM_STM32G4) .rcc_mask = RCC_APB1ENR1_TIM2EN, +#elif CPU_FAM_STM32MP1 + .rcc_mask = RCC_MC_APB1ENSETR_TIM2EN, #else .rcc_mask = RCC_APB1ENR_TIM2EN, #endif diff --git a/boards/stm32mp157c-dk2/Kconfig b/boards/stm32mp157c-dk2/Kconfig new file mode 100644 index 0000000000..2eda0d493f --- /dev/null +++ b/boards/stm32mp157c-dk2/Kconfig @@ -0,0 +1,17 @@ +# Copyright (C) 2020 Savoir-faire Linux +# +# This file is subject to the terms and conditions of the GNU Lesser General +# Public License v2.1. See the file LICENSE in the top level directory for more +# details. + +config BOARD + default "stm32mp157c-dk2" if BOARD_STM32MP157C_DK2 + +config BOARD_STM32MP157C_DK2 + bool + default y + select CPU_MODEL_STM32MP157CAC + + # Put defined MCU peripherals here (in alphabetical order) + select HAS_PERIPH_TIMER + select HAS_PERIPH_UART diff --git a/boards/stm32mp157c-dk2/Makefile b/boards/stm32mp157c-dk2/Makefile new file mode 100644 index 0000000000..f8fcbb53a0 --- /dev/null +++ b/boards/stm32mp157c-dk2/Makefile @@ -0,0 +1,3 @@ +MODULE = board + +include $(RIOTBASE)/Makefile.base diff --git a/boards/stm32mp157c-dk2/Makefile.dep b/boards/stm32mp157c-dk2/Makefile.dep new file mode 100644 index 0000000000..790e431594 --- /dev/null +++ b/boards/stm32mp157c-dk2/Makefile.dep @@ -0,0 +1,6 @@ +USEMODULE += mpu_stack_guard + +# Uncomment this line to build firmware in Engineering mode (BOOT0 off and +# BOOT2 on). +# You can also add it in your application Makefile. +# USEMODULE += stm32mp1_eng_mode diff --git a/boards/stm32mp157c-dk2/Makefile.features b/boards/stm32mp157c-dk2/Makefile.features new file mode 100644 index 0000000000..8849551dd9 --- /dev/null +++ b/boards/stm32mp157c-dk2/Makefile.features @@ -0,0 +1,7 @@ +CPU = stm32 +CPU_MODEL = stm32mp157cac + +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_gpio +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart diff --git a/boards/stm32mp157c-dk2/Makefile.include b/boards/stm32mp157c-dk2/Makefile.include new file mode 100644 index 0000000000..1d55ba58e3 --- /dev/null +++ b/boards/stm32mp157c-dk2/Makefile.include @@ -0,0 +1,20 @@ +# we use shared STM32 configuration snippets +INCLUDES += -I$(RIOTBOARD)/common/stm32/include + +# set default port depending on operating system +PORT_LINUX ?= /dev/ttyACM0 +PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) + +# setup serial terminal +include $(RIOTMAKE)/tools/serial.inc.mk + +# this board has an on-board ST-link adapter +DEBUG_ADAPTER = stlink-dap +OPENOCD_CORE = stm32mp15x.cm4 +GDB_PORT_CORE_OFFSET = 1 + +FFLAGS ?= flashr $(FLASHFILE) +DEBUGGER_FLAGS ?= debugr $(ELFFILE) + +# Setup of programmer and serial is shared between STM32 based boards +include $(RIOTMAKE)/boards/stm32.inc.mk diff --git a/boards/stm32mp157c-dk2/board.c b/boards/stm32mp157c-dk2/board.c new file mode 100644 index 0000000000..e6dfbf5463 --- /dev/null +++ b/boards/stm32mp157c-dk2/board.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_stm32mp157c-dk2 + * @{ + * + * @file + * @brief Board specific implementations for the STM32MP157C-DK2 board + * + * @author Gilles DOFFE + * + * @} + */ + +#include "board.h" +#include "periph/gpio.h" + +#include + +void board_init(void) +{ + /* initialize the CPU */ + cpu_init(); +} diff --git a/boards/stm32mp157c-dk2/doc.txt b/boards/stm32mp157c-dk2/doc.txt new file mode 100644 index 0000000000..d582b932e9 --- /dev/null +++ b/boards/stm32mp157c-dk2/doc.txt @@ -0,0 +1,105 @@ +/** +@defgroup boards_stm32mp157c-dk2 STM32MP157C-DK2 board +@ingroup boards +@brief Support for the STM32MP157C-DK2 board + +## Overview + +The STM32MP157C-DK2 is a board from ST featuring a double architecture based on +a dual Cortex-A7 and a Cortex-M4 STM32MP157C microcontroller with 384KB of SRAM +and no ROM Flash. + +## Hardware + +![STM32MP157C-DK2] +(https://www.st.com/bin/ecommerce/api/image.PF267415.en.feature-description-include-personalized-no-cpn-medium.jpg) + +### MCU + +| MCU | STM32MP157CAC | +|:---------- |:----------------- | +| Family | ARM Dual Cortex-A7 & Cortex-M4 | +| Vendor | ST Microelectronics | +| RAM | 384Kb for Cortex-M4 | +| Flash | None but 64KB of RETRAM | +| Frequency | up to 209MHz | +| FPU | yes | +| Timers | 32 (3x watchdog, 2x 4 Cortex-A7 system timers, 1x SysTick, 5x 16-bit Low-Power, 12x 16-bit, 2x 32-bit, 1 RTC) | +| ADCs | 2x 12-bit (16 channels), 2x 16-bit (16 channels) | +| UARTs | 4x UART + 4x USART | +| SPIs | 6 | +| I2Cs | 6 | +| RTC | 1 | +| CAN | 2 | +| USB | 3 | +| Vcc | 1.8V - 3.6V | +| Datasheet | [Datasheet](https://www.st.com/resource/en/datasheet/stm32mp157c.pdf) | +| Reference Manual | [Reference Manual](https://www.st.com/resource/en/reference_manual/dm00327659-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf) | +| Programming Manual | [Programming Manual](https://www.st.com/resource/en/programming_manual/dm00046982-stm32-cortexm4-mcus-and-mpus-programming-manual-stmicroelectronics.pdf) | +| Board Manual | [Board Manual](https://www.st.com/resource/en/user_manual/dm00591354-discovery-kits-with-stm32mp157-mpus-stmicroelectronics.pdf)| + +## Implementation Status + +| Device | ID | Supported | Comments | +|:------------- |:------------- |:------------- |:------------- | +| MCU | STM32MP157CAC | partly | | +| Low-level driver | GPIO | yes | | +| | UART | 1 UART | USART3 on PB12(RX)/PB10(TX) | +| | Timer | one 32 bit timer | TIM2 | + +## Flashing the device + +Note that the STM32MP157C-DK2 board has no ROM Flash, thus the firmware +needs to be reflashed each time the board is rebooted. + +### Boot selection jumper: + +| BOOT mode | BOOT0 | BOOT2 | +| :-------- |:----- |:----- | +| Engineering | 1 | 1 | +| SD Card (Linux) | 0 | 1 | + +### Engineering mode + +The STM32MP157C-DK2 board includes an on-board ST-LINK V2 programmer. The +easiest way to program the board is to use OpenOCD. Once you have installed +OpenOCD (look [here](https://github.com/RIOT-OS/RIOT/wiki/OpenOCD) for +installation instructions), you can flash the board simply by typing inside +your application directory: + +``` +USEMODULE='stm32mp1_eng_mode' make BOARD=stm32mp157c-dk2 flash +``` +and debug via GDB by simply typing +``` +USEMODULE='stm32mp1_eng_mode' make BOARD=stm32mp157c-dk2 debug +``` +### SD Card (Linux) mode + +This assumes that Linux is booted and that your Linux kernel supports STM32 +remoteproc framework. + +Build the firmware inside your application directory: +``` +make BOARD=stm32mp157c-dk2 +``` +Copy your firmware firmware.elf in /lib/firmwares on the Linux system. +(replace firmware.elf by your firmware filename) + +Then simply launch this commands on the Linux system as root user: +``` +echo firmware.elf > /sys/class/remoteproc/remoteproc0/firmware +echo start > /sys/class/remoteproc/remoteproc0/state +``` + +You can stop RIOT from Linux command line: +``` +echo stop > /sys/class/remoteproc/remoteproc0/state +``` + +## Supported Toolchains + +For using the STM32MP157C-DK2 board we strongly recommend the usage of the +[GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded) +toolchain. + */ diff --git a/boards/stm32mp157c-dk2/include/board.h b/boards/stm32mp157c-dk2/include/board.h new file mode 100644 index 0000000000..793071637a --- /dev/null +++ b/boards/stm32mp157c-dk2/include/board.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_stm32mp157c-dk2 + * @{ + * + * @file + * @brief Board specific definitions for the STM32MP157C-DK2 board + * + * @author Gilles DOFFE + * + * @} + */ + +#ifndef BOARD_H +#define BOARD_H + +#include "cpu.h" +#include "periph_conf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize board specific hardware + */ +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/stm32mp157c-dk2/include/periph_conf.h b/boards/stm32mp157c-dk2/include/periph_conf.h new file mode 100644 index 0000000000..567e4a25e5 --- /dev/null +++ b/boards/stm32mp157c-dk2/include/periph_conf.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_stm32mp157c-dk2 + * @{ + * + * @file + * @brief Board specific implementations for the STM32MP157C-DK2 board + * + * @author Gilles DOFFE + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +/* This board provides an LSE */ +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE 1 +#endif + +/* This board provides an HSE */ +#ifndef CONFIG_BOARD_HAS_HSE +#define CONFIG_BOARD_HAS_HSE 1 +#endif + +#include "periph_cpu.h" +#include "clk_conf.h" +#include "cfg_timer_tim2.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = USART3, + .rcc_mask = RCC_MC_APB1ENSETR_USART3EN, + .rx_pin = GPIO_PIN(PORT_B, 12), + .tx_pin = GPIO_PIN(PORT_B, 10), + .rx_af = GPIO_AF8, + .tx_af = GPIO_AF7, + .bus = APB1, + .irqn = USART3_IRQn, + .type = STM32_USART, +#ifdef UART_USE_DMA + .dma_stream = 4, + .dma_chan = 4, +#endif +#if IS_USED(MODULE_STM32MP1_ENG_MODE) + .clk_src = RCC_UART35CKSELR_UART35SRC_4, /* HSE clock source */ +#else + .clk_src = RCC_UART35CKSELR_UART35SRC_2, /* HSI clock source */ +#endif + }, +}; + +#define UART_0_ISR (isr_usart3) +#define UART_0_DMA_ISR (isr_dma1_stream4) + +#define UART_NUMOF ARRAY_SIZE(uart_config) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */ diff --git a/cpu/stm32/Kconfig b/cpu/stm32/Kconfig index 9a55d4f808..114529daae 100644 --- a/cpu/stm32/Kconfig +++ b/cpu/stm32/Kconfig @@ -8,14 +8,12 @@ config CPU_STM32 bool select HAS_CPU_STM32 - select HAS_BOOTLOADER_STM32 select HAS_PERIPH_CPUID select HAS_PERIPH_GPIO select HAS_PERIPH_GPIO_IRQ select HAS_PERIPH_TIMER_PERIODIC select HAS_PERIPH_UART_MODECFG select HAS_PERIPH_UART_NONBLOCKING - select HAS_PERIPH_WDT # Common CPU symbol config CPU diff --git a/cpu/stm32/Makefile.features b/cpu/stm32/Makefile.features index 235d140231..6e3c46ad99 100644 --- a/cpu/stm32/Makefile.features +++ b/cpu/stm32/Makefile.features @@ -1,13 +1,15 @@ include $(RIOTCPU)/stm32/stm32_info.mk -FEATURES_PROVIDED += bootloader_stm32 +ifneq (mp1,$(CPU_FAM)) + FEATURES_PROVIDED += bootloader_stm32 + FEATURES_PROVIDED += periph_wdt +endif FEATURES_PROVIDED += cpu_stm32$(CPU_FAM) FEATURES_PROVIDED += periph_cpuid FEATURES_PROVIDED += periph_gpio periph_gpio_irq FEATURES_PROVIDED += periph_timer_periodic FEATURES_PROVIDED += periph_uart_modecfg FEATURES_PROVIDED += periph_uart_nonblocking -FEATURES_PROVIDED += periph_wdt ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 wb)) FEATURES_PROVIDED += periph_flashpage @@ -31,7 +33,7 @@ ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l0 l4 l5 wb)) endif endif -ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l1 l4)) +ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l1 l4 mp1)) FEATURES_PROVIDED += cortexm_mpu endif diff --git a/cpu/stm32/Makefile.include b/cpu/stm32/Makefile.include index 82ff9b9cef..723769de7c 100644 --- a/cpu/stm32/Makefile.include +++ b/cpu/stm32/Makefile.include @@ -55,9 +55,11 @@ $(call target-export-variables,$(VECTORS_O),CPU_LINE) # which are only used for STM32 system includes and not of interest for RIOT. CFLAGS += -D__SYSTEM_STM32$(call uppercase,$(CPU_FAM))XX_H -STM32CMSIS_INCLUDE_DIR = $(RIOTCPU)/stm32/include/vendor/cmsis/$(CPU_FAM)/Include -STM32FAM_INCLUDE_FILE = $(STM32CMSIS_INCLUDE_DIR)/stm32$(CPU_FAM)xx.h -INCLUDES += -I$(STM32CMSIS_INCLUDE_DIR) +ifeq (,$(filter STM32MP157Cxx,$(CPU_LINE))) + STM32CMSIS_INCLUDE_DIR = $(RIOTCPU)/stm32/include/vendor/cmsis/$(CPU_FAM)/Include + STM32FAM_INCLUDE_FILE = $(STM32CMSIS_INCLUDE_DIR)/stm32$(CPU_FAM)xx.h + INCLUDES += -I$(STM32CMSIS_INCLUDE_DIR) +endif # Fetch all CMSIS headers using the package mechanism. This rule is called all # the time to ensure it's correctly updated when versions in the packages are @@ -70,19 +72,19 @@ $(STM32FAM_INCLUDE_FILE): FORCE $(VECTORS_FILE): $(STM32FAM_INCLUDE_FILE) $(Q)$(RIOTBASE)/cpu/stm32/dist/irqs/gen_vectors.py $(CPU_LINE) -ifneq (STM32F030x4,$(CPU_LINE)) - # IRQs of STM32F030x4 family are not available in the CMSIS package so they - # are hardcoded in RIOTs codebase. +ifeq (,$(filter STM32MP157Cxx STM32F030x4,$(CPU_LINE))) + # IRQs of STM32F030x4 and STM32MP157Cxx lines are not available in the CMSIS + # package so they are hardcoded in RIOTs codebase. # For other lines, the IRQs are automatically generated once from the whole # list of CMSIS headers available in a given family STM32IRQS_INCLUDE_FILE = $(RIOTCPU)/stm32/include/irqs/$(CPU_FAM)/irqs.h BUILDDEPS += $(STM32IRQS_INCLUDE_FILE) +endif # The IRQ header for a given family requires the family headers to be fetched # before since it's generated from all CMSIS content of that family $(STM32IRQS_INCLUDE_FILE): $(STM32FAM_INCLUDE_FILE) $(Q)$(RIOTBASE)/cpu/stm32/dist/irqs/gen_irqs.py $(CPU_FAM) -endif # Include clock configuration directory INCLUDES += -I$(RIOTCPU)/stm32/include/clk diff --git a/cpu/stm32/cpu_common.c b/cpu/stm32/cpu_common.c index 8820f2cdf3..a42207d6ca 100644 --- a/cpu/stm32/cpu_common.c +++ b/cpu/stm32/cpu_common.c @@ -72,13 +72,19 @@ void periph_clk_en(bus_t bus, uint32_t mask) RCC->APB1ENR1 |= mask; #elif defined(CPU_FAM_STM32G0) RCC->APBENR1 |= mask; +#elif defined(CPU_FAM_STM32MP1) + RCC->MC_APB1ENSETR |= mask; #else RCC->APB1ENR |= mask; #endif break; #if !defined(CPU_FAM_STM32G0) case APB2: +#if defined(CPU_FAM_STM32MP1) + RCC->MC_APB2ENSETR |= mask; +#else RCC->APB2ENR |= mask; +#endif break; #endif #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ @@ -119,6 +125,11 @@ void periph_clk_en(bus_t bus, uint32_t mask) RCC->AHB3ENR |= mask; break; #endif +#endif +#if defined(CPU_FAM_STM32MP1) + case AHB4: + RCC->MC_AHB4ENSETR |= mask; + break; #endif default: DEBUG("unsupported bus %d\n", (int)bus); @@ -137,13 +148,20 @@ void periph_clk_dis(bus_t bus, uint32_t mask) RCC->APB1ENR1 &= ~(mask); #elif defined(CPU_FAM_STM32G0) RCC->APBENR1 &= ~(mask); +#elif defined(CPU_FAM_STM32MP1) + /* Write 1 to clear */ + RCC->MC_APB1ENCLRR |= mask; #else RCC->APB1ENR &= ~(mask); #endif break; #if !defined(CPU_FAM_STM32G0) case APB2: +#if defined(CPU_FAM_STM32MP1) + RCC->MC_APB2ENCLRR |= mask; +#else RCC->APB2ENR &= ~(mask); +#endif break; #endif #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ diff --git a/cpu/stm32/cpu_init.c b/cpu/stm32/cpu_init.c index 8a70680eff..7e1ae66947 100644 --- a/cpu/stm32/cpu_init.c +++ b/cpu/stm32/cpu_init.c @@ -44,7 +44,7 @@ #define BIT_APB_PWREN RCC_APB1ENR1_PWREN #elif defined (CPU_FAM_STM32G0) #define BIT_APB_PWREN RCC_APBENR1_PWREN -#else +#elif !defined(CPU_FAM_STM32MP1) #define BIT_APB_PWREN RCC_APB1ENR_PWREN #endif @@ -152,7 +152,7 @@ void cpu_init(void) /* initialize the Cortex-M core */ cortexm_init(); /* enable PWR module */ -#ifndef CPU_FAM_STM32WB +#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) periph_clk_en(APB1, BIT_APB_PWREN); #endif #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \ @@ -161,8 +161,10 @@ void cpu_init(void) defined(CPU_FAM_STM32L1) _gpio_init_ain(); #endif +#if !defined(CPU_FAM_STM32MP1) || IS_USED(MODULE_STM32MP1_ENG_MODE) /* initialize the system clock as configured in the periph_conf.h */ stmclk_init_sysclk(); +#endif #ifdef MODULE_PERIPH_DMA /* initialize DMA streams */ dma_init(); diff --git a/cpu/stm32/dist/clk_conf/clk_conf.c b/cpu/stm32/dist/clk_conf/clk_conf.c index 37455bcb9a..f21da30647 100644 --- a/cpu/stm32/dist/clk_conf/clk_conf.c +++ b/cpu/stm32/dist/clk_conf/clk_conf.c @@ -188,6 +188,10 @@ static void usage(char **argv) int main(int argc, char **argv) { + int char_offset = 0; + const unsigned int* stm32_model_p = stm32_f_model; + const clk_cfg_t* stm32_clk_cfg_p = stm32_f_clk_cfg; + int model_max = MODEL_F_MAX; if (argc < 2) { usage(argv); return 1; @@ -199,23 +203,36 @@ int main(int argc, char **argv) || !isdigit(argv[1][8]) || ((argv[1][5] != 'f') && (argv[1][5] != 'F') /* && (argv[1][5] != 'l') && (argv[1][5] != 'L') */)) { - fprintf(stderr, "Invalid model : %s\n", argv[1]); - return 1; + if (strlen(argv[1]) < 10 + || !isdigit(argv[1][7]) + || !isdigit(argv[1][8]) + || !isdigit(argv[1][9]) + || ((argv[1][5] != 'm') && (argv[1][5] != 'M')) + || ((argv[1][6] != 'p') && (argv[1][5] != 'p')) + ) { + fprintf(stderr, "Invalid model : %s\n", argv[1]); + return 1; + } + + char_offset = 1; + stm32_model_p = stm32_model_mp; + stm32_clk_cfg_p = stm32_mp_clk_cfg; + model_max = MODEL_MP_MAX; } - int model = atoi(argv[1] + 6); + int model = atoi(argv[1] + 6 + char_offset); int i; - for (i = 0; i < MODEL_MAX; i++) { - if (stm32_model[i] == model) { + for (i = 0; i < model_max; i++) { + if (stm32_model_p[i] == model) { break; } } - if (i == MODEL_MAX) { + if (i == model_max) { fprintf(stderr, "Unsupported CPU model %s\n", argv[1]); return 1; } - const clk_cfg_t *cfg = &stm32_clk_cfg[i]; + const clk_cfg_t *cfg = &stm32_clk_cfg_p[i]; /* print help for given cpu */ if (argc < 5) { @@ -399,6 +416,7 @@ int main(int argc, char **argv) /* APB prescalers */ unsigned apb1_pre; unsigned apb2_pre; + unsigned apb3_pre; for (apb1_pre = 1; apb1_pre <= 16; apb1_pre <<= 1) { if (coreclock / apb1_pre <= cfg->max_apb1) { @@ -412,6 +430,13 @@ int main(int argc, char **argv) } } } + if (cfg->family == STM32MP1) { + for (apb3_pre = 1; apb3_pre <= 16; apb3_pre <<= 1) { + if (coreclock / apb3_pre <= cfg->max_apb3) { + break; + } + } + } /* Print constants */ @@ -435,14 +460,32 @@ int main(int argc, char **argv) " * 1: external crystal available (always 32.768kHz) */\n" "#define CLOCK_LSE (%uU)\n", is_lse); printf("/* peripheral clock setup */\n"); + + if (cfg->family != STM32MP1) { printf("#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1\n" "#define CLOCK_AHB (CLOCK_CORECLOCK / 1)\n"); + } if (cfg->family == STM32F0) { printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV%u /* max %uMHz */\n" "#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n", apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre); printf("#define CLOCK_APB2 (CLOCK_APB1)\n"); } + else if (cfg->family == STM32MP1) { + /* TODO: Set to 1 by default, conf_clk is not able to handle this parameter */ + printf("#define CLOCK_MCU_DIV RCC_MCUDIVR_MCUDIV_1 /* max %uMHz */\n" + "#define CLOCK_MCU (CLOCK_CORECLOCK / 1)\n", + cfg->max_coreclock / 1000000U); + printf("#define CLOCK_APB1_DIV RCC_APB1DIVR_APB1DIV_%u /* max %uMHz */\n" + "#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n", + apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre); + printf("#define CLOCK_APB2_DIV RCC_APB2DIVR_APB2DIV_%u /* max %uMHz */\n" + "#define CLOCK_APB2 (CLOCK_CORECLOCK / %u)\n", + apb2_pre, cfg->max_apb2 / 1000000U, apb2_pre); + printf("#define CLOCK_APB3_DIV RCC_APB3DIVR_APB3DIV_%u /* max %uMHz */\n" + "#define CLOCK_APB3 (CLOCK_CORECLOCK / %u)\n", + apb3_pre, cfg->max_apb3 / 1000000U, apb3_pre); + } else { printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV%u /* max %uMHz */\n" "#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n", diff --git a/cpu/stm32/dist/clk_conf/clk_conf.h b/cpu/stm32/dist/clk_conf/clk_conf.h index 06b37b9214..844419dd8a 100644 --- a/cpu/stm32/dist/clk_conf/clk_conf.h +++ b/cpu/stm32/dist/clk_conf/clk_conf.h @@ -35,6 +35,7 @@ enum fam { STM32F3, STM32F4, STM32F7, + STM32MP1, FAM_MAX, }; /** @} */ @@ -106,8 +107,15 @@ enum { STM32F777, STM32F779, - MODEL_MAX, + MODEL_F_MAX, }; + +enum { + STM32MP157, + + MODEL_MP_MAX, +}; + /** @} */ /** @@ -167,6 +175,7 @@ typedef struct { unsigned max_coreclock; /**< Max coreclock */ unsigned max_apb1; /**< Max APB1 clock */ unsigned max_apb2; /**< Max APB2 clock */ + unsigned max_apb3; /**< Max APB3 clock */ unsigned hsi; /**< HSI frequency */ @@ -200,7 +209,7 @@ typedef struct { #define STM32F0(x) [STM32F0##x] = x /** List of supported models */ -static const unsigned stm32_model[] = { +static const unsigned stm32_f_model[] = { STM32F0(30), STM32F0(70), STM32F0(31), @@ -264,6 +273,13 @@ static const unsigned stm32_model[] = { STM32F(779), }; +#define STM32MP(x) [STM32MP##x] = x + +/** List of supported models */ +static const unsigned stm32_model_mp[] = { + STM32MP(157), +}; + /** STM32F2xx / STM32F401 PLL config */ #define stm32f2_4_192_pll_cfg { \ .min_vco_input = 1000000U, \ @@ -304,10 +320,30 @@ static const unsigned stm32_model[] = { .inc_q = 1, \ } +/** STM32MP1 PLL config */ +#define stm32mp1_pll_cfg { \ + .min_vco_input = 4000000U, \ + .max_vco_input = 16000000U, \ + .min_vco_output = 400000000U, \ + .max_vco_output = 800000000U, \ + .min_n = 25, \ + .max_n = 100, \ + .inc_n = 1, \ + .min_m = 2, \ + .max_m = 63, \ + .inc_m = 1, \ + .min_p = 2, \ + .max_p = 127, \ + .inc_p = 1, \ + .min_q = 2, \ + .max_q = 127, \ + .inc_q = 1, \ +} + /** * @brief Clock config for supported cpu */ -static const clk_cfg_t stm32_clk_cfg[] = { +static const clk_cfg_t stm32_f_clk_cfg[] = { [STM32F030 ... STM32F098] = { .family = STM32F0, .max_coreclock = 48000000U, @@ -595,6 +631,28 @@ static const clk_cfg_t stm32_clk_cfg[] = { }, }; + /** + * @brief Clock config for supported cpu + */ +static const clk_cfg_t stm32_mp_clk_cfg[] = { + [STM32MP157] = { + .family = STM32MP1, + .max_coreclock = 209000000U, + .max_apb1 = 104500000U, + .max_apb2 = 104500000U, + .max_apb3 = 104500000U, + .hsi = 64000000U, + .pll = stm32mp1_pll_cfg, + .has_pll_i2s = false, + .has_pll_sai = false, + .has_pll_i2s_m = false, + .has_pll_sai_m = false, + .has_pll_i2s_alt_input = false, + .has_alt_48MHz = 0, + .need_48MHz = true, + }, +}; + #ifdef __cplusplus } #endif diff --git a/cpu/stm32/dist/irqs/gen_vectors.py b/cpu/stm32/dist/irqs/gen_vectors.py index 9de7a0d5bc..537920916a 100755 --- a/cpu/stm32/dist/irqs/gen_vectors.py +++ b/cpu/stm32/dist/irqs/gen_vectors.py @@ -54,6 +54,10 @@ def parse_cmsis(cpu_line): # STM32F030x4 is provided in the RIOT codebase in a different location cpu_line_cmsis = os.path.join( STM32_VENDOR_DIR, "{}.h".format(cpu_line.lower())) + elif cpu_line.startswith("STM32MP1"): + # STM32MP157Cxx is provided in the RIOT codebase in a different location + cpu_line_cmsis = os.path.join( + STM32_VENDOR_DIR, "{}_cm4.h".format(cpu_line.lower())) else: cpu_line_cmsis = STM32_CMSIS_FILE.format( cpu_fam.lower(), cpu_line.lower()) @@ -70,7 +74,7 @@ def parse_cmsis(cpu_line): # skip line that contains non unicode characters continue # start filling lines after interrupt Doxygen comment - if line.startswith("typedef enum"): + if "typedef enum" in line: use_line = True # use a regexp to get the available IRQs diff --git a/cpu/stm32/include/clk/clk_conf.h b/cpu/stm32/include/clk/clk_conf.h index 797f00284f..2714dee16a 100644 --- a/cpu/stm32/include/clk/clk_conf.h +++ b/cpu/stm32/include/clk/clk_conf.h @@ -38,6 +38,8 @@ #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \ defined(CPU_FAM_STM32WB) #include "l4l5wb/cfg_clock_default.h" +#elif defined(CPU_FAM_STM32MP1) +#include "mp1/cfg_clock_default.h" #else #error "No clock configuration available" #endif diff --git a/cpu/stm32/include/clk/mp1/cfg_clock_common.h b/cpu/stm32/include/clk/mp1/cfg_clock_common.h new file mode 100644 index 0000000000..68ed904e7d --- /dev/null +++ b/cpu/stm32/include/clk/mp1/cfg_clock_common.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Base STM32MP1 clock configuration + * + * @author Gilles DOFFE + */ + +#ifndef CLK_MP1_CFG_CLOCK_COMMON_H +#define CLK_MP1_CFG_CLOCK_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock common configuration + * @{ + */ +/* Select the desired system clock source between PLL, HSE or HSI */ +#ifndef CONFIG_USE_CLOCK_PLL +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) +#define CONFIG_USE_CLOCK_PLL 0 +#else +#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */ +#endif +#endif /* CONFIG_USE_CLOCK_PLL */ + +#ifndef CONFIG_USE_CLOCK_HSE +#define CONFIG_USE_CLOCK_HSE 0 +#endif /* CONFIG_USE_CLOCK_HSE */ + +#ifndef CONFIG_USE_CLOCK_HSI +#define CONFIG_USE_CLOCK_HSI 0 +#endif /* CONFIG_USE_CLOCK_HSI */ + +#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) +#error "Cannot use PLL as clock source with other clock configurations" +#endif + +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) +#error "Cannot use HSE as clock source with other clock configurations" +#endif + +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) +#error "Cannot use HSI as clock source with other clock configurations" +#endif + +#ifndef CONFIG_BOARD_HAS_HSE +#define CONFIG_BOARD_HAS_HSE 0 +#endif + +#ifndef CLOCK_HSE +#define CLOCK_HSE MHZ(24) +#endif + +#define CLOCK_HSI MHZ(64) + +#ifdef __cplusplus +} +#endif + +#endif /* CLK_MP1_CFG_CLOCK_COMMON_H */ +/** @} */ diff --git a/cpu/stm32/include/clk/mp1/cfg_clock_default.h b/cpu/stm32/include/clk/mp1/cfg_clock_default.h new file mode 100644 index 0000000000..aa77185731 --- /dev/null +++ b/cpu/stm32/include/clk/mp1/cfg_clock_default.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + + +/** + * @ingroup cpu_stm32 + * @{ + * + * @file + * @brief Main header for STM32MP1 clock configuration + * + * @author Gilles DOFFE +*/ + +#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_H +#define CLK_MP1_CFG_CLOCK_DEFAULT_H + +#if defined(CPU_LINE_STM32MP157Cxx) +#include "mp1/cfg_clock_default_208.h" +#else +#error "No clock configuration available for this family" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* CLK_MP1_CFG_CLOCK_DEFAULT_H */ +/** @} */ diff --git a/cpu/stm32/include/clk/mp1/cfg_clock_default_208.h b/cpu/stm32/include/clk/mp1/cfg_clock_default_208.h new file mode 100644 index 0000000000..4e52f5ff5f --- /dev/null +++ b/cpu/stm32/include/clk/mp1/cfg_clock_default_208.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Default STM32MP1 clock configuration for 208MHz boards + * + * @author Gilles DOFFE + */ + +#ifndef CLK_MP1_CFG_CLOCK_DEFAULT_208_H +#define CLK_MP1_CFG_CLOCK_DEFAULT_208_H + +#include "mp1/cfg_clock_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock PLL settings (208MHz) + * @{ + */ +/* The following parameters configure a 208MHz system clock with HSE (24MHz) + * or HSI (16MHz) as PLL input clock */ +#ifndef CONFIG_CLOCK_PLL_M +#define CONFIG_CLOCK_PLL_M (2) +#endif +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(24)) +#ifndef CONFIG_CLOCK_PLL_N +#define CONFIG_CLOCK_PLL_N (52) +#endif +#else /* HSI */ +#ifndef CONFIG_CLOCK_PLL_N +#define CONFIG_CLOCK_PLL_N (78) +#endif +#endif +#ifndef CONFIG_CLOCK_PLL_P +#define CONFIG_CLOCK_PLL_P (3) +#endif +#ifndef CONFIG_CLOCK_PLL_Q +#define CONFIG_CLOCK_PLL_Q (13) +#endif +#ifndef CONFIG_CLOCK_PLL_R +#define CONFIG_CLOCK_PLL_R (3) +#endif +/** @} */ + +/** + * @name Clock bus settings (MCU, APB1, APB2 and APB3) + */ +#ifndef CONFIG_CLOCK_MCU_DIV +#define CONFIG_CLOCK_MCU_DIV (1) /* max 208MHz */ +#endif +#ifndef CONFIG_CLOCK_APB1_DIV +#define CONFIG_CLOCK_APB1_DIV (2) /* max 104MHz */ +#endif +#ifndef CONFIG_CLOCK_APB2_DIV +#define CONFIG_CLOCK_APB2_DIV (2) /* max 104MHz */ +#endif +#ifndef CONFIG_CLOCK_APB3_DIV +#define CONFIG_CLOCK_APB3_DIV (2) /* max 104MHz */ +#endif +/** @} */ + +#ifdef __cplusplus +} +#endif + +#include "mp1/cfg_clock_values.h" + +#if CLOCK_CORECLOCK > MHZ(208) +#error "SYSCLK cannot exceed 208MHz" +#endif + +#endif /* CLK_MP1_CFG_CLOCK_DEFAULT_208_H */ +/** @} */ diff --git a/cpu/stm32/include/clk/mp1/cfg_clock_values.h b/cpu/stm32/include/clk/mp1/cfg_clock_values.h new file mode 100644 index 0000000000..d58d7cc7f4 --- /dev/null +++ b/cpu/stm32/include/clk/mp1/cfg_clock_values.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief STM32MP1 clock values definitions + * + * @author Gilles DOFFE + */ + +#ifndef CLK_MP1_CFG_CLOCK_VALUES_H +#define CLK_MP1_CFG_CLOCK_VALUES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock values + * @{ + */ +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#define CLOCK_PLL_SRC (CLOCK_HSE) +#else /* CLOCK_HSI */ +#define CLOCK_PLL_SRC (CLOCK_HSI) +#endif + +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) +#define CLOCK_CORECLOCK (CLOCK_HSI) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) +#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#error "The board doesn't provide an HSE oscillator" +#endif +#define CLOCK_CORECLOCK (CLOCK_HSE) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) +#define CLOCK_CORECLOCK (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \ + * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_P) +#endif /* CONFIG_USE_CLOCK_PLL */ + +#define CLOCK_PLLQ (((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) \ + * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q) + +#define CLOCK_APB1 (CLOCK_CORECLOCK \ + / CONFIG_CLOCK_APB1_DIV) +#define CLOCK_APB2 (CLOCK_CORECLOCK \ + / CONFIG_CLOCK_APB2_DIV) +/** @} */ + + +#ifdef __cplusplus +} +#endif + +#endif /* CLK_MP1_CFG_CLOCK_VALUES_H */ +/** @} */ diff --git a/cpu/stm32/include/cpu_conf.h b/cpu/stm32/include/cpu_conf.h index 8487ef8284..dcdc139154 100644 --- a/cpu/stm32/include/cpu_conf.h +++ b/cpu/stm32/include/cpu_conf.h @@ -25,6 +25,8 @@ #if defined(CPU_LINE_STM32F030x4) #include "vendor/stm32f030x4.h" +#elif defined(CPU_LINE_STM32MP157Cxx) +#include "vendor/stm32mp157cxx_cm4.h" #elif CPU_FAM_STM32F0 #include "stm32f0xx.h" #include "irqs/f0/irqs.h" @@ -77,11 +79,16 @@ extern "C" { * @{ */ #define CPU_DEFAULT_IRQ_PRIO (1U) +/* STM32MP1 family has no flah */ +#if !defined(CPU_FAM_STM32MP1) #define CPU_FLASH_BASE FLASH_BASE +#endif /* CPU_IRQ_NUMOF cannot be determined automatically from cmsis header */ #if defined(CPU_LINE_STM32F030x4) #define CPU_IRQ_NUMOF (28U) +#elif defined(CPU_MODEL_STM32MP157CAC) +#define CPU_IRQ_NUMOF (150U) #endif /** @} */ diff --git a/cpu/stm32/include/periph_cpu.h b/cpu/stm32/include/periph_cpu.h index 36ef560477..817ddfdd44 100644 --- a/cpu/stm32/include/periph_cpu.h +++ b/cpu/stm32/include/periph_cpu.h @@ -67,7 +67,8 @@ extern "C" { #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \ defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \ defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \ - defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) + defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \ + defined(CPU_FAM_STM32MP1) #define CLOCK_LSI (32000U) #else #error "error: LSI clock speed not defined for your target CPU" @@ -190,10 +191,14 @@ typedef enum { AHB1, /**< AHB1 bus */ AHB2, /**< AHB2 bus */ AHB3, /**< AHB3 bus */ +#elif defined(CPU_FAM_STM32MP1) + AHB1, /**< AHB1 bus */ + AHB2, /**< AHB2 bus */ + AHB3, /**< AHB3 bus */ #else #warning "unsupported stm32XX family" #endif -#if defined(CPU_FAM_STM32WB) +#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32MP1) AHB4, /**< AHB4 bus */ #endif } bus_t; @@ -216,7 +221,11 @@ typedef uint32_t gpio_t; /** * @brief Define a CPU specific GPIO pin generator macro */ +#if defined(CPU_FAM_STM32MP1) +#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 12)) | y) +#else #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y) +#endif /** * @brief Available GPIO ports @@ -283,7 +292,8 @@ enum { #define PERIPH_I2C_NEED_WRITE_REG #define PERIPH_I2C_NEED_READ_REGS #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \ - defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F4) + defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F4) || \ + defined(CPU_FAM_STM32MP1) #define PERIPH_I2C_NEED_WRITE_REGS #endif /** @} */ @@ -674,7 +684,7 @@ typedef struct { #endif #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \ defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \ - defined(CPU_FAM_STM32L5) + defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32MP1) uart_type_t type; /**< hardware module type (USART or LPUART) */ uint32_t clk_src; /**< clock source used for UART */ #endif @@ -717,7 +727,8 @@ typedef struct { #define HAVE_I2C_SPEED_T typedef enum { #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \ - defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1) + defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1) || \ + defined(CPU_FAM_STM32MP1) I2C_SPEED_LOW, /**< low speed mode: ~10kit/s */ #endif I2C_SPEED_NORMAL, /**< normal mode: ~100kbit/s */ @@ -751,7 +762,8 @@ typedef struct { uint32_t rcc_sw_mask; /**< bit to switch I2C clock */ #endif #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \ - defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1) + defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1) || \ + defined(CPU_FAM_STM32MP1) uint32_t clk; /**< bus frequency as defined in board config */ #endif uint8_t irqn; /**< I2C event interrupt number */ diff --git a/cpu/stm32/include/vendor/stm32mp157cxx_cm4.h b/cpu/stm32/include/vendor/stm32mp157cxx_cm4.h new file mode 100644 index 0000000000..dc809520c5 --- /dev/null +++ b/cpu/stm32/include/vendor/stm32mp157cxx_cm4.h @@ -0,0 +1,32050 @@ +/** + ****************************************************************************** + * @file stm32mp157cxx_cm4.h + * @author MCD Application Team + * @brief CMSIS stm32mp157cxx_cm4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32mp157cxx_cm4 + * @{ + */ + +#ifndef __STM32MP157Cxx_CM4_H +#define __STM32MP157Cxx_CM4_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Bit position definition inside a 32 bits registers + */ +#define B(x) \ + ((uint32_t) 1 << x) +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32MP1XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + typedef enum IRQn + { + /****** Cortex-M Processor Exceptions Numbers *******************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers ************************************************************************/ + WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */ + TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */ + RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ + RESERVED_4 = 4, /*!< RESERVED interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */ + RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */ + EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */ + ETH1_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */ + EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */ + EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */ + EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */ + EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */ + USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */ + EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */ + EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + CRYP1_IRQn = 79, /*!< CRYP crypto global interrupt */ + HASH1_IRQn = 80, /*!< Hash global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + ADC2_IRQn = 90, /*!< ADC2 global Interrupts */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_IRQn = 98, /*!< USB On The Go global interrupt */ + RESERVED_99 = 99, /*!< RESERVED interrupt */ + IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */ + DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */ + IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */ + IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */ + CRYP2_IRQn = 105, /*!< CRYP2 crypto global interrupt */ + HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */ + I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */ + I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */ + GPU_IRQn = 109, /*!< GPU global Interrupt */ + DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */ + DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */ + DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */ + DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */ + SAI3_IRQn = 114, /*!< SAI3 global Interrupt */ + DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global Interrupt */ + TIM12_IRQn = 119, /*!< TIM12 global Interrupt */ + MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */ + EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */ + MDMA_IRQn = 122, /*!< MDMA global Interrupt */ + DSI_IRQn = 123, /*!< DSI global Interrupt */ + SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */ + HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */ + DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */ + EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */ + nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */ + nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */ + TIM13_IRQn = 130, /*!< TIM13 global interrupt */ + TIM14_IRQn = 131, /*!< TIM14 global interrupt */ + DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */ + RNG1_IRQn = 133, /*!< RNG1 interrupt */ + RNG2_IRQn = 134, /*!< RNG2 interrupt */ + I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */ + I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */ + SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */ + LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */ + LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */ + LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ + LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ + ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */ + RESERVED_143 = 143, /*!< RESERVED interrupt */ + MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */ + RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */ + SAI4_IRQn = 146, /*!< SAI4 global interrupt */ + DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */ + RESERVED_148 = 148, /*!< RESERVED interrupt */ + WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ + MAX_IRQ_n + } IRQn_Type; + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +#define SDC /*!< Step Down Converter feature */ + +/** + * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_stm32mp1xx.h" + + +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + uint32_t RESERVED10; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */ + uint32_t RESERVED2; /*!< Reserved, 0x00C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */ + uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */ + __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */ + __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ + __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ +} DFSDM_Channel_TypeDef; + + +/** + * @brief DFSDM registers + */ +typedef struct +{ + uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */ + __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */ + __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */ +} DFSDM_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */ + __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */ + __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */ + __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */ + __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */ + uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */ + __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ + __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */ + __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */ + uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */ + __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */ + +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, 0x004 */ +// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */ + __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */ +// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */ + uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */ + __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */ + __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED6; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED10; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */ + uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */ + __IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */ + __IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */ + __IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */ + __IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */ + __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */ + __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */ + __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */ + __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */ + __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */ + uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */ + __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */ + __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */ + __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */ + __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */ + uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */ + __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */ + uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */ + __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */ + __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */ + __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */ + __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */ + __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */ + __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */ + __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */ + __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */ + __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */ + __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */ + uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */ + __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */ + __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */ + __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */ + __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */ + uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */ + __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */ + uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */ + __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */ + __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */ + uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */ + __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */ + __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */ + uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */ + __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */ + __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */ + uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */ + __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */ + __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */ + __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */ + __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */ + __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */ + __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */ + __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */ + __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */ + uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */ + __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */ + __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */ + __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */ + __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */ + __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */ + uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */ + __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */ + __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */ + uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */ + __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */ + uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */ + __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */ + __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */ + uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */ + __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */ + uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */ + __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */ + __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */ + __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */ + __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */ + uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */ + __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */ + __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */ + uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */ + __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */ + __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */ + __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */ + __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */ + uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */ + __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */ + __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */ + uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */ + __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */ + __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */ + __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */ + __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */ + uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */ + __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */ + uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */ + __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */ + __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */ + __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */ + __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */ + __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */ + __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */ + __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */ + uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */ + __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */ + __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */ + __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */ + uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */ + __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */ + uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */ + __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */ + __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */ + __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */ + __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */ + __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */ + __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */ + uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */ + __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */ + uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */ + __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */ + __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */ + __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */ + __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */ + uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */ + __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */ + __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */ + __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */ + __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */ + __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */ + uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */ + __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */ + uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */ + __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */ + uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */ + __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */ + __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */ + __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */ + uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */ + __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */ + uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */ + __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */ + __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */ + __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */ + __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */ + __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */ + __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */ + __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */ + __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */ + uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */ + __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */ + __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */ + __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */ + __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */ + __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */ + __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */ + uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */ + __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */ + __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */ + __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */ + __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */ + __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */ + uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */ + __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */ + __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */ + __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */ + __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */ + uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */ + __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */ + __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */ + __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */ + uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */ + __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */ + __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */ + __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */ + uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */ + __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */ + uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */ + __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */ + __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */ + uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */ + __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */ + __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */ + __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */ + __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */ + __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */ + __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */ + uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */ + __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */ + uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */ + __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */ + uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */ + __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */ + uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */ + __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */ + __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */ + uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */ + __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */ + uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */ + __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */ + __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */ + uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */ + __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */ + uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */ + __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */ + uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */ + __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */ + uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */ + __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */ + uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */ + __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */ + uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */ + __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */ + uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */ + __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */ + uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */ + __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */ + uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */ + __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */ +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */ + __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */ + __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */ + __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ + __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ + __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ + __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */ + __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */ + __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ + uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ + __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ + __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ + __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ + __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ + __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ + __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ + __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ + __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ + __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ + __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */ + __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */ + __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */ + uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */ + __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */ + __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */ + __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */ + __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */ + __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */ + +}EXTI_TypeDef; + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ + uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */ +}EXTI_Core_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */ + __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */ + uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */ + __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */ + __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */ + __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */ + uint32_t RESERVED1; /*!< Reserved, 0x25C */ + __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */ + __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */ + __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */ + __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */ + __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */ + __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */ + __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */ + __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */ + __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */ + uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */ + __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */ + __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */ +} FMC_Bank3_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */ + __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */ + uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */ + __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */ + __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */ + __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */ + __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */ + __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */ + __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */ + __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */ + __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */ + __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */ + __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */ + __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */ +} GPIO_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ + __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ + __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ + __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ + __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ + __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ + __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ +} SYSCFG_TypeDef; + + +/** + * @briefVoltage reference buffer + */ +typedef struct +{ + __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */ + __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */ +} VREF_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */ + __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */ + uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */ + __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */ + __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + + +/** + * @brief DDRPHYC DDR Physical Interface Control + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ + __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ + __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ + __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ + __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ + uint32_t RESERVED0[24]; /*!< Reserved */ + __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ + __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ + __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ + __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ + __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ + __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ + __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ + __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ + uint32_t RESERVED1[8]; /*!< Reserved */ + __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ + __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ + __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ + __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ + __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ + __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ + __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ + __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ + __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ + __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ + __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ + __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ + __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ + __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ + __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ + __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ + __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ + uint32_t RESERVED2[13]; /*!< Reserved */ + __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ + uint32_t RESERVED3[12]; /*!< Reserved */ + __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ + uint32_t RESERVED4[10]; /*!< Reserved */ + __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ + uint32_t RESERVED5[10]; /*!< Reserved */ + __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ + uint32_t RESERVED6[10]; /*!< Reserved */ + __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ +}DDRPHYC_TypeDef; + + +/** + * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ + /* @TODO : TypeDef to be compleated */ +}DDRC_TypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control + */ +typedef struct +{ + __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */ + uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */ + __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */ + uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/ + __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */ +}USBPHYC_GlobalTypeDef; + + +/** + * @brief USBPHYC USB HS PHY Control PHYx + */ +typedef struct +{ + uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */ + __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */ +}USBPHYC_InstanceTypeDef; + + +/** + * @brief TZC TrustZone Address Space Controller for DDR + */ +typedef struct +{ + __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */ + __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */ + __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */ + __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */ + uint8_t RESERVED0[0x100 - 0x10]; + __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */ + __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */ + __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */ + __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */ + __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */ + __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */ + /* @TODO : TypeDef to be compleated if needed*/ +}TZC_TypeDef; + + + +/** + * @brief TZPC TrustZone Protection Controller + */ +typedef struct +{ + __IO uint32_t TZMA0_SIZE; /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!VER) + +/******************************* TZPC VERSION ********************************/ +#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* FMC VERSION ********************************/ +#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SYSCFG VERSION ********************************/ +#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ETHERNET VERSION ********************************/ +#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) + + +/******************************* SYSCFG VERSION ********************************/ +#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* PWR VERSION ********************************/ +#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* RCC VERSION ********************************/ +#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* HDP VERSION ********************************/ +#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IPCC VERSION ********************************/ +#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HSEM VERSION ********************************/ +#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* GPIO VERSION ********************************/ +#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMA VERSION ********************************/ +#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DMAMUX VERSION ********************************/ +#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDMA VERSION ********************************/ +#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TAMP VERSION ********************************/ +#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RTC VERSION ********************************/ +#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SDMMC VERSION ********************************/ +#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* QUADSPI VERSION ********************************/ +#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CRC VERSION ********************************/ +#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* RNG VERSION ********************************/ +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* HASH VERSION ********************************/ +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* CRYP VERSION ********************************/ +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) + +/******************************* DCMI VERSION ********************************/ +#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* CEC VERSION ********************************/ +#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* LPTIM VERSION ********************************/ +#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* TIM VERSION ********************************/ +#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* IWDG VERSION ********************************/ +#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* WWDG VERSION ********************************/ +#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DFSDM VERSION ********************************/ +#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SAI VERSION ********************************/ +#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* MDIOS VERSION ********************************/ +#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* I2C VERSION ********************************/ +#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USART VERSION ********************************/ +#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPDIFRX VERSION ********************************/ +#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* SPI VERSION ********************************/ +#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* ADC VERSION ********************************/ +#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DLYB VERSION ********************************/ +#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DAC VERSION ********************************/ +#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) + +/******************************* DSI VERSION ********************************/ +#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* USBPHYC VERSION ********************************/ +#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR) + +/******************************* DEVICE VERSION ********************************/ +#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos) +#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000) + +/******************************* DEVICE ID ************************************/ +#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk)) + +/** + * @brief Check whether platform is engineering boot mode + * @param None + * @retval TRUE or FALSE + */ +#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2)) + + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32MP157Cxx_CM4_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32/include/vendor/system_stm32mp1xx.h b/cpu/stm32/include/vendor/system_stm32mp1xx.h new file mode 100644 index 0000000000..7d22efc319 --- /dev/null +++ b/cpu/stm32/include/vendor/system_stm32mp1xx.h @@ -0,0 +1,106 @@ +/** + ****************************************************************************** + * @file system_stm32mp1xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device System Source File for STM32MP1xx devices. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32mp1xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32MP1XX_H +#define __SYSTEM_STM32MP1XX_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/** @addtogroup STM32MP1xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32MP1xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Core1 Clock Frequency */ +extern uint32_t SystemCore1Clock; /*!< System Core1 Clock Frequency */ +extern uint32_t SystemCore2Clock; /*!< System Core2 Clock Frequency */ + +/** + * @} + */ + +/** @addtogroup STM32MP1xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32MP1xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32MP1xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32MP1XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32/kconfigs/f0/Kconfig b/cpu/stm32/kconfigs/f0/Kconfig index 05ee6e6d14..d0c1d49834 100644 --- a/cpu/stm32/kconfigs/f0/Kconfig +++ b/cpu/stm32/kconfigs/f0/Kconfig @@ -15,6 +15,9 @@ config CPU_FAM_F0 select HAS_CPU_STM32F0 select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE_PAGEWISE + select HAS_PERIPH_FLASHPAGE_RAW + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config HAS_CPU_STM32F0 bool diff --git a/cpu/stm32/kconfigs/f1/Kconfig b/cpu/stm32/kconfigs/f1/Kconfig index 66fd9f1dbd..3cd94fefc2 100644 --- a/cpu/stm32/kconfigs/f1/Kconfig +++ b/cpu/stm32/kconfigs/f1/Kconfig @@ -12,6 +12,9 @@ config CPU_FAM_F1 select HAS_CPU_STM32F1 select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE_PAGEWISE + select HAS_PERIPH_FLASHPAGE_RAW + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "f1" if CPU_FAM_F1 diff --git a/cpu/stm32/kconfigs/f2/Kconfig b/cpu/stm32/kconfigs/f2/Kconfig index 2ef5b4552d..f99960816f 100644 --- a/cpu/stm32/kconfigs/f2/Kconfig +++ b/cpu/stm32/kconfigs/f2/Kconfig @@ -12,6 +12,8 @@ config CPU_FAM_F2 select HAS_CPU_STM32F2 select HAS_CORTEXM_MPU select HAS_PERIPH_HWRNG + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "f2" if CPU_FAM_F2 diff --git a/cpu/stm32/kconfigs/f3/Kconfig b/cpu/stm32/kconfigs/f3/Kconfig index a3cdd4c810..5ee691fd6a 100644 --- a/cpu/stm32/kconfigs/f3/Kconfig +++ b/cpu/stm32/kconfigs/f3/Kconfig @@ -12,6 +12,9 @@ config CPU_FAM_F3 select HAS_CPU_STM32F3 select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE_PAGEWISE + select HAS_PERIPH_FLASHPAGE_RAW + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "f3" if CPU_FAM_F3 diff --git a/cpu/stm32/kconfigs/f4/Kconfig b/cpu/stm32/kconfigs/f4/Kconfig index aafa41059b..2dcabf9cf8 100644 --- a/cpu/stm32/kconfigs/f4/Kconfig +++ b/cpu/stm32/kconfigs/f4/Kconfig @@ -11,6 +11,8 @@ config CPU_FAM_F4 select CPU_CORE_CORTEX_M4F select HAS_CPU_STM32F4 select HAS_CORTEXM_MPU + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "f4" if CPU_FAM_F4 diff --git a/cpu/stm32/kconfigs/f7/Kconfig b/cpu/stm32/kconfigs/f7/Kconfig index e838f92789..9a1d4c8094 100644 --- a/cpu/stm32/kconfigs/f7/Kconfig +++ b/cpu/stm32/kconfigs/f7/Kconfig @@ -12,6 +12,8 @@ config CPU_FAM_F7 select HAS_CPU_STM32F7 select HAS_CORTEXM_MPU select HAS_PERIPH_HWRNG + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "f7" if CPU_FAM_F7 diff --git a/cpu/stm32/kconfigs/g0/Kconfig b/cpu/stm32/kconfigs/g0/Kconfig index f47bf05af7..b1157ce533 100644 --- a/cpu/stm32/kconfigs/g0/Kconfig +++ b/cpu/stm32/kconfigs/g0/Kconfig @@ -12,6 +12,9 @@ config CPU_FAM_G0 select HAS_CPU_STM32G0 select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE_PAGEWISE + select HAS_PERIPH_FLASHPAGE_RAW + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "g0" if CPU_FAM_G0 diff --git a/cpu/stm32/kconfigs/g4/Kconfig b/cpu/stm32/kconfigs/g4/Kconfig index 02851b1a22..f80a6f9746 100644 --- a/cpu/stm32/kconfigs/g4/Kconfig +++ b/cpu/stm32/kconfigs/g4/Kconfig @@ -14,6 +14,8 @@ config CPU_FAM_G4 select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE_PAGEWISE select HAS_PERIPH_HWRNG + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "g4" if CPU_FAM_G4 diff --git a/cpu/stm32/kconfigs/l0/Kconfig b/cpu/stm32/kconfigs/l0/Kconfig index 9f441b43c9..66fd11e584 100644 --- a/cpu/stm32/kconfigs/l0/Kconfig +++ b/cpu/stm32/kconfigs/l0/Kconfig @@ -13,6 +13,8 @@ config CPU_FAM_L0 select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE_PAGEWISE select HAS_PERIPH_EEPROM + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "l0" if CPU_FAM_L0 diff --git a/cpu/stm32/kconfigs/l1/Kconfig b/cpu/stm32/kconfigs/l1/Kconfig index a99ea64a25..15c0fc93c1 100644 --- a/cpu/stm32/kconfigs/l1/Kconfig +++ b/cpu/stm32/kconfigs/l1/Kconfig @@ -14,6 +14,8 @@ config CPU_FAM_L1 select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE_PAGEWISE select HAS_PERIPH_EEPROM + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "l1" if CPU_FAM_L1 diff --git a/cpu/stm32/kconfigs/l4/Kconfig b/cpu/stm32/kconfigs/l4/Kconfig index 5ddf175fd1..312d8ab210 100644 --- a/cpu/stm32/kconfigs/l4/Kconfig +++ b/cpu/stm32/kconfigs/l4/Kconfig @@ -14,6 +14,8 @@ config CPU_FAM_L4 select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE_PAGEWISE select HAS_PERIPH_HWRNG + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "l4" if CPU_FAM_L4 diff --git a/cpu/stm32/kconfigs/l5/Kconfig b/cpu/stm32/kconfigs/l5/Kconfig index ff8a4c294a..ddb6169bb4 100644 --- a/cpu/stm32/kconfigs/l5/Kconfig +++ b/cpu/stm32/kconfigs/l5/Kconfig @@ -13,6 +13,8 @@ config CPU_FAM_L5 select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE_PAGEWISE select HAS_PERIPH_HWRNG + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "l5" if CPU_FAM_L5 diff --git a/cpu/stm32/kconfigs/mp1/Kconfig b/cpu/stm32/kconfigs/mp1/Kconfig new file mode 100644 index 0000000000..8bd8cf6777 --- /dev/null +++ b/cpu/stm32/kconfigs/mp1/Kconfig @@ -0,0 +1,20 @@ +# Copyright (C) 2020 Savoir-faire Linux +# +# This file is subject to the terms and conditions of the GNU Lesser General +# Public License v2.1. See the file LICENSE in the top level directory for more +# details. + +config CPU_FAM_MP1 + bool + select CPU_STM32 + select CPU_CORE_CORTEX_M4F + select HAS_CORTEXM_MPU + select HAS_CPU_STM32MP1 + +config CPU_FAM + default "mp1" if CPU_FAM_MP1 + +config HAS_CPU_STM32MP1 + bool + help + Indicates that the cpu being used belongs to the 'stm32mp1' family. diff --git a/cpu/stm32/kconfigs/mp1/Kconfig.lines b/cpu/stm32/kconfigs/mp1/Kconfig.lines new file mode 100644 index 0000000000..174272ec4d --- /dev/null +++ b/cpu/stm32/kconfigs/mp1/Kconfig.lines @@ -0,0 +1,10 @@ +# Copyright (C) 2020 Savoir-faire Linux +# +# This file is subject to the terms and conditions of the GNU Lesser General +# Public License v2.1. See the file LICENSE in the top level directory for more +# details. + +# CPU lines +config CPU_LINE_STM32MP157CXX + bool + select CPU_FAM_MP1 diff --git a/cpu/stm32/kconfigs/mp1/Kconfig.models b/cpu/stm32/kconfigs/mp1/Kconfig.models new file mode 100644 index 0000000000..42b2902609 --- /dev/null +++ b/cpu/stm32/kconfigs/mp1/Kconfig.models @@ -0,0 +1,14 @@ +# Copyright (C) 2020 Savoir-faire Linux +# +# This file is subject to the terms and conditions of the GNU Lesser General +# Public License v2.1. See the file LICENSE in the top level directory for more +# details. + +# CPU models +config CPU_MODEL_STM32MP157CAC + bool + select CPU_LINE_STM32MP157CXX + +# Configure CPU model +config CPU_MODEL + default "stm32mp157cac" if CPU_MODEL_STM32MP157CAC diff --git a/cpu/stm32/kconfigs/wb/Kconfig b/cpu/stm32/kconfigs/wb/Kconfig index 76e922f318..679e301dad 100644 --- a/cpu/stm32/kconfigs/wb/Kconfig +++ b/cpu/stm32/kconfigs/wb/Kconfig @@ -13,6 +13,8 @@ config CPU_FAM_WB select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE_PAGEWISE select HAS_PERIPH_HWRNG + select HAS_PERIPH_WDT + select HAS_BOOTLOADER_STM32 config CPU_FAM default "wb" if CPU_FAM_WB diff --git a/cpu/stm32/periph/gpio_all.c b/cpu/stm32/periph/gpio_all.c index f95c83799d..79d1882428 100644 --- a/cpu/stm32/periph/gpio_all.c +++ b/cpu/stm32/periph/gpio_all.c @@ -26,7 +26,6 @@ * @} */ - #include "cpu.h" #include "bitarithm.h" #include "periph/gpio.h" @@ -51,6 +50,11 @@ static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF]; #define EXTI_REG_FTSR (EXTI->FTSR1) #define EXTI_REG_PR (EXTI->PR1) #define EXTI_REG_IMR (EXTI->IMR1) +#elif defined(CPU_FAM_STM32MP1) +#define EXTI_REG_RTSR (EXTI->RTSR1) +#define EXTI_REG_FTSR (EXTI->FTSR1) +#define EXTI_REG_PR (EXTI->PR1) +#define EXTI_REG_IMR (EXTI_C2->IMR1) #else #define EXTI_REG_RTSR (EXTI->RTSR) #define EXTI_REG_FTSR (EXTI->FTSR) @@ -74,7 +78,11 @@ static inline GPIO_TypeDef *_port(gpio_t pin) */ static inline int _port_num(gpio_t pin) { +#if defined(CPU_FAM_STM32MP1) + return (((pin - GPIOA_BASE) >> 12) & 0x0f); +#else return ((pin >> 10) & 0x0f); +#endif } /** @@ -102,6 +110,8 @@ static inline void port_init_clock(GPIO_TypeDef *port, gpio_t pin) PWR->CR2 |= PWR_CR2_IOSV; } #endif /* PWR_CR2_IOSV */ +#elif defined(CPU_FAM_STM32MP1) + periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin))); #else periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin))); #endif @@ -161,6 +171,8 @@ void gpio_init_analog(gpio_t pin) #elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ defined (CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin))); +#elif defined(CPU_FAM_STM32MP1) + periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin))); #else periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin))); #endif @@ -223,7 +235,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, isr_ctx[pin_num].arg = arg; /* enable clock of the SYSCFG module for EXTI configuration */ -#ifndef CPU_FAM_STM32WB +#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) #ifdef CPU_FAM_STM32F0 periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN); #elif defined(CPU_FAM_STM32G0) @@ -250,6 +262,31 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, else { NVIC_EnableIRQ(EXTI4_15_IRQn); } +#elif defined(CPU_FAM_STM32MP1) + if (pin_num < 5) { + NVIC_EnableIRQ(EXTI0_IRQn + pin_num); + } + else if (pin_num < 6) { + NVIC_EnableIRQ(EXTI5_IRQn); + } + else if (pin_num < 10) { + NVIC_EnableIRQ(EXTI6_IRQn + pin_num - 6); + } + else if (pin_num < 11) { + NVIC_EnableIRQ(EXTI10_IRQn); + } + else if (pin_num < 12) { + NVIC_EnableIRQ(EXTI11_IRQn); + } + else if (pin_num < 14) { + NVIC_EnableIRQ(EXTI12_IRQn + pin_num - 12); + } + else if (pin_num < 15) { + NVIC_EnableIRQ(EXTI14_IRQn); + } + else { + NVIC_EnableIRQ(EXTI15_IRQn); + } #else if (pin_num < 5) { NVIC_EnableIRQ(EXTI0_IRQn + pin_num); @@ -271,13 +308,22 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, /* enable specific pin as exti sources */ EXTI->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 8)); EXTI->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 8)); - /* clear any pending requests */ - EXTI->RPR1 = (1 << pin_num); - EXTI->FPR1 = (1 << pin_num); +#elif defined(CPU_FAM_STM32MP1) + /* enable specific pin as exti sources */ + EXTI->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4)); + EXTI->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4)); #else /* enable specific pin as exti sources */ SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4)); SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4)); +#endif + +#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \ + defined(CPU_FAM_STM32MP1) + /* clear any pending requests */ + EXTI->RPR1 = (1 << pin_num); + EXTI->FPR1 = (1 << pin_num); +#else /* clear any pending requests */ EXTI_REG_PR = (1 << pin_num); #endif @@ -289,7 +335,8 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, void isr_exti(void) { -#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) +#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \ + defined(CPU_FAM_STM32MP1) /* only generate interrupts against lines which have their IMR set */ uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_REG_IMR); uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_REG_IMR); diff --git a/cpu/stm32/periph/pm.c b/cpu/stm32/periph/pm.c index 5425aec391..371c0f1604 100644 --- a/cpu/stm32/periph/pm.c +++ b/cpu/stm32/periph/pm.c @@ -53,7 +53,8 @@ #define PM_STOP_CONFIG (PWR_CR1_LPMS_0) #elif defined(CPU_FAM_STM32F7) #define PM_STOP_CONFIG (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS) -#elif defined(CPU_FAM_STM32WB) +#elif defined(CPU_FAM_STM32MP1) +#define PM_STOP_CONFIG (0) #else #define PM_STOP_CONFIG (PWR_CR_LPDS | PWR_CR_FPDS) #endif @@ -74,6 +75,8 @@ #define PM_STANDBY_CONFIG (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) #elif defined(CPU_FAM_STM32F7) #define PM_STANDBY_CONFIG (PWR_CR1_PDDS | PWR_CR1_CSBF) +#elif defined(CPU_FAM_STM32MP1) +#define PM_STANDBY_CONFIG (0) #else #define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF) #endif @@ -92,6 +95,9 @@ #elif defined(CPU_FAM_STM32F7) #define PWR_CR_REG PWR->CR1 #define PWR_WUP_REG PWR->CSR2 +#elif defined(CPU_FAM_STM32MP1) +#define PWR_CR_REG PWR->CR1 +#define PWR_WUP_REG PWR->MCUWKUPENR #else #define PWR_CR_REG PWR->CR #define PWR_WUP_REG PWR->CSR @@ -102,7 +108,7 @@ void pm_set(unsigned mode) int deep; switch (mode) { -#ifdef STM32_PM_STANDBY +#if !defined(CPU_FAM_STM32MP1) case STM32_PM_STANDBY: PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG); PWR_CR_REG |= PM_STANDBY_CONFIG; @@ -125,14 +131,12 @@ void pm_set(unsigned mode) deep = 1; break; #endif -#ifdef STM32_PM_STOP case STM32_PM_STOP: PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG); PWR_CR_REG |= PM_STOP_CONFIG; /* Set SLEEPDEEP bit of system control block */ deep = 1; break; -#endif default: deep = 0; break; @@ -142,7 +146,9 @@ void pm_set(unsigned mode) if (deep) { /* Re-init clock after STOP */ +#if !defined(CPU_FAM_STM32MP1) || IS_USED(MODULE_STM32MP1_ENG_MODE) stmclk_init_sysclk(); +#endif } } diff --git a/cpu/stm32/periph/uart.c b/cpu/stm32/periph/uart.c index 2dadad0fb0..afc7821367 100644 --- a/cpu/stm32/periph/uart.c +++ b/cpu/stm32/periph/uart.c @@ -45,7 +45,7 @@ #elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \ defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \ defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32F7) || \ - defined(CPU_FAM_STM32G4) + defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32MP1) #define ISR_REG ISR #define ISR_TXE USART_ISR_TXE #define ISR_RXNE USART_ISR_RXNE @@ -297,7 +297,24 @@ static inline void uart_init_usart(uart_t uart, uint32_t baudrate) uint32_t clk; /* calculate and apply baudrate */ +#ifdef CPU_FAM_STM32MP1 + RCC->UART35CKSELR = uart_config[uart].clk_src; + + switch (uart_config[uart].clk_src) { + case RCC_UART35CKSELR_UART35SRC_2: /* HSI */ + clk = CLOCK_HSI; + break; + case RCC_UART35CKSELR_UART35SRC_4: /* HSE */ + clk = CLOCK_HSE; + break; + default: /* return */ + return; + } + + clk /= baudrate; +#else clk = periph_apb_clk(uart_config[uart].bus) / baudrate; +#endif mantissa = (uint16_t)(clk / 16); fraction = (uint8_t)(clk - (mantissa * 16)); dev(uart)->BRR = ((mantissa & 0x0fff) << 4) | (fraction & 0x0f); diff --git a/cpu/stm32/stm32_info.mk b/cpu/stm32/stm32_info.mk index 04175f25e7..c81f622f23 100644 --- a/cpu/stm32/stm32_info.mk +++ b/cpu/stm32/stm32_info.mk @@ -8,15 +8,20 @@ # - STM32_PINCOUNT: R (64) # - STM32_ROMSIZE: G (1024K) CPU_MODEL_UPPERCASE = $(call uppercase,$(CPU_MODEL)) -STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G)([0-7]|B)([A-Z0-9])([0-9])(.)(.)(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/') +STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G|MP)([0-7]|B)([A-Z0-9])([0-9])(.)(.)?(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/') STM32_TYPE = $(word 1, $(STM32_INFO)) STM32_FAMILY = $(word 2, $(STM32_INFO)) STM32_MODEL = $(word 3, $(STM32_INFO)) -STM32_MODEL2 = $(word 4, $(STM32_INFO)) -STM32_MODEL3 = $(word 5, $(STM32_INFO)) -STM32_PINCOUNT = $(word 6, $(STM32_INFO)) -STM32_ROMSIZE = $(word 7, $(STM32_INFO)) -STM32_RAMMOD = $(word 8, $(STM32_INFO)) +ifneq (MP, $(STM32_TYPE)) + STM32_MODEL2 = $(word 4, $(STM32_INFO)) + STM32_MODEL3 = $(word 5, $(STM32_INFO)) + STM32_PINCOUNT = $(word 6, $(STM32_INFO)) + STM32_ROMSIZE = $(word 7, $(STM32_INFO)) + STM32_RAMMOD = $(word 8, $(STM32_INFO)) +else + STM32_MODEL2 = $(word 6, $(STM32_INFO)) + STM32_PINCOUNT = $(word 7, $(STM32_INFO))$(word 8, $(STM32_INFO)) +endif CPU_FAM = $(call lowercase,$(STM32_TYPE)$(STM32_FAMILY)) @@ -24,7 +29,7 @@ ifeq (f0,$(CPU_FAM)) CPU_CORE = cortex-m0 else ifneq (,$(filter $(CPU_FAM),f1 f2 l1)) CPU_CORE = cortex-m3 -else ifneq (,$(filter $(CPU_FAM),f3 f4 l4)) +else ifneq (,$(filter $(CPU_FAM),f3 f4 l4 mp1)) CPU_CORE = cortex-m4f else ifneq (,$(filter $(CPU_FAM),g4 wb)) CPU_CORE = cortex-m4 diff --git a/cpu/stm32/stm32_line.mk b/cpu/stm32/stm32_line.mk index 543106131c..50f0e91e27 100644 --- a/cpu/stm32/stm32_line.mk +++ b/cpu/stm32/stm32_line.mk @@ -137,3 +137,10 @@ ifeq (L,$(STM32_TYPE)) endif endif endif +ifeq (MP,$(STM32_TYPE)) + ifeq (157,$(STM32_MODEL)) + ifeq (C,$(STM32_MODEL2)) + CPU_LINE = STM32MP157Cxx + endif + endif +endif diff --git a/cpu/stm32/stm32_mem_lengths.mk b/cpu/stm32/stm32_mem_lengths.mk index 9fcba4afd1..f87649d245 100644 --- a/cpu/stm32/stm32_mem_lengths.mk +++ b/cpu/stm32/stm32_mem_lengths.mk @@ -1,7 +1,3 @@ -# Set the common memory addresses for stm32 MCU family -ROM_START_ADDR ?= 0x08000000 -RAM_START_ADDR ?= 0x20000000 - # The next block takes care of setting the rigth lengths of RAM and ROM # for the stm32 family. Most of the CPUs should have been taken into # account here, so no need to assign the lengths per model. @@ -278,6 +274,13 @@ else ifeq ($(STM32_TYPE), W) endif endif endif +else ifeq ($(STM32_TYPE), MP) + ifeq ($(STM32_FAMILY), 1) + ifeq ($(STM32_MODEL), 157) + RAM_START_ADDR = 0x10000000 + RAM_LEN = 384K + endif + endif endif ifeq ($(RAM_LEN), ) @@ -308,6 +311,26 @@ else ifeq ($(STM32_ROMSIZE), H) ROM_LEN = 1536K else ifeq ($(STM32_ROMSIZE), I) ROM_LEN = 2048K +else ifeq ($(STM32_TYPE), MP) + ifeq ($(STM32_FAMILY), 1) + # STM32MP1 family has no flash ROM memory. + # Thus a part of SRAM must be considered as ROM. + # RETRAM (0x0 address) is setup as ROM by default. + # However in RIOT, vector table is relocated using VTOR register. + # Considering the minimum alignment is 128 words and knowing the number of + # interrupt vectors for a given MCU, if a device has for example 150 interrupt + # channels: + # Vector table has a size of 150 * 4 = 600 = 0x258 + # As the table should be 128 word aligned, vector table size reserved is 0x400. + ifeq ($(STM32_MODEL), 157) + ROM_START_ADDR ?= 0x0 + ifneq (,$(filter stm32mp1_eng_mode,$(USEMODULE))) + ROM_OFFSET ?= 0x400 + endif + ROM_LEN ?= 64K + endif + endif +else endif ifeq ($(STM32_PINCOUNT), A) @@ -348,4 +371,10 @@ else ifeq ($(STM32_PINCOUNT), V) STM32_PIN = 100 else ifeq ($(STM32_PINCOUNT), Z) STM32_PIN = 144 +else ifeq ($(STM32_PINCOUNT), AC) + STM32_PIN = 361 endif + +# Set the common memory addresses for stm32 MCU family +ROM_START_ADDR ?= 0x08000000 +RAM_START_ADDR ?= 0x20000000 diff --git a/cpu/stm32/stmclk/Makefile b/cpu/stm32/stmclk/Makefile index 8203ca23ef..f33f4111cd 100644 --- a/cpu/stm32/stmclk/Makefile +++ b/cpu/stm32/stmclk/Makefile @@ -1,6 +1,8 @@ MODULE = stm32_clk -SRC = stmclk_common.c +ifneq (mp1,$(CPU_FAM)) + SRC = stmclk_common.c +endif ifneq (,$(filter $(CPU_FAM),f2 f4 f7)) SRC += stmclk_f2f4f7.c @@ -14,6 +16,13 @@ else ifneq (,$(filter $(CPU_FAM),l5)) SRC += stmclk_l5.c else ifneq (,$(filter $(CPU_FAM),g0 g4)) SRC += stmclk_gx.c +else ifneq (,$(filter $(CPU_FAM),mp1)) + ifneq (,$(filter stm32mp1_eng_mode,$(USEMODULE))) + SRC = stmclk_mp1.c + else + # Do not use *.c as SRC if SRC is empty (see Makefile.base) + NO_AUTO_SRC = 1 + endif endif include $(RIOTBASE)/Makefile.base diff --git a/cpu/stm32/stmclk/stmclk_mp1.c b/cpu/stm32/stmclk/stmclk_mp1.c new file mode 100644 index 0000000000..1b28d628ec --- /dev/null +++ b/cpu/stm32/stmclk/stmclk_mp1.c @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2020 Savoir-faire Linux + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_stm32 + * @{ + * + * @file + * @brief Implementation of STM32 clock configuration for STM32MP1 + * + * @author Gilles DOFFE + * + * @} + */ + +#include "cpu.h" +#include "stmclk.h" +#include "periph_conf.h" + +/* PLL configuration */ +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#define PLL_SRC RCC_RCK3SELR_PLL3SRC_1 +#else +#define PLL_SRC RCC_RCK3SELR_PLL3SRC_0 +#endif + +/* Compute the bitfields for the PLL configuration */ +#define PLL_P (((CONFIG_CLOCK_PLL_P / 2)) \ + << RCC_PLL3CFGR2_DIVP_Pos) +#define PLL_M ((CONFIG_CLOCK_PLL_M) \ + << RCC_PLL3CFGR1_DIVM3_Pos) +#define PLL_N ((CONFIG_CLOCK_PLL_N) \ + << RCC_PLL3CFGR1_DIVN_Pos) +#define PLL_Q ((CONFIG_CLOCK_PLL_Q) \ + << RCC_PLL3CFGR2_DIVQ_Pos) +#if defined(RCC_PLL3CFGR2_DIVR) && defined(CONFIG_CLOCK_PLL_R) +#define PLL_R ((CONFIG_CLOCK_PLL_R) \ + << RCC_PLL3CFGR2_DIVR_Pos) +#else +#define PLL_R (0) +#endif + +/* Configure HLCK and PCLK prescalers */ +#if CONFIG_CLOCK_MCU_DIV == 1 +#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_0) +#elif CONFIG_CLOCK_MCU_DIV == 2 +#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_1) +#elif CONFIG_CLOCK_MCU_DIV == 4 +#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_2) +#elif CONFIG_CLOCK_MCU_DIV == 8 +#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_3) +#elif CONFIG_CLOCK_MCU_DIV == 16 +#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_4) +#elif CONFIG_CLOCK_MCU_DIV == 32 +#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_5) +#elif CONFIG_CLOCK_MCU_DIV == 64 +#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_6) +#elif CONFIG_CLOCK_MCU_DIV == 128 +#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_7) +#elif CONFIG_CLOCK_MCU_DIV == 256 +#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_8) +#elif CONFIG_CLOCK_MCU_DIV == 512 +#define CLOCK_MCU_DIV (RCC_MCUDIVR_MCUDIV_9) +#else +#error "Invalid MCU prescaler value (only 1, 2, 4, 8, 16, 32, 64, 128, 256 \ +and 512 allowed)" +#endif + +#if CONFIG_CLOCK_APB1_DIV == 1 +#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_0) +#elif CONFIG_CLOCK_APB1_DIV == 2 +#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_1) +#elif CONFIG_CLOCK_APB1_DIV == 4 +#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_2) +#elif CONFIG_CLOCK_APB1_DIV == 8 +#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_3) +#elif CONFIG_CLOCK_APB1_DIV == 16 +#define CLOCK_APB1_DIV (RCC_APB1DIVR_APB1DIV_4) +#else +#error "Invalid APB1 prescaler value (only 1, 2, 4, 8 and 16 allowed)" +#endif + +#if CONFIG_CLOCK_APB2_DIV == 1 +#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_0) +#elif CONFIG_CLOCK_APB2_DIV == 2 +#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_1) +#elif CONFIG_CLOCK_APB2_DIV == 4 +#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_2) +#elif CONFIG_CLOCK_APB2_DIV == 8 +#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_3) +#elif CONFIG_CLOCK_APB2_DIV == 16 +#define CLOCK_APB2_DIV (RCC_APB2DIVR_APB2DIV_4) +#else +#error "Invalid APB2 prescaler value (only 1, 2, 4, 8 and 16 allowed)" +#endif + +#if CONFIG_CLOCK_APB3_DIV == 1 +#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_0) +#elif CONFIG_CLOCK_APB3_DIV == 2 +#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_1) +#elif CONFIG_CLOCK_APB3_DIV == 4 +#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_2) +#elif CONFIG_CLOCK_APB3_DIV == 8 +#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_3) +#elif CONFIG_CLOCK_APB3_DIV == 16 +#define CLOCK_APB3_DIV (RCC_APB3DIVR_APB3DIV_4) +#else +#error "Invalid APB3 prescaler value (only 1, 2, 4, 8 and 16 allowed)" +#endif + +/* Check whether PLL must be enabled: + - When PLL is used as SYSCLK + - When PLLQ is required +*/ +#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_CLOCK_ENABLE_PLLQ) +#define CONFIG_CLOCK_USE_PLL 1 +#else +#define CONFIG_CLOCK_USE_PLL 0 +#endif + +/* Check whether HSE must be enabled: + - When HSE is used as SYSCLK + - When PLL is used as SYSCLK and the board provides HSE (since HSE will be + used as PLL input clock) +*/ +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \ + (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_CLOCK_USE_PLL)) +#define CONFIG_CLOCK_USE_HSE 1 +#else +#define CONFIG_CLOCK_USE_HSE 0 +#endif + +void stmclk_enable_hsi(void) +{ + RCC->OCENSETR |= RCC_OCENSETR_HSION; + while (!(RCC->OCRDYR & RCC_OCRDYR_HSIRDY)) {} +} + +static void stmclk_enable_hse(void) +{ + RCC->OCENSETR |= RCC_OCENSETR_HSEON; + while (!(RCC->OCRDYR & RCC_OCRDYR_HSERDY)) {} +} + +void stmclk_init_sysclk(void) +{ + /* disable any interrupts. Global interrupts could be enabled if this is + * called from some kind of bootloader... */ + unsigned is = irq_disable(); + RCC->MC_CIFR = 0; + + /* enable HSI clock for the duration of initialization */ + stmclk_enable_hsi(); + + /* use HSI as system clock while we do any further configuration and + * configure the AHB and APB clock dividers as configured by the board */ + /* MCUDIV */ + RCC->MCUDIVR = CLOCK_MCU_DIV; + while ((RCC->MCUDIVR & RCC_MCUDIVR_MCUDIVRDY) + != RCC_MCUDIVR_MCUDIVRDY) {} + /* APB1DIV */ + RCC->APB1DIVR = CLOCK_APB1_DIV; + while ((RCC->APB1DIVR & RCC_APB1DIVR_APB1DIVRDY) + != RCC_APB1DIVR_APB1DIVRDY) {} + /* APB2DIV */ + RCC->APB2DIVR = CLOCK_APB2_DIV; + while ((RCC->APB2DIVR & RCC_APB2DIVR_APB2DIVRDY) + != RCC_APB2DIVR_APB2DIVRDY) {} + /* APB3DIV */ + RCC->APB3DIVR = CLOCK_APB3_DIV; + while ((RCC->APB3DIVR & RCC_APB3DIVR_APB3DIVRDY) + != RCC_APB3DIVR_APB3DIVRDY) {} + + /* MCU clock source */ + RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_0; /* HSI */ + while ((RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY) + != RCC_MSSCKSELR_MCUSSRCRDY) {} + + /* disable all active clocks except HSI -> resets the clk configuration */ + RCC->OCENCLRR = ~(RCC_OCENSETR_HSION); + + /* if configured, we need to enable the HSE clock now */ + if (IS_ACTIVE(CONFIG_CLOCK_USE_HSE)) { + stmclk_enable_hse(); + } + + if (IS_ACTIVE(CONFIG_CLOCK_USE_PLL)) { + /* now we can safely configure the PLL */ + RCC->PLL3CFGR1 = (PLL_M | PLL_N); + RCC->PLL3CFGR2 = (PLL_P | PLL_Q | PLL_R); + + RCC->RCK3SELR |= PLL_SRC; + while (!(RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRCRDY)) {} + + /* and start the PLL */ + RCC->PLL3CR |= (RCC_PLL3CR_DIVPEN | RCC_PLL3CR_DIVQEN + | RCC_PLL3CR_DIVREN | RCC_PLL3CR_PLLON); + while (!(RCC->PLL3CR & RCC_PLL3CR_PLL3RDY)) {} + } + + /* Configure SYSCLK */ + if (IS_ACTIVE(CONFIG_CLOCK_USE_PLL)) { + RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_3; /* PLL3 */ + } + else if (IS_ACTIVE(CONFIG_CLOCK_USE_HSE)) { + RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_1; /* HSE */ + } + else { + RCC->MSSCKSELR = RCC_MSSCKSELR_MCUSSRC_0; /* HSI by default */ + } + /* Wait SYSCLK to be ready */ + while (!(RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY)) {} + + irq_restore(is); +} diff --git a/dist/tools/openocd/adapters/stlink-dap.cfg b/dist/tools/openocd/adapters/stlink-dap.cfg new file mode 100644 index 0000000000..91128a6bc9 --- /dev/null +++ b/dist/tools/openocd/adapters/stlink-dap.cfg @@ -0,0 +1,3 @@ +try { + source [find interface/stlink-dap.cfg] +} diff --git a/dist/tools/openocd/openocd.sh b/dist/tools/openocd/openocd.sh index 9fe06ff971..92dd062244 100755 --- a/dist/tools/openocd/openocd.sh +++ b/dist/tools/openocd/openocd.sh @@ -51,6 +51,15 @@ # DBG: debugger client command, default: 'gdb -q' # TUI: if TUI!=null, the -tui option will be used # +# debugr: debug +# debug given file on the target but flash it first directly +# in RAM. +# +# flashr: flash +# flash given file to the target but directly in RAM. +# +# See 'flash' command above for options +# # debug-server: starts OpenOCD as GDB server, but does not connect to # to it with any frontend. This might be useful when using # IDEs. @@ -67,6 +76,8 @@ # Default GDB port, set to 0 to disable, required != 0 for debug and debug-server targets : ${GDB_PORT:=3333} +# Default GDB port core offset +: ${GDB_PORT_CORE_OFFSET:=0} # Default telnet port, set to 0 to disable : ${TELNET_PORT:=4444} # Default TCL port, set to 0 to disable @@ -86,7 +97,7 @@ # Debugger client command, can be used to wrap GDB in a front-end : ${DBG:=${GDB}} # Default debugger flags, -: ${DBG_DEFAULT_FLAGS:=-q -ex \"tar ext :${GDB_PORT}\"} +: ${DBG_DEFAULT_FLAGS:=-q -ex \"tar ext :$(( GDB_PORT + GDB_PORT_CORE_OFFSET ))\"} # Extra debugger flags, added by the user : ${DBG_EXTRA_FLAGS:=} # Debugger flags, will be passed to sh -c, remember to escape any quotation signs. @@ -100,6 +111,8 @@ : ${OPENOCD_DBG_EXTRA_CMD:=} # command used to reset the board : ${OPENOCD_CMD_RESET_RUN:="-c 'reset run'"} +# Select core on multi-core processors. +: ${OPENOCD_CORE:=} # This is an optional offset to the base address that can be used to flash an # image in a different location than it is linked at. This feature can be useful # when flashing images for firmware swapping/remapping boot loaders. @@ -254,6 +267,52 @@ _flash_address() { _flash_list | awk "NR==${bank_num}"'{printf "0x%08x\n", $4}' } +do_flashr() { + IMAGE_FILE=$1 + test_config + test_imagefile + if [ -n "${PRE_FLASH_CHECK_SCRIPT}" ]; then + sh -c "${PRE_FLASH_CHECK_SCRIPT} '${IMAGE_FILE}'" + RETVAL=$? + if [ $RETVAL -ne 0 ]; then + echo "pre-flash checks failed, status=$RETVAL" + exit $RETVAL + fi + fi + + # In case of binary file, IMAGE_OFFSET should include the flash base address + # This allows flashing normal binary files without env configuration + if _is_binfile "${IMAGE_FILE}" "${IMAGE_TYPE}"; then + # hardwritten to use the first bank + FLASH_ADDR=$(_flash_address 1) + echo "Binfile detected, adding ROM base address: ${FLASH_ADDR}" + IMAGE_TYPE=bin + IMAGE_OFFSET=$(printf "0x%08x\n" "$((${IMAGE_OFFSET} + ${FLASH_ADDR}))") + fi + + if [ "${IMAGE_OFFSET}" != "0" ]; then + echo "Flashing with IMAGE_OFFSET: ${IMAGE_OFFSET}" + fi + + # flash device + sh -c "${OPENOCD} \ + ${OPENOCD_ADAPTER_INIT} \ + -f '${OPENOCD_CONFIG}' \ + ${OPENOCD_EXTRA_INIT} \ + ${OPENOCD_EXTRA_RESET_INIT} \ + -c 'tcl_port 0' \ + -c 'telnet_port 0' \ + -c 'gdb_port 0' \ + -c 'init' \ + -c 'targets ${OPENOCD_CORE}' \ + -c 'reset' \ + -c 'halt' \ + -c 'load_image \"${IMAGE_FILE}\" ' \ + -c 'resume ${START_ADDR}' \ + -c 'shutdown'" && + echo "'Done flashing" +} + # # now comes the actual actions # @@ -332,7 +391,7 @@ do_debug() { -c 'gdb_port ${GDB_PORT}' \ -c 'init' \ ${OPENOCD_DBG_EXTRA_CMD} \ - -c 'targets' \ + -c 'targets ${OPENOCD_CORE}' \ ${OPENOCD_DBG_START_CMD} \ -l /dev/null & \ echo \$! > $OCD_PIDFILE" & @@ -391,6 +450,19 @@ case "${ACTION}" in echo "### Flashing Target ###" do_flash "$@" ;; + flashr) + START_ADDR=$(objdump -f $1 | sed '/^$/d' | tail -1 | grep -o "0x[0-9a-fA-F].*") + echo "### Flashing target RAM ###" + do_flashr "$@" + ;; + debugr) + START_ADDR=$(objdump -f $1 | sed '/^$/d' | tail -1 | grep -o "0x[0-9a-fA-F].*") + echo "Start address: $START_ADDR" + DBG_FLAGS="$DBG_FLAGS \ + -ex 'load $1' \ + " + do_debug "$@" + ;; debug) echo "### Starting Debugging ###" do_debug "$@" diff --git a/examples/dtls-echo/Makefile.ci b/examples/dtls-echo/Makefile.ci index 5cd8f11711..d82fb9f534 100644 --- a/examples/dtls-echo/Makefile.ci +++ b/examples/dtls-echo/Makefile.ci @@ -37,5 +37,6 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ yunjia-nrf51822 \ # diff --git a/examples/dtls-sock/Makefile.ci b/examples/dtls-sock/Makefile.ci index 0211f5fbc6..bd5cd8c793 100644 --- a/examples/dtls-sock/Makefile.ci +++ b/examples/dtls-sock/Makefile.ci @@ -40,5 +40,6 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f0discovery \ stm32l0538-disco \ stm32mindev \ + stm32mp157c-dk2 \ yunjia-nrf51822 \ # diff --git a/examples/dtls-wolfssl/Makefile.ci b/examples/dtls-wolfssl/Makefile.ci index 06f7f32c91..683e19c2ac 100644 --- a/examples/dtls-wolfssl/Makefile.ci +++ b/examples/dtls-wolfssl/Makefile.ci @@ -35,5 +35,6 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f0discovery \ stm32l0538-disco \ stm32mindev \ + stm32mp157c-dk2 \ yunjia-nrf51822 \ # diff --git a/examples/gnrc_border_router/Makefile.ci b/examples/gnrc_border_router/Makefile.ci index 296206814d..6310f021cb 100644 --- a/examples/gnrc_border_router/Makefile.ci +++ b/examples/gnrc_border_router/Makefile.ci @@ -52,6 +52,7 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ telosb \ waspmote-pro \ weio \ diff --git a/examples/gnrc_networking/Makefile.ci b/examples/gnrc_networking/Makefile.ci index 5e3a5acb6d..728e0c2693 100644 --- a/examples/gnrc_networking/Makefile.ci +++ b/examples/gnrc_networking/Makefile.ci @@ -38,6 +38,7 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ telosb \ waspmote-pro \ z1 \ diff --git a/examples/javascript/Makefile.ci b/examples/javascript/Makefile.ci index 898c6989cf..3708e29680 100644 --- a/examples/javascript/Makefile.ci +++ b/examples/javascript/Makefile.ci @@ -47,5 +47,6 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ yunjia-nrf51822 \ # diff --git a/examples/lua_REPL/Makefile.ci b/examples/lua_REPL/Makefile.ci index f6b1dfac25..2c5eaa6985 100644 --- a/examples/lua_REPL/Makefile.ci +++ b/examples/lua_REPL/Makefile.ci @@ -91,6 +91,7 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f0discovery \ stm32f3discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ wemos-zero \ yarm \ yunjia-nrf51822 \ diff --git a/examples/lua_basic/Makefile.ci b/examples/lua_basic/Makefile.ci index a02a2abf9f..bf85b628be 100644 --- a/examples/lua_basic/Makefile.ci +++ b/examples/lua_basic/Makefile.ci @@ -38,4 +38,5 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ # diff --git a/examples/micropython/Makefile.ci b/examples/micropython/Makefile.ci index bcde1dc9ad..855779edb4 100644 --- a/examples/micropython/Makefile.ci +++ b/examples/micropython/Makefile.ci @@ -26,4 +26,5 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ # diff --git a/examples/paho-mqtt/Makefile.ci b/examples/paho-mqtt/Makefile.ci index a5c907acca..c475bf9054 100644 --- a/examples/paho-mqtt/Makefile.ci +++ b/examples/paho-mqtt/Makefile.ci @@ -27,5 +27,6 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ yunjia-nrf51822 \ # diff --git a/examples/wakaama/Makefile.ci b/examples/wakaama/Makefile.ci index e5489282be..7e824e9455 100644 --- a/examples/wakaama/Makefile.ci +++ b/examples/wakaama/Makefile.ci @@ -34,5 +34,6 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ yunjia-nrf51822 \ # diff --git a/makefiles/pseudomodules.inc.mk b/makefiles/pseudomodules.inc.mk index 4189235592..2a57defd2e 100644 --- a/makefiles/pseudomodules.inc.mk +++ b/makefiles/pseudomodules.inc.mk @@ -125,6 +125,7 @@ PSEUDOMODULES += stdio_uart_rx PSEUDOMODULES += stm32_eth PSEUDOMODULES += stm32_eth_auto PSEUDOMODULES += stm32_eth_link_up +PSEUDOMODULES += stm32mp1_eng_mode PSEUDOMODULES += suit_transport_% PSEUDOMODULES += suit_storage_% PSEUDOMODULES += wakaama_objects_% diff --git a/makefiles/tools/openocd-adapters/stlink-dap.inc.mk b/makefiles/tools/openocd-adapters/stlink-dap.inc.mk new file mode 100644 index 0000000000..312a557f58 --- /dev/null +++ b/makefiles/tools/openocd-adapters/stlink-dap.inc.mk @@ -0,0 +1,5 @@ +OPENOCD_ADAPTER_INIT ?= -c 'set stlink_version $(STLINK_VERSION);source $(RIOTBASE)/dist/tools/openocd/adapters/stlink-dap.cfg' + +OPENOCD_TRANSPORT ?= dapdirect_swd + +include $(RIOTMAKE)/tools/openocd-adapters/stlink.inc.mk diff --git a/makefiles/tools/openocd.inc.mk b/makefiles/tools/openocd.inc.mk index 25ce37915b..e2c4324db5 100644 --- a/makefiles/tools/openocd.inc.mk +++ b/makefiles/tools/openocd.inc.mk @@ -16,10 +16,17 @@ endif OPENOCD_CONFIG ?= $(BOARDDIR)/dist/openocd.cfg -# Export OPENOCD_CONFIG to required targets OPENOCD_TARGETS = debug% flash% reset + +# Export GDB_PORT_CORE_OFFSET to required targets +$(call target-export-variables,$(OPENOCD_TARGETS),GDB_PORT_CORE_OFFSET) + +# Export OPENOCD_CONFIG to required targets $(call target-export-variables,$(OPENOCD_TARGETS),OPENOCD_CONFIG) +# Export OPENOCD_CORE to required targets +$(call target-export-variables,$(OPENOCD_TARGETS),OPENOCD_CORE) + # Export OPENOCD_ADAPTER_INIT to required targets $(call target-export-variables,$(OPENOCD_TARGETS),OPENOCD_ADAPTER_INIT) diff --git a/pkg/paho-mqtt/patches/0001-MQTTClient-C-skip-SUCCESS-enum-on-STM32-cpus.patch b/pkg/paho-mqtt/patches/0001-MQTTClient-C-skip-SUCCESS-enum-on-STM32-cpus.patch index 38145a29a7..107ff62050 100644 --- a/pkg/paho-mqtt/patches/0001-MQTTClient-C-skip-SUCCESS-enum-on-STM32-cpus.patch +++ b/pkg/paho-mqtt/patches/0001-MQTTClient-C-skip-SUCCESS-enum-on-STM32-cpus.patch @@ -11,11 +11,12 @@ diff --git a/MQTTClient-C/src/MQTTClient.h b/MQTTClient-C/src/MQTTClient.h index b612341..4f1dfba 100755 --- a/MQTTClient-C/src/MQTTClient.h +++ b/MQTTClient-C/src/MQTTClient.h -@@ -54,7 +54,13 @@ +@@ -54,7 +54,14 @@ enum QoS { QOS0, QOS1, QOS2, SUBFAIL=0x80 }; /* all failure return codes must be negative */ -+#if !defined(CPU_LINE_STM32F030x4) && defined(CPU_STM32) ++#if !defined(CPU_LINE_STM32F030x4) && !defined(CPU_LINE_STM32MP157Cxx) && \ ++ defined(CPU_STM32) +/* the SUCCESS enum is defined for all stm32. + Since it contains the same value, we just skip its definition here for them. */ +enum returnCode { BUFFER_OVERFLOW = -2, FAILURE = -1}; diff --git a/tests/gnrc_dhcpv6_client_6lbr/Makefile.ci b/tests/gnrc_dhcpv6_client_6lbr/Makefile.ci index d3648bdfd4..321f5fd833 100644 --- a/tests/gnrc_dhcpv6_client_6lbr/Makefile.ci +++ b/tests/gnrc_dhcpv6_client_6lbr/Makefile.ci @@ -51,6 +51,7 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ telosb \ waspmote-pro \ yunjia-nrf51822 \ diff --git a/tests/gnrc_ipv6_ext_frag/Makefile.ci b/tests/gnrc_ipv6_ext_frag/Makefile.ci index 28999d9e2a..a8a9b6ac03 100644 --- a/tests/gnrc_ipv6_ext_frag/Makefile.ci +++ b/tests/gnrc_ipv6_ext_frag/Makefile.ci @@ -34,6 +34,7 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ telosb \ waspmote-pro \ z1 \ diff --git a/tests/gnrc_netif/Makefile.ci b/tests/gnrc_netif/Makefile.ci index c71a6ebc57..510de453d8 100644 --- a/tests/gnrc_netif/Makefile.ci +++ b/tests/gnrc_netif/Makefile.ci @@ -52,6 +52,7 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ telosb \ waspmote-pro \ yunjia-nrf51822 \ diff --git a/tests/gnrc_udp/Makefile.ci b/tests/gnrc_udp/Makefile.ci index ca568dc088..d74ee4138c 100644 --- a/tests/gnrc_udp/Makefile.ci +++ b/tests/gnrc_udp/Makefile.ci @@ -41,6 +41,7 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ telosb \ waspmote-pro \ yunjia-nrf51822 \ diff --git a/tests/lwip/Makefile.ci b/tests/lwip/Makefile.ci index cc6870f34e..3fe76a4afe 100644 --- a/tests/lwip/Makefile.ci +++ b/tests/lwip/Makefile.ci @@ -21,5 +21,6 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ yunjia-nrf51822 \ # diff --git a/tests/lwip_sock_tcp/Makefile.ci b/tests/lwip_sock_tcp/Makefile.ci index 20dfbbbb5f..7af88900e6 100644 --- a/tests/lwip_sock_tcp/Makefile.ci +++ b/tests/lwip_sock_tcp/Makefile.ci @@ -17,4 +17,5 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ # diff --git a/tests/pkg_tensorflow-lite/Makefile.ci b/tests/pkg_tensorflow-lite/Makefile.ci index 1edf2c171b..e917c0fc3f 100644 --- a/tests/pkg_tensorflow-lite/Makefile.ci +++ b/tests/pkg_tensorflow-lite/Makefile.ci @@ -32,6 +32,7 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ usb-kw41z \ yunjia-nrf51822 \ # diff --git a/tests/pkg_tinydtls_sock_async/Makefile.ci b/tests/pkg_tinydtls_sock_async/Makefile.ci index 0211f5fbc6..bd5cd8c793 100644 --- a/tests/pkg_tinydtls_sock_async/Makefile.ci +++ b/tests/pkg_tinydtls_sock_async/Makefile.ci @@ -40,5 +40,6 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f0discovery \ stm32l0538-disco \ stm32mindev \ + stm32mp157c-dk2 \ yunjia-nrf51822 \ # diff --git a/tests/pkg_utensor/Makefile.ci b/tests/pkg_utensor/Makefile.ci index f041bf7cdc..df615fa9ed 100644 --- a/tests/pkg_utensor/Makefile.ci +++ b/tests/pkg_utensor/Makefile.ci @@ -38,4 +38,5 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ # diff --git a/tests/pkg_wolfssl/Makefile.ci b/tests/pkg_wolfssl/Makefile.ci index 20dfbbbb5f..7af88900e6 100644 --- a/tests/pkg_wolfssl/Makefile.ci +++ b/tests/pkg_wolfssl/Makefile.ci @@ -17,4 +17,5 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f030f4-demo \ stm32f0discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ # diff --git a/tests/unittests/Makefile.ci b/tests/unittests/Makefile.ci index accfc710ad..1119f6e8c1 100644 --- a/tests/unittests/Makefile.ci +++ b/tests/unittests/Makefile.ci @@ -100,6 +100,7 @@ BOARD_INSUFFICIENT_MEMORY := \ stm32f0discovery \ stm32f3discovery \ stm32l0538-disco \ + stm32mp157c-dk2 \ teensy31 \ telosb \ waspmote-pro \