From 4a9cb807c6bc8753ae01f7ffd0634537d88106cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Fri, 24 Mar 2017 17:26:25 +0100 Subject: [PATCH] k60: Remove (broken) support for first revision K60 hardware The CPU has multiple issues and several parts of the platform code does not even compile cleanly for this CPU in the current state. This removes support for parts MK60DN256ZVLL10, MK60DN512ZVLL10 (note the Z) CPUs with this part number were used in Mulle v0.60 which only has been used in some in-house projects at Eistec and LTU. --- boards/mulle/Makefile.include | 15 - boards/mulle/board.c | 14 - cpu/k60/cpu.c | 29 - cpu/k60/include/MK60-comp.h | 69 - cpu/k60/include/cpu_conf.h | 32 +- cpu/k60/include/vendor/MK60D10.h | 6 + cpu/k60/include/vendor/MK60DZ10.h | 9247 --------------------------- cpu/k60/ldscripts/K60DN256ZVLL10.ld | 1 - cpu/k60/ldscripts/K60DN512ZVLL10.ld | 1 - 9 files changed, 8 insertions(+), 9406 deletions(-) delete mode 100644 cpu/k60/include/MK60-comp.h delete mode 100644 cpu/k60/include/vendor/MK60DZ10.h delete mode 120000 cpu/k60/ldscripts/K60DN256ZVLL10.ld delete mode 120000 cpu/k60/ldscripts/K60DN512ZVLL10.ld diff --git a/boards/mulle/Makefile.include b/boards/mulle/Makefile.include index a4bb2aca4c..bd2c87111d 100644 --- a/boards/mulle/Makefile.include +++ b/boards/mulle/Makefile.include @@ -5,22 +5,7 @@ export CPU = k60 export GDBPORT ?= 3333 # MULLE_SERIAL is used to select which specific Mulle board we are compiling for. -# This was called MULLE_BOARD_SERIAL_NUMBER previously, renamed because -# MULLE_BOARD_SERIAL_NUMBER is too long to type. ifdef MULLE_SERIAL - ifeq "200" "$(word 1, $(sort 200 $(MULLE_SERIAL)))" - # >= 200 - ifneq "220" "$(word 1, $(sort 220 $(MULLE_SERIAL)))" - # < 220 - CPU_MODEL = K60DN256ZVLL10 - # It seems some of the MK60DZ10 devices have problems with JTAG speeds >= around 400 KHz - # when programming, we reduce the speed to 300 KHz with this command. - CPU_OOCD_FLAGS += -c 'adapter_khz 300' - else - # >= 220 - CPU_MODEL = K60DN512VLL10 - endif - endif CFLAGS += -DMULLE_SERIAL=$(MULLE_SERIAL) endif diff --git a/boards/mulle/board.c b/boards/mulle/board.c index 3800b03d02..b47f1c2af1 100644 --- a/boards/mulle/board.c +++ b/boards/mulle/board.c @@ -191,24 +191,10 @@ static inline void set_fll_source(void) /* Select FLL as source (as opposed to PLL) */ SIM->SOPT2 &= ~(SIM_SOPT2_PLLFLLSEL_MASK); /* Use external 32kHz RTC clock as source for OSC32K */ -#if K60_CPU_REV == 1 - SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL_MASK; -#elif K60_CPU_REV == 2 SIM->SOPT1 = (SIM->SOPT1 & ~(SIM_SOPT1_OSC32KSEL_MASK)) | SIM_SOPT1_OSC32KSEL(2); -#else -#error Unknown K60 CPU revision -#endif /* Select RTC 32kHz clock as reference clock for the FLL */ -#if K60_CPU_REV == 1 - /* Rev 1 parts */ - SIM->SOPT2 |= SIM_SOPT2_MCGCLKSEL_MASK; -#elif K60_CPU_REV == 2 - /* Rev 2 parts */ MCG->C7 = (MCG_C7_OSCSEL_MASK); -#else -#error Unknown K60 CPU revision -#endif } static int mulle_nvram_init(void) diff --git a/cpu/k60/cpu.c b/cpu/k60/cpu.c index 3768f8374d..50818f99f6 100644 --- a/cpu/k60/cpu.c +++ b/cpu/k60/cpu.c @@ -6,7 +6,6 @@ * details. */ -#include #include "cpu.h" #include "board.h" #include "periph/init.h" @@ -21,12 +20,6 @@ * @author Joakim Nohlgård */ -/** - * @brief Check the running CPU identification to find if we are running on the - * wrong hardware. - */ -static void check_running_cpu_revision(void); - /** * @brief Initialize the CPU, set IRQ priorities */ @@ -34,30 +27,8 @@ void cpu_init(void) { /* initialize the Cortex-M core */ cortexm_init(); - /* Check that we are running on the CPU that this code was built for */ - check_running_cpu_revision(); /* trigger static peripheral initialization */ periph_init(); } -static void check_running_cpu_revision(void) -{ - /* Check that the running CPU revision matches the compiled revision */ - if (SCB->CPUID != K60_EXPECTED_CPUID) { - uint32_t CPUID = SCB->CPUID; /* This is only to ease debugging, type - * "print /x CPUID" in gdb */ - uint32_t SILICON_REVISION = (SCB->CPUID & SCB_CPUID_REVISION_Msk) + 1; - (void)CPUID; /* prevents compiler warnings about an unused variable. */ - (void)SILICON_REVISION; - - /* Running on the wrong CPU, the clock initialization is different - * between silicon revision 1.x and 2.x (LSB of CPUID) */ - /* If you unexpectedly end up on this line when debugging: - * Rebuild the code using the correct value for K60_CPU_REV */ - __asm__ volatile ("bkpt #99\n"); - - while (1); - } -} - /** @} */ diff --git a/cpu/k60/include/MK60-comp.h b/cpu/k60/include/MK60-comp.h deleted file mode 100644 index 54b52469ce..0000000000 --- a/cpu/k60/include/MK60-comp.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2015 Eistec AB - * - * This file is subject to the terms and conditions of the GNU Lesser General - * Public License v2.1. See the file LICENSE in the top level directory for more - * details. - */ - -/** - * @ingroup cpu_k60 - * @{ - * - * @file - * @brief Compatibility definitions between MK60D10.h and MK60DZ10.h - * - * @author Joakim Nohlgård - */ - -#ifndef MK60_COMP_H -#define MK60_COMP_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#if K60_CPU_REV == 1 - -/* Some compatibility defines to minimize the ifdefs needed for the register - * name changes */ - -#define SIM_SCGC6_SPI0_MASK SIM_SCGC6_DSPI0_MASK -#define SIM_SCGC6_SPI0_SHIFT SIM_SCGC6_DSPI0_SHIFT - -#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK -#define MCG_C5_PRDIV0_MASK MCG_C5_PRDIV_MASK -#define MCG_C6_VDIV0_MASK MCG_C6_VDIV_MASK - -#define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 } - -#define LPTMR0_IRQn LPTimer_IRQn - -/* Rev 2.x made the OSC32KSEL field into a bitfield (is a single bit in 1.x) */ -#define SIM_SOPT1_OSC32KSEL(a) (SIM_SOPT1_OSC32KSEL_MASK) - -#endif /* K60_CPU_REV == 1 */ - - -/* Compatibility defines for compatibility with differing module names between - * MK60 and MKW22 headers */ -#define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK -#define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT - -#ifndef OSC0 -/* Compatibility definition */ -#define OSC0 OSC -#endif -#ifndef MCG_C2_RANGE0 -/* Rev 2 parts renamed the parameter RANGE -> RANGE0 */ -#define MCG_C2_RANGE0 MCG_C2_RANGE -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* MK60_COMP_H */ -/** @} */ diff --git a/cpu/k60/include/cpu_conf.h b/cpu/k60/include/cpu_conf.h index 6ba81c4db2..334b300afa 100644 --- a/cpu/k60/include/cpu_conf.h +++ b/cpu/k60/include/cpu_conf.h @@ -31,9 +31,6 @@ extern "C" #include #if defined(CPU_MODEL_K60DN512VLL10) || defined(CPU_MODEL_K60DN256VLL10) - -/* Rev. 2.x silicon */ -#define K60_CPU_REV 2 #include "vendor/MK60D10.h" /** The expected CPUID value, can be used to implement a check that we are @@ -42,27 +39,10 @@ extern "C" /* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */ #define KINETIS_RNGA (RNG) - -#elif defined(CPU_MODEL_K60DN512ZVLL10) || defined(CPU_MODEL_K60DN256ZVLL10) - -/* Rev. 1.x silicon */ -#define K60_CPU_REV 1 -#include "vendor/MK60DZ10.h" - -/** The expected CPUID value, can be used to implement a check that we are - * running on the right hardware */ -#define K60_EXPECTED_CPUID 0x410fc240u - -/* K60 rev 1.x has the cryptographically strong RNGB module */ -#define KINETIS_RNGB (RNG) - #else #error Unknown CPU model. Update Makefile.include in the board directory. #endif -/* Compatibility definitions between the two different Freescale headers */ -#include "MK60-comp.h" - /** * @brief ARM Cortex-M specific CPU configuration * @{ @@ -146,20 +126,12 @@ extern "C" * @name Power mode hardware details */ /** @{ */ -#if K60_CPU_REV == 1 -#define KINETIS_PMCTRL MC->PMCTRL -#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = MC_PMCTRL_LPLLSM(x) | MC_PMCTRL_LPWUI_MASK) +#define KINETIS_PMCTRL SMC->PMCTRL +#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK) /* Clear LLS protection, clear VLPS, VLPW, VLPR protection */ /* Note: This register can only be written once after each reset, so we must * enable all power modes that we wish to use. */ -#define KINETIS_UNLOCK_PMPROT() (MC->PMPROT |= MC_PMPROT_ALLS_MASK | MC_PMPROT_AVLP_MASK) -#elif K60_CPU_REV == 2 -#define KINETIS_PMCTRL SMC->PMCTRL -#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK) #define KINETIS_PMPROT_UNLOCK() (SMC->PMPROT |= SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK) -#else -#error Unknown K60 CPU revision! -#endif /** * @name STOP mode bitfield values diff --git a/cpu/k60/include/vendor/MK60D10.h b/cpu/k60/include/vendor/MK60D10.h index fa77a49f28..0500f52ba8 100644 --- a/cpu/k60/include/vendor/MK60D10.h +++ b/cpu/k60/include/vendor/MK60D10.h @@ -14576,6 +14576,12 @@ typedef struct { #define LPTimer_IRQn LPTMR0_IRQn #define LPTimer_IRQHandler LPTMR0_IRQHandler +/* Compatibility defines for compatibility with differing module names between + * MK60 and MKW22 headers */ +#define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK +#define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT +#define OSC0 OSC + /*! * @} */ /* end of group Backward_Compatibility_Symbols */ diff --git a/cpu/k60/include/vendor/MK60DZ10.h b/cpu/k60/include/vendor/MK60DZ10.h deleted file mode 100644 index 4188c2f279..0000000000 --- a/cpu/k60/include/vendor/MK60DZ10.h +++ /dev/null @@ -1,9247 +0,0 @@ -/* -** ################################################################### -** Processors: MK60DN512ZVLL10 -** MK60DX256ZVLL10 -** MK60DN256ZVLL10 -** MK60DN512ZVLQ10 -** MK60DN256ZVLQ10 -** MK60DX256ZVLQ10 -** MK60DN512ZVMC10 -** MK60DN256ZVMC10 -** MK60DX256ZVMC10 -** MK60DN512ZVMD10 -** MK60DX256ZVMD10 -** MK60DN256ZVMD10 -** -** Compilers: ARM Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manual: K60P144M100SF2RM, Rev. 5, 8 May 2011 -** Version: rev. 1.2, 2011-09-08 -** -** Abstract: -** CMSIS Peripheral Access Layer for MK60DZ10 -** -** Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2011-06-10) -** Initial version. -** Changes with respect to the previous MK60NxxxMD100 header file: -** RTC - CCR register removed. Replaced by IER register. -** CRC - added CTRLHU register for 8-bit access to the CTRL register. -** FB - bit FB_CSCR_EXALE renamed to FB_CSCR_EXTS. -** SIM - bit group FSIZE in SIM_FCFG1 split into groups PFSIZE and NVMSIZE. -** I2S - bit SSIEN in I2S_CR register renamed to I2SEN. -** SDHC - bit VOLTSEL in SDHC_VENDOR register removed. -** - rev. 1.1 (2011-06-29) -** Order of declarations changed. -** - rev. 1.2 (2011-09-08) -** Cortex_Core_Configuration extended with additional parameters. -** Gap between end of interrupt vector table and flash configuration field filled by default ISR. -** - rev. 1.2-jg (2015-05-18) -** Added BITBAND_REG32, BITBAND_REG16, BITBAND_REG8, BITBAND_REGADDR macros from MK60D10.h. -** Removed BITBAND_REG macro. -** -** ################################################################### -*/ - -/** - * @file MK60DZ10.h - * @version 1.2-jg - * @date 2015-05-18 - * @brief CMSIS Peripheral Access Layer for MK60DZ10 - * - * CMSIS Peripheral Access Layer for MK60DZ10 - */ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#if !defined(MK60DZ10_H_) -#define MK60DZ10_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map version 1.2 */ -#define MCU_MEM_MAP_VERSION 0x0102u - -/** - * @brief Macro to calculate address of an aliased word in the peripheral - * bitband area for a peripheral register and bit (bit band region 0x40000000 to - * 0x400FFFFF). - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Address of the aliased word in the peripheral bitband area. - */ -#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 32bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 16bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) -/** - * @brief Macro to access a single bit of a peripheral register (bit band region - * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can - * be used for peripherals with 8bit access allowed. - * @param Reg Register to access. - * @param Bit Bit number to access. - * @return Value of the targeted bit in the bit band region. - */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -typedef enum IRQn { - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - - /* Device specific interrupts */ - DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ - DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ - DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ - DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ - DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ - DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ - DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ - DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ - DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ - DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ - DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ - DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ - DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ - DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ - DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ - DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ - DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ - MCM_IRQn = 17, /**< Normal Interrupt */ - FTFL_IRQn = 18, /**< FTFL Interrupt */ - Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ - LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ - LLW_IRQn = 21, /**< Low Leakage Wakeup */ - Watchdog_IRQn = 22, /**< WDOG Interrupt */ - RNG_IRQn = 23, /**< RNGB Interrupt */ - I2C0_IRQn = 24, /**< I2C0 interrupt */ - I2C1_IRQn = 25, /**< I2C1 interrupt */ - SPI0_IRQn = 26, /**< SPI0 Interrupt */ - SPI1_IRQn = 27, /**< SPI1 Interrupt */ - SPI2_IRQn = 28, /**< SPI2 Interrupt */ - CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd Message Buffers Interrupt */ - CAN0_Bus_Off_IRQn = 30, /**< CAN0 Bus Off Interrupt */ - CAN0_Error_IRQn = 31, /**< CAN0 Error Interrupt */ - CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx Warning Interrupt */ - CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx Warning Interrupt */ - CAN0_Wake_Up_IRQn = 34, /**< CAN0 Wake Up Interrupt */ - Reserved51_IRQn = 35, /**< Reserved interrupt 51 */ - Reserved52_IRQn = 36, /**< Reserved interrupt 52 */ - CAN1_ORed_Message_buffer_IRQn = 37, /**< CAN1 OR'd Message Buffers Interrupt */ - CAN1_Bus_Off_IRQn = 38, /**< CAN1 Bus Off Interrupt */ - CAN1_Error_IRQn = 39, /**< CAN1 Error Interrupt */ - CAN1_Tx_Warning_IRQn = 40, /**< CAN1 Tx Warning Interrupt */ - CAN1_Rx_Warning_IRQn = 41, /**< CAN1 Rx Warning Interrupt */ - CAN1_Wake_Up_IRQn = 42, /**< CAN1 Wake Up Interrupt */ - Reserved59_IRQn = 43, /**< Reserved interrupt 59 */ - Reserved60_IRQn = 44, /**< Reserved interrupt 60 */ - UART0_RX_TX_IRQn = 45, /**< UART0 Receive/Transmit interrupt */ - UART0_ERR_IRQn = 46, /**< UART0 Error interrupt */ - UART1_RX_TX_IRQn = 47, /**< UART1 Receive/Transmit interrupt */ - UART1_ERR_IRQn = 48, /**< UART1 Error interrupt */ - UART2_RX_TX_IRQn = 49, /**< UART2 Receive/Transmit interrupt */ - UART2_ERR_IRQn = 50, /**< UART2 Error interrupt */ - UART3_RX_TX_IRQn = 51, /**< UART3 Receive/Transmit interrupt */ - UART3_ERR_IRQn = 52, /**< UART3 Error interrupt */ - UART4_RX_TX_IRQn = 53, /**< UART4 Receive/Transmit interrupt */ - UART4_ERR_IRQn = 54, /**< UART4 Error interrupt */ - UART5_RX_TX_IRQn = 55, /**< UART5 Receive/Transmit interrupt */ - UART5_ERR_IRQn = 56, /**< UART5 Error interrupt */ - ADC0_IRQn = 57, /**< ADC0 interrupt */ - ADC1_IRQn = 58, /**< ADC1 interrupt */ - CMP0_IRQn = 59, /**< CMP0 interrupt */ - CMP1_IRQn = 60, /**< CMP1 interrupt */ - CMP2_IRQn = 61, /**< CMP2 interrupt */ - FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */ - FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */ - FTM2_IRQn = 64, /**< FTM2 fault, overflow and channels interrupt */ - CMT_IRQn = 65, /**< CMT interrupt */ - RTC_IRQn = 66, /**< RTC interrupt */ - Reserved83_IRQn = 67, /**< Reserved interrupt 83 */ - PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */ - PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */ - PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */ - PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */ - PDB0_IRQn = 72, /**< PDB0 Interrupt */ - USB0_IRQn = 73, /**< USB0 interrupt */ - USBDCD_IRQn = 74, /**< USBDCD Interrupt */ - ENET_1588_Timer_IRQn = 75, /**< Ethernet MAC IEEE 1588 Timer Interrupt */ - ENET_Transmit_IRQn = 76, /**< Ethernet MAC Transmit Interrupt */ - ENET_Receive_IRQn = 77, /**< Ethernet MAC Receive Interrupt */ - ENET_Error_IRQn = 78, /**< Ethernet MAC Error and miscelaneous Interrupt */ - I2S0_IRQn = 79, /**< I2S0 Interrupt */ - SDHC_IRQn = 80, /**< SDHC Interrupt */ - DAC0_IRQn = 81, /**< DAC0 interrupt */ - DAC1_IRQn = 82, /**< DAC1 interrupt */ - TSI0_IRQn = 83, /**< TSI0 Interrupt */ - MCG_IRQn = 84, /**< MCG Interrupt */ - LPTimer_IRQn = 85, /**< LPTimer interrupt */ - Reserved102_IRQn = 86, /**< Reserved interrupt 102 */ - PORTA_IRQn = 87, /**< Port A interrupt */ - PORTB_IRQn = 88, /**< Port B interrupt */ - PORTC_IRQn = 89, /**< Port C interrupt */ - PORTD_IRQn = 90, /**< Port D interrupt */ - PORTE_IRQn = 91, /**< Port E interrupt */ - Reserved108_IRQn = 92, /**< Reserved interrupt 108 */ - Reserved109_IRQn = 93, /**< Reserved interrupt 109 */ - Reserved110_IRQn = 94, /**< Reserved interrupt 110 */ - Reserved111_IRQn = 95, /**< Reserved interrupt 111 */ - Reserved112_IRQn = 96, /**< Reserved interrupt 112 */ - Reserved113_IRQn = 97, /**< Reserved interrupt 113 */ - Reserved114_IRQn = 98, /**< Reserved interrupt 114 */ - Reserved115_IRQn = 99, /**< Reserved interrupt 115 */ - Reserved116_IRQn = 100, /**< Reserved interrupt 116 */ - Reserved117_IRQn = 101, /**< Reserved interrupt 117 */ - Reserved118_IRQn = 102, /**< Reserved interrupt 118 */ - Reserved119_IRQn = 103 /**< Reserved interrupt 119 */ -} IRQn_Type; - -/** - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Configuration of the Cortex-M4 Processor and Core Peripherals - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals - * @{ - */ - -#define __CM4_REV 0x0001 /**< Core revision r0p1 */ -#define __MPU_PRESENT 0 /**< MPU present or not */ -#define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0 /**< FPU present or not */ - -#include "core_cm4.h" /* Core Peripheral Access Layer */ - -/** - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #pragma push - #pragma anon_unions -#elif defined(__CWCC__) - #pragma push - #pragma cpp_extensions on -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ - __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */ - __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */ - __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ - __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */ - __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */ - __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */ - __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */ - __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */ - __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */ - __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */ - __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ - __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ - __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ - __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ - __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ - __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ - __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ - __IO uint32_t PGA; /**< ADC PGA register, offset: 0x50 */ - __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ - __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ - __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ - __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ - __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ - __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ - __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))< MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218 */ - __IO uint32_t RMON_T_FRAG; /**< RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C */ - __IO uint32_t RMON_T_JAB; /**< RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220 */ - __IO uint32_t RMON_T_COL; /**< RMON Tx collision count (RMON_T_COL), offset: 0x224 */ - __IO uint32_t RMON_T_P64; /**< RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228 */ - __IO uint32_t RMON_T_P65TO127; /**< RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C */ - __IO uint32_t RMON_T_P128TO255; /**< RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230 */ - __IO uint32_t RMON_T_P256TO511; /**< RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234 */ - __IO uint32_t RMON_T_P512TO1023; /**< RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238 */ - __IO uint32_t RMON_T_P1024TO2047; /**< RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C */ - __IO uint32_t RMON_T_P_GTE2048; /**< RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240 */ - __IO uint32_t RMON_T_OCTETS; /**< RMON Tx Octets (RMON_T_OCTETS), offset: 0x244 */ - __IO uint32_t IEEE_T_DROP; /**< Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248 */ - __IO uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C */ - __IO uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250 */ - __IO uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254 */ - __IO uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258 */ - __IO uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C */ - __IO uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260 */ - __IO uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264 */ - __IO uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268 */ - __IO uint32_t IEEE_T_SQE; /**< Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C */ - __IO uint32_t IEEE_T_FDXFC; /**< Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270 */ - __IO uint32_t IEEE_T_OCTETS_OK; /**< Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274 */ - uint8_t RESERVED_14[12]; - __IO uint32_t RMON_R_PACKETS; /**< RMON Rx packet count (RMON_R_PACKETS), offset: 0x284 */ - __IO uint32_t RMON_R_BC_PKT; /**< RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288 */ - __IO uint32_t RMON_R_MC_PKT; /**< RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C */ - __IO uint32_t RMON_R_CRC_ALIGN; /**< RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290 */ - __IO uint32_t RMON_R_UNDERSIZE; /**< RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294 */ - __IO uint32_t RMON_R_OVERSIZE; /**< RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298 */ - __IO uint32_t RMON_R_FRAG; /**< RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C */ - __IO uint32_t RMON_R_JAB; /**< RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0 */ - __IO uint32_t RMON_R_RESVD_0; /**< Reserved (RMON_R_RESVD_0), offset: 0x2A4 */ - __IO uint32_t RMON_R_P64; /**< RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8 */ - __IO uint32_t RMON_R_P65TO127; /**< RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC */ - __IO uint32_t RMON_R_P128TO255; /**< RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0 */ - __IO uint32_t RMON_R_P256TO511; /**< RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4 */ - __IO uint32_t RMON_R_P512TO1023; /**< RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8 */ - __IO uint32_t RMON_R_P1024TO2047; /**< RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC */ - __IO uint32_t RMON_R_P_GTE2048; /**< RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0 */ - __IO uint32_t RMON_R_OCTETS; /**< RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4 */ - __IO uint32_t RMON_R_DROP; /**< Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8 */ - __IO uint32_t RMON_R_FRAME_OK; /**< Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC */ - __IO uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0 */ - __IO uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4 */ - __IO uint32_t IEEE_R_MACERR; /**< Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8 */ - __IO uint32_t IEEE_R_FDXFC; /**< Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC */ - __IO uint32_t IEEE_R_OCTETS_OK; /**< Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0 */ - uint8_t RESERVED_15[284]; - __IO uint32_t ATCR; /**< Timer Control Register, offset: 0x400 */ - __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ - __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ - __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ - __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ - __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ - __IO uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ - uint8_t RESERVED_16[488]; - __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ - struct { /* offset: 0x608, array step: 0x8 */ - __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ - __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ - } CHANNEL[4]; -} ENET_Type; - -/* ---------------------------------------------------------------------------- - -- ENET Register Masks - ---------------------------------------------------------------------------- */ - -/** - * @addtogroup ENET_Register_Masks ENET Register Masks - * @{ - */ - -/* EIR Bit Fields */ -#define ENET_EIR_TS_TIMER_MASK 0x8000u -#define ENET_EIR_TS_TIMER_SHIFT 15 -#define ENET_EIR_TS_AVAIL_MASK 0x10000u -#define ENET_EIR_TS_AVAIL_SHIFT 16 -#define ENET_EIR_WAKEUP_MASK 0x20000u -#define ENET_EIR_WAKEUP_SHIFT 17 -#define ENET_EIR_PLR_MASK 0x40000u -#define ENET_EIR_PLR_SHIFT 18 -#define ENET_EIR_UN_MASK 0x80000u -#define ENET_EIR_UN_SHIFT 19 -#define ENET_EIR_RL_MASK 0x100000u -#define ENET_EIR_RL_SHIFT 20 -#define ENET_EIR_LC_MASK 0x200000u -#define ENET_EIR_LC_SHIFT 21 -#define ENET_EIR_EBERR_MASK 0x400000u -#define ENET_EIR_EBERR_SHIFT 22 -#define ENET_EIR_MII_MASK 0x800000u -#define ENET_EIR_MII_SHIFT 23 -#define ENET_EIR_RXB_MASK 0x1000000u -#define ENET_EIR_RXB_SHIFT 24 -#define ENET_EIR_RXF_MASK 0x2000000u -#define ENET_EIR_RXF_SHIFT 25 -#define ENET_EIR_TXB_MASK 0x4000000u -#define ENET_EIR_TXB_SHIFT 26 -#define ENET_EIR_TXF_MASK 0x8000000u -#define ENET_EIR_TXF_SHIFT 27 -#define ENET_EIR_GRA_MASK 0x10000000u -#define ENET_EIR_GRA_SHIFT 28 -#define ENET_EIR_BABT_MASK 0x20000000u -#define ENET_EIR_BABT_SHIFT 29 -#define ENET_EIR_BABR_MASK 0x40000000u -#define ENET_EIR_BABR_SHIFT 30 -/* EIMR Bit Fields */ -#define ENET_EIMR_TS_TIMER_MASK 0x8000u -#define ENET_EIMR_TS_TIMER_SHIFT 15 -#define ENET_EIMR_TS_AVAIL_MASK 0x10000u -#define ENET_EIMR_TS_AVAIL_SHIFT 16 -#define ENET_EIMR_WAKEUP_MASK 0x20000u -#define ENET_EIMR_WAKEUP_SHIFT 17 -#define ENET_EIMR_PLR_MASK 0x40000u -#define ENET_EIMR_PLR_SHIFT 18 -#define ENET_EIMR_UN_MASK 0x80000u -#define ENET_EIMR_UN_SHIFT 19 -#define ENET_EIMR_RL_MASK 0x100000u -#define ENET_EIMR_RL_SHIFT 20 -#define ENET_EIMR_LC_MASK 0x200000u -#define ENET_EIMR_LC_SHIFT 21 -#define ENET_EIMR_EBERR_MASK 0x400000u -#define ENET_EIMR_EBERR_SHIFT 22 -#define ENET_EIMR_MII_MASK 0x800000u -#define ENET_EIMR_MII_SHIFT 23 -#define ENET_EIMR_RXB_MASK 0x1000000u -#define ENET_EIMR_RXB_SHIFT 24 -#define ENET_EIMR_RXF_MASK 0x2000000u -#define ENET_EIMR_RXF_SHIFT 25 -#define ENET_EIMR_TXB_MASK 0x4000000u -#define ENET_EIMR_TXB_SHIFT 26 -#define ENET_EIMR_TXF_MASK 0x8000000u -#define ENET_EIMR_TXF_SHIFT 27 -#define ENET_EIMR_GRA_MASK 0x10000000u -#define ENET_EIMR_GRA_SHIFT 28 -#define ENET_EIMR_BABT_MASK 0x20000000u -#define ENET_EIMR_BABT_SHIFT 29 -#define ENET_EIMR_BABR_MASK 0x40000000u -#define ENET_EIMR_BABR_SHIFT 30 -/* RDAR Bit Fields */ -#define ENET_RDAR_RDAR_MASK 0x1000000u -#define ENET_RDAR_RDAR_SHIFT 24 -/* TDAR Bit Fields */ -#define ENET_TDAR_TDAR_MASK 0x1000000u -#define ENET_TDAR_TDAR_SHIFT 24 -/* ECR Bit Fields */ -#define ENET_ECR_RESET_MASK 0x1u -#define ENET_ECR_RESET_SHIFT 0 -#define ENET_ECR_ETHEREN_MASK 0x2u -#define ENET_ECR_ETHEREN_SHIFT 1 -#define ENET_ECR_MAGICEN_MASK 0x4u -#define ENET_ECR_MAGICEN_SHIFT 2 -#define ENET_ECR_SLEEP_MASK 0x8u -#define ENET_ECR_SLEEP_SHIFT 3 -#define ENET_ECR_EN1588_MASK 0x10u -#define ENET_ECR_EN1588_SHIFT 4 -#define ENET_ECR_DBGEN_MASK 0x40u -#define ENET_ECR_DBGEN_SHIFT 6 -#define ENET_ECR_STOPEN_MASK 0x80u -#define ENET_ECR_STOPEN_SHIFT 7 -/* MMFR Bit Fields */ -#define ENET_MMFR_DATA_MASK 0xFFFFu -#define ENET_MMFR_DATA_SHIFT 0 -#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<