From 03ee0c938fe8f39f374bc307398e5151fd06bb3d Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 30 Aug 2020 16:54:57 +0200 Subject: [PATCH 1/5] cpu/stm32: adapt Kconfig clock configuration for f0 --- cpu/stm32/kconfigs/Kconfig.clk | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/cpu/stm32/kconfigs/Kconfig.clk b/cpu/stm32/kconfigs/Kconfig.clk index 8c6a79cbad..00da93e42a 100644 --- a/cpu/stm32/kconfigs/Kconfig.clk +++ b/cpu/stm32/kconfigs/Kconfig.clk @@ -6,7 +6,7 @@ # menu "STM32 clock configuration" - depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB + depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_F0 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB choice bool "Clock source selection" @@ -47,11 +47,11 @@ endchoice endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB -if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CUSTOM_PLL_PARAMS bool "Configure PLL parameters" depends on USE_CLOCK_PLL +if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CLOCK_PLL_M int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS default 1 if CPU_FAM_G0 @@ -112,6 +112,20 @@ endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 endif # CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB +if CPU_FAM_F0 +config CLOCK_PLL_PREDIV + int "PLLIN division factor" if USE_CLOCK_PLL && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6 + default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 + default 1 + range 1 16 + +config CLOCK_PLL_MUL + int "PLLIN multiply factor" if USE_CLOCK_PLL + default 12 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 + default 6 + range 2 16 +endif + if CPU_FAM_L0 || CPU_FAM_L1 config CLOCK_PLL_DIV int "Main PLL division factor" if USE_CLOCK_PLL From 6e9a433c9a3c521dcb9aa23d0d22255d9ab94376 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 30 Aug 2020 17:00:51 +0200 Subject: [PATCH 2/5] boards/stm32f0*: adapt Kconfig for clock configuration --- boards/nucleo-f030r8/Kconfig | 4 ++++ boards/nucleo-f070rb/Kconfig | 4 ++++ boards/nucleo-f072rb/Kconfig | 4 ++++ boards/nucleo-f091rc/Kconfig | 4 ++++ boards/stm32f030f4-demo/Kconfig | 5 +++++ boards/stm32f0discovery/Kconfig | 5 +++++ 6 files changed, 26 insertions(+) diff --git a/boards/nucleo-f030r8/Kconfig b/boards/nucleo-f030r8/Kconfig index 5196350ec8..f4064bd6c4 100644 --- a/boards/nucleo-f030r8/Kconfig +++ b/boards/nucleo-f030r8/Kconfig @@ -21,4 +21,8 @@ config BOARD_NUCLEO_F030R8 select HAS_PERIPH_TIMER select HAS_PERIPH_UART + # Clock configuration + select BOARD_HAS_HSE + select BOARD_HAS_LSE + source "$(RIOTBOARD)/common/nucleo64/Kconfig" diff --git a/boards/nucleo-f070rb/Kconfig b/boards/nucleo-f070rb/Kconfig index d7247820d2..9df46ca453 100644 --- a/boards/nucleo-f070rb/Kconfig +++ b/boards/nucleo-f070rb/Kconfig @@ -22,4 +22,8 @@ config BOARD_NUCLEO_F070RB select HAS_PERIPH_TIMER select HAS_PERIPH_UART + # Clock configuration + select BOARD_HAS_HSE + select BOARD_HAS_LSE + source "$(RIOTBOARD)/common/nucleo64/Kconfig" diff --git a/boards/nucleo-f072rb/Kconfig b/boards/nucleo-f072rb/Kconfig index 33e28d9261..6b53f38ac1 100644 --- a/boards/nucleo-f072rb/Kconfig +++ b/boards/nucleo-f072rb/Kconfig @@ -23,4 +23,8 @@ config BOARD_NUCLEO_F072RB select HAS_PERIPH_UART select HAS_PERIPH_SPI + # Clock configuration + select BOARD_HAS_HSE + select BOARD_HAS_LSE + source "$(RIOTBOARD)/common/nucleo64/Kconfig" diff --git a/boards/nucleo-f091rc/Kconfig b/boards/nucleo-f091rc/Kconfig index b85c71dcfd..abbb15df08 100644 --- a/boards/nucleo-f091rc/Kconfig +++ b/boards/nucleo-f091rc/Kconfig @@ -22,4 +22,8 @@ config BOARD_NUCLEO_F091RC select HAS_PERIPH_UART select HAS_PERIPH_SPI + # Clock configuration + select BOARD_HAS_HSE + select BOARD_HAS_LSE + source "$(RIOTBOARD)/common/nucleo64/Kconfig" diff --git a/boards/stm32f030f4-demo/Kconfig b/boards/stm32f030f4-demo/Kconfig index 85788cae69..8f6b5b221e 100644 --- a/boards/stm32f030f4-demo/Kconfig +++ b/boards/stm32f030f4-demo/Kconfig @@ -20,3 +20,8 @@ config BOARD_STM32F030F4_DEMO select HAS_PERIPH_UART select HAS_PERIPH_SPI select HAS_PERIPH_RTC + + # Clock configuration + select BOARD_HAS_HSE + +source "$(RIOTBOARD)/common/stm32/Kconfig" diff --git a/boards/stm32f0discovery/Kconfig b/boards/stm32f0discovery/Kconfig index 5bc2882d89..9922c547d6 100644 --- a/boards/stm32f0discovery/Kconfig +++ b/boards/stm32f0discovery/Kconfig @@ -19,3 +19,8 @@ config BOARD_STM32F0DISCOVERY select HAS_PERIPH_SPI select HAS_PERIPH_TIMER select HAS_PERIPH_UART + + # Clock configuration + select BOARD_HAS_HSE + +source "$(RIOTBOARD)/common/stm32/Kconfig" From 5d77b7d90d3022ca803220c147ab45067f1862e3 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Tue, 10 Nov 2020 11:42:11 +0100 Subject: [PATCH 3/5] cpu/stm32: show PLL params in menuconfig with CUSTOM_PLL_PARAMS --- cpu/stm32/kconfigs/Kconfig.clk | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/cpu/stm32/kconfigs/Kconfig.clk b/cpu/stm32/kconfigs/Kconfig.clk index 00da93e42a..2c1af9bdc9 100644 --- a/cpu/stm32/kconfigs/Kconfig.clk +++ b/cpu/stm32/kconfigs/Kconfig.clk @@ -114,13 +114,13 @@ endif # CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB if CPU_FAM_F0 config CLOCK_PLL_PREDIV - int "PLLIN division factor" if USE_CLOCK_PLL && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6 + int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6 default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 default 1 range 1 16 config CLOCK_PLL_MUL - int "PLLIN multiply factor" if USE_CLOCK_PLL + int "PLLIN multiply factor" if CUSTOM_PLL_PARAMS default 12 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 default 6 range 2 16 @@ -128,12 +128,12 @@ endif if CPU_FAM_L0 || CPU_FAM_L1 config CLOCK_PLL_DIV - int "Main PLL division factor" if USE_CLOCK_PLL + int "Main PLL division factor" if CUSTOM_PLL_PARAMS default 2 range 2 4 choice -bool "Main PLL multiply factor" if USE_CLOCK_PLL +bool "Main PLL multiply factor" if CUSTOM_PLL_PARAMS default PLL_MUL_4 config PLL_MUL_3 From 9d13c07e92f25b94ac41d8eb582f4d23933d9790 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Tue, 10 Nov 2020 14:34:44 +0100 Subject: [PATCH 4/5] cpu/stm32f0: handle custom pll prediv/mul at cpu level --- cpu/stm32/include/clk/f0/cfg_clock_default.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/cpu/stm32/include/clk/f0/cfg_clock_default.h b/cpu/stm32/include/clk/f0/cfg_clock_default.h index f13ea8b0d7..d380e973e6 100644 --- a/cpu/stm32/include/clk/f0/cfg_clock_default.h +++ b/cpu/stm32/include/clk/f0/cfg_clock_default.h @@ -78,13 +78,23 @@ extern "C" { #define CLOCK_HSI MHZ(8) -/* The following parameters configure a 48MHz system clock with HSI (or default HSE) as input clock */ +/* The following parameters configure a 48MHz system clock with HSI (or default HSE) as input clock +On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is hard-wired to 2, +so to reach 48MHz set PLL_PREDIV to 2 and PLL_MUL to 12 so core clock = (HSI8 / 2) * 12 = 48MHz */ #ifndef CONFIG_CLOCK_PLL_PREDIV +#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6) +#define CONFIG_CLOCK_PLL_PREDIV (2) +#else #define CONFIG_CLOCK_PLL_PREDIV (1) #endif +#endif #ifndef CONFIG_CLOCK_PLL_MUL +#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6) +#define CONFIG_CLOCK_PLL_MUL (12) +#else #define CONFIG_CLOCK_PLL_MUL (6) #endif +#endif #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) #define CLOCK_CORECLOCK (CLOCK_HSI) From c4269ffefca930b0c12bcac029194cfc7c91a47c Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Tue, 10 Nov 2020 14:35:16 +0100 Subject: [PATCH 5/5] boards/nucleo-f0*: remove custom pll prediv/mul defines --- boards/nucleo-f031k6/include/periph_conf.h | 8 -------- boards/nucleo-f042k6/include/periph_conf.h | 8 -------- 2 files changed, 16 deletions(-) diff --git a/boards/nucleo-f031k6/include/periph_conf.h b/boards/nucleo-f031k6/include/periph_conf.h index e7f5da4bcb..a51f9814b2 100644 --- a/boards/nucleo-f031k6/include/periph_conf.h +++ b/boards/nucleo-f031k6/include/periph_conf.h @@ -20,14 +20,6 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H -/* Adjust PLL factors: - - On nucleo-f031k6, there's no HSE and PREDIV is hard-wired to 2 - - to reach 48MHz set PLL_MUL to 12 so core clock = (HSI8 / 2) * 12 = 48MHz */ -#define CONFIG_CLOCK_PLL_PREDIV (2) -#ifndef CONFIG_CLOCK_PLL_MUL -#define CONFIG_CLOCK_PLL_MUL (12) -#endif - #include "periph_cpu.h" #include "f0/cfg_clock_default.h" #include "cfg_timer_tim2.h" diff --git a/boards/nucleo-f042k6/include/periph_conf.h b/boards/nucleo-f042k6/include/periph_conf.h index e409716013..f70473b546 100644 --- a/boards/nucleo-f042k6/include/periph_conf.h +++ b/boards/nucleo-f042k6/include/periph_conf.h @@ -19,14 +19,6 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H -/* Adjust PLL factors: - - On nucleo-f042k6, there's no HSE and PREDIV is hard-wired to 2 - - to reach 48MHz set PLL_MUL to 12 so core clock = (HSI8 / 2) * 12 = 48MHz */ -#define CONFIG_CLOCK_PLL_PREDIV (2) -#ifndef CONFIG_CLOCK_PLL_MUL -#define CONFIG_CLOCK_PLL_MUL (12) -#endif - #include "periph_cpu.h" #include "f0/cfg_clock_default.h" #include "cfg_timer_tim2.h"