boards: add support for i-nucleo-lrwan1

boards/i-nucleo-lrwan1/Makefile

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+MODULE = board
+
+include $(RIOTBASE)/Makefile.base

boards/i-nucleo-lrwan1/Makefile.dep

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+FEATURES_REQUIRED += periph_lpuart
+
+ifneq (,$(filter netdev_default,$(USEMODULE)))
+  USEMODULE += sx1272
+endif

boards/i-nucleo-lrwan1/Makefile.features

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+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_lpuart
+FEATURES_PROVIDED += periph_rtc
+FEATURES_PROVIDED += periph_rtt
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = cortex_m0_1
+
+include $(RIOTCPU)/stm32l0/Makefile.features

boards/i-nucleo-lrwan1/Makefile.include

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+## the cpu to build for
+export CPU = stm32l0
+export CPU_MODEL = stm32l052t8
+
+# we use shared STM32 configuration snippets
+INCLUDES += -I$(RIOTBOARD)/common/stm32/include
+
+# define the default port depending on the host OS
+PORT_LINUX ?= /dev/ttyACM0
+PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
+
+# setup serial terminal
+include $(RIOTMAKE)/tools/serial.inc.mk
+
+# to flash this board, use an ST-link adapter
+export DEBUG_ADAPTER ?= stlink
+
+# call a 'reset halt' command before starting the debugger
+export OPENOCD_DBG_START_CMD = -c 'reset halt'
+
+# this board uses openocd
+include $(RIOTMAKE)/tools/openocd.inc.mk

boards/i-nucleo-lrwan1/board.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2019 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_i-nucleo-lrwan1
+ * @{
+ *
+ * @file
+ * @brief       Board specific implementations for the ST I-NUCLEO-LRWAN1 board
+ *
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "periph/gpio.h"
+
+
+void board_init(void)
+{
+    /* initialize the CPU */
+    cpu_init();
+}

boards/i-nucleo-lrwan1/doc.txt

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+/**
+@defgroup    boards_i-nucleo-lrwan1 ST I-NUCLEO-LRWAN1 LoRa board
+@ingroup     boards
+@brief       Support for the ST I-NUCLEO-LRWAN1 LoRa board shield
+
+## Description
+
+<img src="https://www.st.com/content/ccc/fragment/product_related/rpn_information/board_photo/group0/d0/d8/be/59/bb/0f/42/d9/i-nucleo-lrwan1.jpg/files/i-nucleo-lrwan1.jpg/_jcr_content/translations/en.i-nucleo-lrwan1.jpg"
+     alt="I-NUCLEO-LRWAN1" style="width:400px;"/>
+
+The [I-NUCLEO-LRWAN1](https://www.st.com/en/evaluation-tools/i-nucleo-lrwan1.html)
+board provides LoRa connectivity with an SX1272 radio connected via SPI
+to an ultra-low power
+[STM32L052T8](https://www.st.com/en/microcontrollers-microprocessors/stm32l052t8.html).
+microcontroller.
+
+For details, the
+[schematics are available on GitHub](https://github.com/USIWP1Module/USI_I-NUCLEO-LRWAN1/blob/master/Schematics/USI%20LoRa%20Arduino%20shield_SCH_20161115-1.pdf).
+
+_Note_: to use the on-board I2C sensors, the R19 and R20 shorts must be closed
+(soldered).
+
+## Flashing the board
+
+To flash, one needs to use an external ST-Link programmer connected to SWD pins
+of the JP6 connector.
+
+By default, the flash on the microcontroller is write protected so before being
+able to flash it, one needs to unlock using the following:
+- Apply the following patch to the `openocd.sh` script:
+```diff
+diff --git a/dist/tools/openocd/openocd.sh b/dist/tools/openocd/openocd.sh
+index c59a1939a2..0c359e438c 100755
+--- a/dist/tools/openocd/openocd.sh
++++ b/dist/tools/openocd/openocd.sh
+@@ -248,6 +248,11 @@ do_flash() {
+             -c 'init' \
+             -c 'targets' \
+             -c 'reset halt' \
++            -c 'stm32lx unlock 0' \
++            -c 'reset halt' \
++            -c 'init' \
++            -c 'targets' \
++            -c 'reset halt' \
+             ${OPENOCD_PRE_FLASH_CMDS} \
+             -c 'flash write_image erase \"${IMAGE_FILE}\" ${IMAGE_OFFSET} ${IMAGE_TYPE}' \
+             ${OPENOCD_PRE_VERIFY_CMDS} \
+```
+- Run make flash:
+```sh
+make BOARD=i-nucleo-lrwan1 -C examples/hello-world flash
+```
+  The command will fail but after that the memory will be unlocked after a
+  power cycle. The line added above in `openocd.sh` can also be removed.
+- Unplug the board and replug-it: the board is now flashable normally.
+
+Note that this unlock procedure only needs to be done once.
+
+## Accessing STDIO
+
+STDIO is available on pin 0 and 1 on CN9 so one needs an USB to UART to connect
+to STDIO.
+
+When flashing using an ST-Link, STDIO pins can be plugged directly to the RX/TX
+pins on the programmer, STDIO is then accessible like on any Nucleo boards.
+
+ */

boards/i-nucleo-lrwan1/include/board.h

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+/*
+ * Copyright (C) 2019 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_i-nucleo-lrwan1
+ * @{
+ *
+ * @file
+ * @brief       Board specific definitions for the ST I-NUCLEO-LRWAN1 board
+ *
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include <stdint.h>
+
+#include "cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    xtimer configuration
+ * @{
+ */
+#define XTIMER_WIDTH        (16)
+/** @} */
+
+/**
+ * @name    SX1272 configuration
+ * @{
+ **/
+#define SX127X_PARAM_SPI_NSS                GPIO_PIN(PORT_A, 15)
+#define SX127X_PARAM_RESET                  GPIO_PIN(PORT_A, 9)
+#define SX127X_PARAM_DIO0                   GPIO_PIN(PORT_A, 2)
+#define SX127X_PARAM_DIO1                   GPIO_PIN(PORT_A, 3)
+#define SX127X_PARAM_DIO2                   GPIO_PIN(PORT_A, 5)
+#define SX127X_PARAM_DIO3                   GPIO_PIN(PORT_A, 6)
+#define SX127X_PARAM_PASELECT               (SX127X_PA_BOOST)
+/** @} */
+
+/**
+ * @brief   Initialize board specific hardware, including clock, LEDs and std-IO
+ */
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H */
+/** @} */

boards/i-nucleo-lrwan1/include/periph_conf.h

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+/*
+ * Copyright (C) 2019 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_i-nucleo-lrwan1
+ * @{
+ *
+ * @file
+ * @brief       Peripheral MCU configuration for the ST I-NUCLEO-LRWAN1 board
+ *
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+#include "periph_cpu.h"
+#include "cfg_rtt_default.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    Clock system configuration
+ * @{
+ */
+#define CLOCK_HSI           (16000000U)         /* internal oscillator */
+#define CLOCK_CORECLOCK     (32000000U)         /* desired core clock frequency */
+#define CLOCK_LSE           (1)                 /* enable low speed external oscillator */
+
+/* configuration of PLL prescaler and multiply values */
+/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
+#define CLOCK_PLL_DIV       RCC_CFGR_PLLDIV2
+#define CLOCK_PLL_MUL       RCC_CFGR_PLLMUL4
+/* configuration of peripheral bus clock prescalers */
+#define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1      /* AHB clock -> 32MHz */
+#define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1     /* APB2 clock -> 32MHz */
+#define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV1     /* APB1 clock -> 32MHz */
+/* configuration of flash access cycles */
+#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 1)
+/** @} */
+
+/**
+ * @name    Timer configuration
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0x0000ffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    }
+};
+
+#define TIMER_0_ISR         isr_tim2
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
+/** @} */
+
+/**
+ * @name    UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+    {
+        .dev        = LPUART1,
+        .rcc_mask   = RCC_APB1ENR_LPUART1EN,
+        .rx_pin     = GPIO_PIN(PORT_B, 11),
+        .tx_pin     = GPIO_PIN(PORT_B, 10),
+        .rx_af      = GPIO_AF4,
+        .tx_af      = GPIO_AF4,
+        .bus        = APB1,
+        .irqn       = LPUART1_IRQn,
+        .type       = STM32_LPUART,
+        .clk_src    = 0, /* Use APB clock */
+    },
+};
+
+#define UART_0_ISR          (isr_rng_lpuart1)
+
+#define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))
+/** @} */
+
+/**
+ * @name    SPI configuration
+ *
+ * @note    The spi_divtable is auto-generated from
+ *          `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
+ * @{
+ */
+static const uint8_t spi_divtable[2][5] = {
+    {       /* for APB1 @ 32000000Hz */
+        7,  /* -> 125000Hz */
+        5,  /* -> 500000Hz */
+        4,  /* -> 1000000Hz */
+        2,  /* -> 4000000Hz */
+        1   /* -> 8000000Hz */
+    },
+    {       /* for APB2 @ 32000000Hz */
+        7,  /* -> 125000Hz */
+        5,  /* -> 500000Hz */
+        4,  /* -> 1000000Hz */
+        2,  /* -> 4000000Hz */
+        1   /* -> 8000000Hz */
+    }
+};
+
+static const spi_conf_t spi_config[] = {
+    {
+        .dev      = SPI1, /* connected to SX1272 */
+        .mosi_pin = GPIO_PIN(PORT_A, 12),
+        .miso_pin = GPIO_PIN(PORT_B, 4),
+        .sclk_pin = GPIO_PIN(PORT_B, 3),
+        .cs_pin   = GPIO_PIN(PORT_A, 15),
+        .af       = GPIO_AF0,
+        .rccmask  = RCC_APB2ENR_SPI1EN,
+        .apbbus   = APB2,
+    },
+};
+
+#define SPI_NUMOF           (sizeof(spi_config) / sizeof(spi_config[0]))
+/** @} */
+
+/**
+ * @name I2C configuration
+ * @{
+ */
+static const i2c_conf_t i2c_config[] = {
+    {
+        .dev            = I2C1,
+        .speed          = I2C_SPEED_NORMAL,
+        .scl_pin        = GPIO_PIN(PORT_B, 6),
+        .sda_pin        = GPIO_PIN(PORT_B, 7),
+        .scl_af         = GPIO_AF1,
+        .sda_af         = GPIO_AF1,
+        .bus            = APB1,
+        .rcc_mask       = RCC_APB1ENR_I2C1EN,
+        .irqn           = I2C1_IRQn
+    }
+};
+
+#define I2C_0_ISR           isr_i2c1
+
+#define I2C_NUMOF           (sizeof(i2c_config) / sizeof(i2c_config[0]))
+/** @} */
+
+/**
+ * @name    RTC configuration
+ * @{
+ */
+#define RTC_NUMOF           (1U)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */