From 5f355e7210c45b68b4faea8e6f716b64e322019f Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Wed, 24 Apr 2019 16:29:30 +0200 Subject: [PATCH] cpu/arm7_common: Make irq_*() compiler barriers Previously the compiler was allowed to reorder access to the interrupt control registers in regard to memory access not marked as `volatile` (at least some people - most notably some compiler developers - read the C standard this way). In practise this did not happen as irq_disable(), irq_restore(), irq_enable() are part of a separate compilation unit: Calls to external functions unknown to the compiler are treated as if they were memory barriers. But if link time optimization (LTO) is enabled, this no longer would work: The compiler could inline the code accessing the interrupt control registers and reorder the memory accesses wrapped in irq_disable() and irq_restore() outside of their protection. This commit adds the "memory" clobber to the inline assembly accessing the interrupt control registers. This makes those accesses explicit compiler memory barriers. The machine code generated without LTO enabled should not differ in any way by this commit. But the use of irq_*() should now be safe with LTO. --- cpu/arm7_common/VIC.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu/arm7_common/VIC.c b/cpu/arm7_common/VIC.c index 53f7bcf12b..90897be324 100644 --- a/cpu/arm7_common/VIC.c +++ b/cpu/arm7_common/VIC.c @@ -14,20 +14,20 @@ static inline unsigned __get_cpsr(void) { unsigned long retval; - __asm__ volatile(" mrs %0, cpsr" : "=r"(retval) : /* no inputs */); + __asm__ volatile(" mrs %0, cpsr" : "=r"(retval) : /* no inputs */ : "memory"); return retval; } int irq_is_in(void) { int retval; - __asm__ volatile(" mrs %0, cpsr" : "=r"(retval) : /* no inputs */); + __asm__ volatile(" mrs %0, cpsr" : "=r"(retval) : /* no inputs */ : "memory"); return (retval & INTMode) == 18; } static inline void __set_cpsr(unsigned val) { - __asm__ volatile(" msr cpsr, %0" : /* no outputs */ : "r"(val)); + __asm__ volatile(" msr cpsr, %0" : /* no outputs */ : "r"(val) : "memory"); } unsigned irq_disable(void)