From 2f503f11fafb6ceda55aa14864d3d8a1dc4449ae Mon Sep 17 00:00:00 2001 From: Jue Date: Mon, 12 Apr 2021 17:01:33 +0200 Subject: [PATCH] cpu/stm32/gpio_all: fix IRQ handler for G0/L5/MP1 families --- cpu/stm32/periph/gpio_all.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/cpu/stm32/periph/gpio_all.c b/cpu/stm32/periph/gpio_all.c index 560909e5f3..eda691bef9 100644 --- a/cpu/stm32/periph/gpio_all.c +++ b/cpu/stm32/periph/gpio_all.c @@ -338,15 +338,16 @@ void isr_exti(void) { #if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \ defined(CPU_FAM_STM32MP1) - /* only generate interrupts against lines which have their IMR set */ - uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_REG_IMR & EXTI_MASK); - uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_REG_IMR & EXTI_MASK); + /* get all interrupts handled by this ISR */ + uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_MASK); + uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_MASK); /* clear by writing a 1 */ EXTI->RPR1 = pending_rising_isr; EXTI->FPR1 = pending_falling_isr; - uint32_t pending_isr = pending_rising_isr | pending_falling_isr; + /* only generate interrupts against lines which have their IMR set */ + uint32_t pending_isr = (pending_rising_isr | pending_falling_isr) & EXTI_REG_IMR; #else /* read all pending interrupts wired to isr_exti */ uint32_t pending_isr = (EXTI_REG_PR & EXTI_MASK);