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boards/nucleo-f767zi: Add SPI settings

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This commit is contained in:
Marian Buschsieweke 2019-03-25 13:06:39 +01:00
parent d00becbc4b
commit 61e1068eba
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GPG Key ID: 61F64C6599B1539F
2 changed files with 25 additions and 0 deletions
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1
boards/nucleo-f767zi/Makefile.features
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@ -2,6 +2,7 @@
FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_dma
FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_rtc FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart FEATURES_PROVIDED += periph_uart

24
boards/nucleo-f767zi/include/periph_conf.h
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@ -24,6 +24,7 @@
#include "periph_cpu.h" #include "periph_cpu.h"
#include "f7/cfg_clock_216_8_1.h" #include "f7/cfg_clock_216_8_1.h"
#include "cfg_i2c1_pb8_pb9.h" #include "cfg_i2c1_pb8_pb9.h"
#include "cfg_spi_divtable.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -123,6 +124,29 @@ static const uart_conf_t uart_config[] = {
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */ /** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif