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cpu/stm32: Use mii.h for periph_eth

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Use shared MII definitions and utilities instead own definitions.
This commit is contained in:
Marian Buschsieweke 2020-10-09 20:10:14 +02:00
parent 33d916b237
commit 6294382627
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GPG Key ID: 61F64C6599B1539F
3 changed files with 35 additions and 135 deletions
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139
cpu/stm32/include/periph_cpu.h
View File

@ -1018,34 +1018,24 @@ void dma_prepare(dma_t dma, void *mem, size_t len, bool incr_mem);
* @brief STM32 Ethernet configuration mode
*/
typedef enum {
MII = 18, /**< Configuration for MII */
RMII = 9, /**< Configuration for RMII */
SMI = 2, /**< Configuration for SMI */
MII = 18, /**< Configuration for MII */
RMII = 9, /**< Configuration for RMII */
SMI = 2, /**< Configuration for SMI */
} eth_mode_t;
/**
* @brief STM32 Ethernet speed options
*/
typedef enum {
ETH_SPEED_10T_HD = 0x0000,
ETH_SPEED_10T_FD = 0x0100,
ETH_SPEED_100TX_HD = 0x2000,
ETH_SPEED_100TX_FD = 0x2100,
} eth_speed_t;
/**
* @brief Ethernet Peripheral configuration
*/
typedef struct {
eth_mode_t mode; /**< Select configuration mode */
uint8_t addr[6]; /**< Ethernet MAC address */
eth_speed_t speed; /**< Speed selection */
uint16_t speed; /**< Speed selection */
uint8_t dma; /**< Locical CMA Descriptor used for TX */
uint8_t dma_chan; /**< DMA channel used for TX */
char phy_addr; /**< PHY address */
uint8_t phy_addr; /**< PHY address */
gpio_t pins[]; /**< Pins to use. MII requires 18 pins,
RMII 9 and SMI 9. Not all speeds are
supported by all modes. */
RMII 9 and SMI 9. Not all speeds are
supported by all modes. */
} eth_conf_t;
/**
@ -1144,121 +1134,6 @@ typedef struct eth_dma_desc {
#define TX_DESC_STAT_OWN (BIT31) /**< If set, descriptor is owned by DMA, otherwise by CPU */
/** @} */
/**
* @name Ethernet PHY Common Registers
* @{
*/
#define PHY_BMCR (0x00)
#define PHY_BSMR (0x01)
#define PHY_PHYIDR1 (0x02)
#define PHY_PHYIDR2 (0x03)
#define PHY_ANAR (0x04)
#define PHY_ANLPAR (0x05)
#define PHY_ANER (0x06)
#define PHY_ANNPTR (0x07)
/** @} */
/**
* @name Ethernet PHY BMCR Fields
* @{
*/
#define BMCR_RESET (0x8000)
#define BMCR_LOOPBACK (0x4000)
#define BMCR_SPEED_SELECT (0x2000)
#define BMCR_AN (0x1000)
#define BMCR_POWER_DOWN (0x0800)
#define BMCR_ISOLATE (0x0400)
#define BMCR_RESTART_AN (0x0200)
#define BMCR_DUPLEX_MODE (0x0100)
#define BMCR_COLLISION_TEST (0x0080)
/** @} */
/**
* @name Ethernet PHY BSMR Fields
* @{
*/
#define BSMR_100BASE_T4 (0x8000)
#define BSMR_100BASE_TX_FDUPLEX (0x4000)
#define BSMR_100BASE_TX_HDUPLEX (0x2000)
#define BSMR_10BASE_T_FDUPLEX (0x1000)
#define BSMR_10BASE_T_HDUPLEX (0x0800)
#define BSMR_NO_PREAMBLE (0x0040)
#define BSMR_AN_COMPLETE (0x0020)
#define BSMR_REMOTE_FAULT (0x0010)
#define BSMR_AN_ABILITY (0x0008)
#define BSMR_LINK_STATUS (0x0004)
#define BSMR_JABBER_DETECT (0x0002)
#define BSMR_EXTENDED_CAP (0x0001)
/** @} */
/**
* @name Ethernet PHY PHYIDR1 Fields
*/
#define PHYIDR1_OUI (0xffff)
/**
* @name Ethernet PHY PHYIDR2 Fields
* @{
*/
#define PHYIDR2_OUI (0xfe00)
#define PHYIDR2_MODEL (0x01f0)
#define PHYIDR2_REV (0x0007)
/** @} */
/**
* @name Ethernet PHY ANAR Fields
* @{
*/
#define ANAR_NEXT_PAGE (0x8000)
#define ANAR_REMOTE_FAULT (0x2000)
#define ANAR_PAUSE (0x0600)
#define ANAR_100BASE_T4 (0x0200)
#define ANAR_100BASE_TX_FDUPLEX (0x0100)
#define ANAR_100BASE_TX_HDUPLEX (0x0080)
#define ANAR_10BASE_T_FDUPLEX (0x0040)
#define ANAR_10BASE_T_HDUPLEX (0x0020)
#define ANAR_SELECTOR (0x000f)
/** @} */
/**
* @name Ethernet PHY ANLPAR Fields
* @{
*/
#define ANLPAR_NEXT_PAGE (0x8000)
#define ANLPAR_ACK (0x4000)
#define ANLPAR_REMOTE_FAULT (0x2000)
#define ANLPAR_PAUSE (0x0600)
#define ANLPAR_100BASE_T4 (0x0200)
#define ANLPAR_100BASE_TX_FDUPLEX (0x0100)
#define ANLPAR_100BASE_TX_HDUPLEX (0x0080)
#define ANLPAR_10BASE_T_FDUPLEX (0x0040)
#define ANLPAR_10BASE_T_HDUPLEX (0x0020)
#define ANLPAR_SELECTOR (0x000f)
/** @} */
/**
* @name Ethernet PHY ANNPTR Fields
* @{
*/
#define ANNPTR_NEXT_PAGE (0x8000)
#define ANNPTR_MSG_PAGE (0x2000)
#define ANNPTR_ACK2 (0x1000)
#define ANNPTR_TOGGLE_TX (0x0800)
#define ANNPTR_CODE (0x03ff)
/** @} */
/**
* @name Ethernet PHY ANER Fields
* @{
*/
#define ANER_PDF (0x0010)
#define ANER_LP_NEXT_PAGE_ABLE (0x0008)
#define ANER_NEXT_PAGE_ABLE (0x0004)
#define ANER_PAGE_RX (0x0002)
#define ANER_LP_AN_ABLE (0x0001)
/** @} */
#ifdef __cplusplus
}
#endif

7
cpu/stm32/periph/eth.c
View File

@ -25,6 +25,7 @@
#include "bitarithm.h"
#include "iolist.h"
#include "luid.h"
#include "mii.h"
#include "mutex.h"
#include "net/ethernet.h"
#include "net/netdev/eth.h"
@ -150,7 +151,7 @@ static inline void _mii_reg_write(uint8_t reg, uint16_t value)
static inline bool _get_link_status(void)
{
return (_mii_reg_read(PHY_BSMR) & BSMR_LINK_STATUS);
return (_mii_reg_read(MII_BMSR) & MII_BMSR_LINK);
}
static void stm32_eth_get_addr(char *out)
@ -305,7 +306,7 @@ static int stm32_eth_init(netdev_t *netdev)
/* configure the PHY (standard for all PHY's) */
/* if there's no PHY, this has no effect */
_mii_reg_write(PHY_BMCR, BMCR_RESET);
_mii_reg_write(MII_BMCR, MII_BMCR_RESET);
/* speed from conf */
ETH->MACCR |= (ETH_MACCR_ROD | ETH_MACCR_IPCO | ETH_MACCR_APCS |
@ -351,7 +352,7 @@ static int stm32_eth_init(netdev_t *netdev)
/* configure speed, do it at the end so the PHY had time to
* reset */
_mii_reg_write(PHY_BMCR, eth_config.speed);
_mii_reg_write(MII_BMCR, eth_config.speed);
return 0;
}

24
drivers/include/mii.h
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@ -95,6 +95,30 @@ extern "C" {
#define MII_BMSR_EXTENDED BIT0 /**< Extended MII registers available */
/** @} */
/**
* @name Bits in the MII Extended Mode Advertisement Register
* @{
*/
#define MII_ADVERTISE_100_F BIT8 /**< Advertise 100BASE-T, full duplex */
#define MII_ADVERTISE_100_H BIT7 /**< Advertise 100BASE-T, half duplex */
#define MII_ADVERTISE_10_F BIT6 /**< Advertise 10BASE-T, full duplex */
#define MII_ADVERTISE_10_H BIT5 /**< Advertise 10BASE-T, half duplex */
#define MII_ADVERTISE_100 (BIT7 | BIT8) /**< Advertise 100BASE-T */
#define MII_ADVERTISE_10 (BIT5 | BIT6) /**< Advertise 10BASE-T */
/** @} */
/**
* @name Bits in the MII Extended Mode Advertisement Register
* @{
*/
#define MII_LPA_100_F BIT8 /**< Partner can 100BASE-T, full duplex */
#define MII_LPA_100_H BIT7 /**< Partner can 100BASE-T, half duplex */
#define MII_LPA_10_F BIT6 /**< Partner can 10BASE-T, full duplex */
#define MII_LPA_10_H BIT5 /**< Partner can 10BASE-T, half duplex */
#define MII_LPA_100 (BIT7 | BIT8) /**< Partner can 100BASE-T */
#define MII_LPA_10 (BIT5 | BIT6) /**< Partner can 10BASE-T */
/** @} */
/**
* @brief Check if an Ethernet PHY supports 100 Mbps at full duplex
*