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cpu/stm32_common: implement low-power modes for L4

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Alexandre Abadie 2019-03-13 10:46:57 +01:00
parent c391ed4109
commit 679fee7f9c
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GPG Key ID: 1C919A403CAE1405
2 changed files with 41 additions and 6 deletions
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2
cpu/stm32_common/include/periph_cpu_common.h
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@ -81,7 +81,7 @@ extern "C" {
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \ #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \ defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \ defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
defined(DOXYGEN) defined(CPU_FAM_STM32L4) || defined(DOXYGEN)
/** /**
* @brief Number of usable low power modes * @brief Number of usable low power modes
*/ */

45
cpu/stm32_common/periph/pm.c
View File

@ -3,6 +3,7 @@
* 2015 Freie Universität Berlin * 2015 Freie Universität Berlin
* 2015 Engineering-Spirit * 2015 Engineering-Spirit
* 2017-2019 OTA keys S.A. * 2017-2019 OTA keys S.A.
* 2019 Inria
* *
* This file is subject to the terms and conditions of the GNU Lesser * This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level * General Public License v2.1. See the file LICENSE in the top level
@ -21,6 +22,7 @@
* @author Kaspar Schleiser <kaspar@schleiser.de> * @author Kaspar Schleiser <kaspar@schleiser.de>
* @author Fabian Nack <nack@inf.fu-berlin.de> * @author Fabian Nack <nack@inf.fu-berlin.de>
* @author Vincent Dupont <vincent@otakeys.com> * @author Vincent Dupont <vincent@otakeys.com>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* *
* @} * @}
*/ */
@ -42,6 +44,10 @@
#define PM_STOP_CONFIG (PWR_CR_LPDS) #define PM_STOP_CONFIG (PWR_CR_LPDS)
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#define PM_STOP_CONFIG (PWR_CR_LPSDSR | PWR_CR_ULP) #define PM_STOP_CONFIG (PWR_CR_LPSDSR | PWR_CR_ULP)
#elif defined(CPU_FAM_STM32L4)
#define PM_STOP_CONFIG (PWR_CR1_LPMS_STOP1)
#elif defined(CPU_FAM_STM32F7)
#define PM_STOP_CONFIG (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS)
#else #else
#define PM_STOP_CONFIG (PWR_CR_LPDS | PWR_CR_FPDS) #define PM_STOP_CONFIG (PWR_CR_LPDS | PWR_CR_FPDS)
#endif #endif
@ -55,11 +61,31 @@
*/ */
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF | PWR_CR_ULP) #define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF | PWR_CR_ULP)
#elif defined(CPU_FAM_STM32L4)
#define PM_STANDBY_CONFIG (PWR_CR1_LPMS_STANDBY)
#elif defined(CPU_FAM_STM32F7)
#define PM_STANDBY_CONFIG (PWR_CR1_PDDS | PWR_CR1_CSBF)
#else #else
#define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF) #define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF)
#endif #endif
#endif #endif
#if defined(CPU_FAM_STM32L4)
#define PWR_CR_REG PWR->CR1
#define PWR_WUP_REG PWR->CR3
/* Allow overridable SRAM2 retention mode using CFLAGS */
#ifndef STM32L4_SRAM2_RETENTION
/* Disable SRAM2 retention by default for maximum power saving */
#define STM32L4_SRAM2_RETENTION (0)
#endif
#elif defined(CPU_FAM_STM32F7)
#define PWR_CR_REG PWR->CR1
#define PWR_WUP_REG PWR->CSR2
#else
#define PWR_CR_REG PWR->CR
#define PWR_WUP_REG PWR->CSR
#endif
void pm_set(unsigned mode) void pm_set(unsigned mode)
{ {
int deep; int deep;
@ -67,18 +93,27 @@ void pm_set(unsigned mode)
switch (mode) { switch (mode) {
#ifdef STM32_PM_STANDBY #ifdef STM32_PM_STANDBY
case STM32_PM_STANDBY: case STM32_PM_STANDBY:
PWR->CR &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG); PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
PWR->CR |= PM_STANDBY_CONFIG; PWR_CR_REG |= PM_STANDBY_CONFIG;
#if defined(CPU_FAM_STM32L4)
#if STM32L4_SRAM2_RETENTION
PWR->CR3 |= PWR_CR3_RRS;
#else
PWR->CR3 &= ~PWR_CR3_RRS;
#endif
/* Clear flags */
PWR->SCR |= PWR_SCR_CSBF;
#endif
/* Enable WKUP pin to use for wakeup from standby mode */ /* Enable WKUP pin to use for wakeup from standby mode */
PWR->CSR |= PM_EWUP_CONFIG; PWR_WUP_REG |= PM_EWUP_CONFIG;
/* Set SLEEPDEEP bit of system control block */ /* Set SLEEPDEEP bit of system control block */
deep = 1; deep = 1;
break; break;
#endif #endif
#ifdef STM32_PM_STOP #ifdef STM32_PM_STOP
case STM32_PM_STOP: case STM32_PM_STOP:
PWR->CR &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG); PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
PWR->CR |= PM_STOP_CONFIG; PWR_CR_REG |= PM_STOP_CONFIG;
/* Set SLEEPDEEP bit of system control block */ /* Set SLEEPDEEP bit of system control block */
deep = 1; deep = 1;
break; break;