From 4acceefa6589d31bcdf2c1dea17bcdb91f907eb7 Mon Sep 17 00:00:00 2001 From: francisco Date: Thu, 6 Jun 2019 11:07:34 +0200 Subject: [PATCH 1/2] cortexm_common/Makefile.include: set RIOTBOOT_HRD_LEN for cortex-m - Since the Vector table must be naturally aligned to the next power of two of the amount of supported ISR, and the table will be placed after riotboot_hdr, we must ensure RIOTBOOT_HRD_LEN has the same alignment. --- cpu/cortexm_common/Makefile.include | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/cpu/cortexm_common/Makefile.include b/cpu/cortexm_common/Makefile.include index f024eb56bf..4f68848e16 100644 --- a/cpu/cortexm_common/Makefile.include +++ b/cpu/cortexm_common/Makefile.include @@ -25,6 +25,33 @@ LINKFLAGS += $(if $(ROM_OFFSET),$(LINKFLAGPREFIX)--defsym=_rom_offset=$(ROM_OFFS # FW_ROM_LEN: rom length to use for firmware linking. Allows linking only in a section of the rom. LINKFLAGS += $(if $(FW_ROM_LEN),$(LINKFLAGPREFIX)--defsym=_fw_rom_length=$(FW_ROM_LEN)) +# Cortex-M0+/1/3/4/7 riotboot settings + +# From ARMv7-M (M4, M3, M7) architecture reference manual, section B1.5.3 +# https://static.docs.arm.com/ddi0403/e/DDI0403E_d_armv7m_arm.pdf +# "The Vector table must be naturally aligned to a power of two whose alignment +# value is greater than or equal to number of Exceptions supported x 4" + +# From ARMv6-M (M0, M0+, M1) architecture reference manual, section B1.5.3 +# https://static.docs.arm.com/ddi0419/d/DDI0419D_armv6m_arm.pdf +# "The table offset address that VTOR defines is 32-word aligned. Where more +# than 16 external interrupts are used, the offset word alignment must be +# increased to accommodate vectors for all the exceptions and interrupts +# supported and keep the required table size naturally aligned." + +# For reference on the max number in interrupts per processor look in The +# technical reference manual "Interrupt Controller Type Register, ICTR" section. +# * For M4, M3 & M7: Maximum of 256 exceptions (256*4 bytes == 0x400). +# * For M0, M0+ & M1: Maximum of 48 exceptions (48*4 bytes = 192 bytes ~= 0x100). + +# The values defined here are a theoretical maximum, in practice most cpu's +# CPU_IRQ_NUMOF value is around 100, in these cases the value can be reduced +# accordingly in the cpu Makefile.include, e.g: `kinetis/Makefile.include` +ifneq (,$(filter cortex-m2% cortex-m4% cortex-m3% cortex-m7%,$(CPU_ARCH))) + RIOTBOOT_HDR_LEN ?= 0x400 +else + RIOTBOOT_HDR_LEN ?= 0x100 +endif # Configure riotboot bootloader and slot lengths # 4KB are currently enough From 75efed16cb42703505c0c1b19afd2fa692a21e3f Mon Sep 17 00:00:00 2001 From: francisco Date: Tue, 18 Jun 2019 14:58:28 +0200 Subject: [PATCH 2/2] sys/riotboot: RIOTBOOT_HDR_LEN generic definition --- sys/riotboot/Makefile.include | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/sys/riotboot/Makefile.include b/sys/riotboot/Makefile.include index 4e2d9b6c62..56e5aa9952 100644 --- a/sys/riotboot/Makefile.include +++ b/sys/riotboot/Makefile.include @@ -1,6 +1,8 @@ -# Indicate the reserved space for a header, 256B by default -# Notice that it must be 256B aligned. This is restricted by -# the Cortex-M0+/3/4/7 architecture +# Indicate the reserved space for a header, 256B by default. +# The value must respect the cpu alignment requirements for the specific +# cpu, it can be re-defined in the cpu Makefile.include accordingly. +# e.g: `cortex-m` vector-table comes after `riotboot_hdr` and must be naturally +# aligned according to CPU_IRQ_NUMOF (ref: cpu/cortexm_common/Makefile.include) RIOTBOOT_HDR_LEN ?= 0x100 # By default, slot 0 is found just after RIOTBOOT_LEN. Slot 1 after